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ibm processor for network resources revision 2.5 databook preliminary ?
copyright and disclaimer ? copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america august 2000 the following are trademarks of international business machines corporation in the united states, or other coun- tries, or both. ibm ibm logo powerpc other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com pnr25.01 august 14, 2000 ?
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 3 contents features ...................................................................................................................... .... 21 description ................................................................................................................... .. 21 conventions ................................................................................................................... 22 standards compliance .................................................................................................. 23 environmental ratings .................................................................................................. 24 functional description .................................................................................................. 28 subsystem blocks .............................................................................................................. ................. 29 external architecture ......................................................................................................... .................. 30 internal architecture ......................................................................................................... ................... 31 logical channel support ....................................................................................................... .......... 31 virtual memory support ........................................................................................................ ........... 31 queues ........................................................................................................................ .................... 32 scheduling .................................................................................................................... ................... 32 system environment ............................................................................................................ ............... 34 data flows .................................................................................................................... .. 36 transmit path ................................................................................................................. ...................... 37 receive path .................................................................................................................. ....................... 39 input/output definitions ................................................................................................ 41 dram memory bus interface ..................................................................................................... ......... 41 dram memory bus interface ..................................................................................................... ......... 44 npbus ......................................................................................................................... .......................... 48 atm phy bus interface ......................................................................................................... .............. 51 data structures .............................................................................................................. 6 1 packet header ................................................................................................................. ..................... 61 transmit logical channel descriptor data structures .................................................................... 66 field definitions ............................................................................................................. .................. 74 receive lcd data structure and modes ........................................................................................ 78 raw lcd ....................................................................................................................... .................. 80 raw routed lcd ................................................................................................................ ............. 81 raw routed early drop lcd ..................................................................................................... ...... 82 raw scatter/cut-through lcd ................................................................................................... ..... 83 aal5 lcd ...................................................................................................................... .................. 84 aal5 routed lcd ............................................................................................................... ............ 85 aal5 cut-through/scatter mode lcd ............................................................................................ 8 6 packet lcd .................................................................................................................... ................. 87 packet routed lcd ............................................................................................................. ............ 88 packet cut-through scatter mode lcd .......................................................................................... 8 9 field definitions ............................................................................................................. .................. 90
IBM3206K0424 ibm processor for network resources preliminary page 4 nrm.toc.01 august 14, 2000 internal organization: entity descriptions ...................................................................93 note on set/clear type registers .............................................................................................. .....93 control processor bus interface entities ....................................................................93 the iop bus specific interface controller (pcint) ...........................................................................93 pci options taken ............................................................................................................. ..............93 pci target response ........................................................................................................... ...........93 pci master response ........................................................................................................... ...........93 pci master retry .............................................................................................................. ...............94 pcint config word 0 ........................................................................................................... ...........94 pcint config word 1 ........................................................................................................... ...........95 pcint config word 2 ........................................................................................................... ...........97 pcint config word 3 ........................................................................................................... ...........98 pcint base address 1 (i/o for register) ....................................................................................... .99 pcint base address 2 (mem for register) ...................................................................................101 pcint base addresses 3-6 (memory) ..........................................................................................103 pcint cardbus cis pointer ..................................................................................................... .....105 pcint subsystem id/vendor id .................................................................................................. ..106 pcint rom base address ........................................................................................................ ...107 capabilities pointer .......................................................................................................... ..............108 pcint config word 15 .......................................................................................................... ........109 pcint endian control register ................................................................................................. ....110 pcint base address control register ..........................................................................................1 11 pcint window offsets for base addresses 3-6 ...........................................................................113 pcint count timeout register .................................................................................................. ...114 pcint 64-bit control register ................................................................................................. ......116 pcint 64-bit enable register .................................................................................................. ......118 pcint perf counters control register .......................................................................................... 119 pcint perf counter 1 .......................................................................................................... ..........121 pcint perf counter 2 .......................................................................................................... ..........122 pci master options control .................................................................................................... .......123 power management program control ...........................................................................................125 message signaled interrupts-word 1 ............................................................................................ 127 message signaled interrupts-word 2 ............................................................................................ 128 message signaled interrupts-word 3 ............................................................................................ 129 message signaled interrupts-word 4 ............................................................................................ 130 power management interface-word 1 ...........................................................................................13 1 power management interface-word 2 ...........................................................................................13 2 vital product data interface-word 1 ........................................................................................... ...133 vital product data interface-word 2 ........................................................................................... ...134 interrupt and status/control (intst) .......................................................................................... ......135 intst interrupt 1 prioritized status .......................................................................................... .....135 intst interrupt 2 prioritized status .......................................................................................... .....136 intst control register ........................................................................................................ ..........137 intst interrupt source ........................................................................................................ ..........139 intst enable for interrupt 1 (minta) .......................................................................................... .140 intst enable for interrupt 2 (mint2) .......................................................................................... ..141 intst interrupt source without enables .......................................................................................1 41 intst cpb status .............................................................................................................. ...........142 intst cpb status enable ....................................................................................................... ......144 intst IBM3206K0424 halt enable ...............................................................................................1 44
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 5 intst cpb capture enable ...................................................................................................... .... 144 intst cpb captured address .................................................................................................... .. 145 intst general purpose timer pre-scaler .................................................................................... 145 intst general purpose timer compare ...................................................................................... 146 intst general purpose timer counter ........................................................................................ 146 intst general purpose timer status ........................................................................................... 1 47 intst general purpose timer mode control ............................................................................... 148 intst enable for pcore normal interrupt .................................................................................. 149 intst enable for pcore critical interrupt ................................................................................... 14 9 intst debug states control .................................................................................................... ..... 150 intst delayed interrupts dma system address 1 ....................................................................... 152 intst delayed interrupts dma system address 2 ....................................................................... 152 current pci master address counter for debug ........................................................................... 152 external entity states read ................................................................................................... ........ 153 dma queues (dmaqs) ............................................................................................................ ........ 154 dma descriptors ............................................................................................................... ............ 154 dma types and options ......................................................................................................... ...... 155 descriptor based dmas ......................................................................................................... ....... 156 register based dmas ........................................................................................................... ........ 156 polling, interrupts, or events ................................................................................................ ......... 156 error detection and recovery .................................................................................................. ..... 156 dma/queue scheduling options .................................................................................................. . 156 address size .................................................................................................................. ............... 156 data width .................................................................................................................... ................. 157 initialization of dmaqs ....................................................................................................... ........... 157 dmaqs lower bound registers ................................................................................................... 158 dmaqs upper bound registers ................................................................................................... 159 dmaqs head pointer registers .................................................................................................. . 160 dmaqs tail pointer registers .................................................................................................. .... 160 dmaqs length registers ........................................................................................................ ..... 161 dmaqs threshold registers ..................................................................................................... ... 161 dmaqs interrupt status ........................................................................................................ ........ 162 dmaqs interrupt enable ........................................................................................................ ....... 164 dmaqs control register ........................................................................................................ ...... 164 dmaqs enqueue dma descriptor primitive ................................................................................. 166 dmaqs source address register ................................................................................................ 1 66 dmaqs destination address register .......................................................................................... 16 7 dmaqs buffer address register ................................................................................................. . 167 dmaqs transfer count and flag register ................................................................................... 168 dmaqs system descriptor address ............................................................................................. 17 1 dmaqs checksum register ....................................................................................................... .. 171 dmaqs local descriptor range registers ................................................................................... 173 dmaqs event queue number register ....................................................................................... 173 dmaqs dma request size register ............................................................................................ 174 dmaqs enq fifo register ....................................................................................................... ... 174 general purpose dma (gpdma) ................................................................................................... ... 175 gpdma interrupt status ........................................................................................................ ........ 175 gpdma interrupt enable ........................................................................................................ ....... 176 gpdma control register ........................................................................................................ ...... 177 gpdma source address register ................................................................................................ 1 78 gpdma destination address register .......................................................................................... 17 9
IBM3206K0424 ibm processor for network resources preliminary page 6 nrm.toc.01 august 14, 2000 gpdma transfer count and flag register ...................................................................................179 gpdma dma max burst time ...................................................................................................... .181 gpdma maximum memory transfer count ..................................................................................181 gpdma checksum register ....................................................................................................... ..181 gpdma read dma byte count ....................................................................................................1 82 gpdma write dma byte count .................................................................................................... .182 gpdma array read address ...................................................................................................... ..182 gpdma array write address ..................................................................................................... ....183 gpdma array ................................................................................................................... .............183 memory controlling entities ........................................................................................184 the dram controllers (comet/pakit) ...........................................................................................1 84 memory reset sequence ......................................................................................................... .....185 comet/pakit control register .................................................................................................. ..186 comet/pakit status register ................................................................................................... ..189 comet/pakit interrupt enable register ......................................................................................190 comet/pakit lock enable register ...........................................................................................190 comet/pakit memory error address register ...........................................................................191 comet/pakit sdram command and status register ..............................................................192 comet/pakit dram refresh rate register ..............................................................................194 comet/pakit syndrome register ...............................................................................................19 5 comet/pakit checkbit inversion register ..................................................................................197 comet/pakit memory controller write enable register ............................................................197 comet/pakit memory configuration error sense register ........................................................198 atm virtual memory logic (vimem) .............................................................................................. ...200 vimem virtual memory base address ...........................................................................................20 0 on-chip memory base address ................................................................................................... .201 vimem control memory base address .........................................................................................201 vimem packet memory base address ..........................................................................................202 vimem virtual memory total bytes .............................................................................................. .203 vimem virtual/real memory buffer size .......................................................................................20 4 vimem packet memory offset .................................................................................................... ...205 vimem maximum buffer size ..................................................................................................... ...205 vimem access control register ................................................................................................. ...206 vimem access status register .................................................................................................. ...207 vimem access status interrupt enable register ..........................................................................209 vimem memory lock enable register ..........................................................................................209 vimem state machine current state ............................................................................................. 210 vimem last processor read real address ..................................................................................211 vimem virtual buffer segment size register ................................................................................212 vimem buffer map base address ................................................................................................. 214 vimem real buffer base addresses .............................................................................................2 15 atm packet/control memory arbitration logic (arbit) ................................................................217 arbit control priority resolution register high ...........................................................................217 arbit control priority resolution register low ............................................................................218 arbit control error mask register ............................................................................................. ..219 arbit control error source register ........................................................................................... .220 arbit control winner register ................................................................................................. ....221 arbit control address register a .............................................................................................. ..222 arbit control address register b .............................................................................................. ..222 arbit control length register ................................................................................................. ....223
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 7 arbit control lock entity enable register .................................................................................. 224 arbit control config register ................................................................................................. ..... 225 arbit packet priority resolution register high ........................................................................... 225 arbit packet priority resolution register low ............................................................................ 227 arbit packet entity error mask register ..................................................................................... 22 8 arbit packet error source register ............................................................................................ 229 arbit packet winner register .................................................................................................. ... 230 arbit packet address register a ............................................................................................... . 231 arbit packet address register b ............................................................................................... . 231 arbit packet length register .................................................................................................. .... 232 arbit packet lock entity enable register ................................................................................... 233 arbit packet config register .................................................................................................. .... 234 arbit performance counter control ............................................................................................ 2 35 arbit memory performance counter .............................................................................................. 237 the bus dram cache controller (bcach) ..................................................................................... 238 bcach control register ........................................................................................................ ....... 239 bcach status register ......................................................................................................... ....... 241 bcach interrupt enable register ............................................................................................... .. 242 bcach high priority timer value ............................................................................................... .. 242 bcach line tag registers ...................................................................................................... ..... 243 bcach line valid bytes register ............................................................................................... .. 244 bcach line status register .................................................................................................... ..... 245 bcach cache line array ........................................................................................................ ..... 246 buffer pool management (pools) ................................................................................................ ... 247 basic operation in real memory mode ......................................................................................... 24 7 basic operation in virtual memory mode ...................................................................................... 24 7 resource controls ............................................................................................................. ............ 247 virtual memory overview ....................................................................................................... ....... 248 pools get pointer primitive ................................................................................................... ..... 252 pools free pointer primitive .................................................................................................. ..... 253 pools common pools count registers ...................................................................................... 253 pools client thresholds array ................................................................................................. ... 254 pools user threshold and client active packet count array .................................................... 255 pools pointer queues dram head pointer offset address register ....................................... 256 pools pointer queues dram tail pointer offset address register .......................................... 257 pools pointer queues dram lower bound address register .................................................. 258 pools pointer queues dram upper bound register ................................................................ 259 pools pointer queues length registers .................................................................................... 261 pools interrupt enable register ............................................................................................... .. 261 pools event enables ........................................................................................................... ....... 262 pools event hysteresis register ............................................................................................... . 262 pools event data register ..................................................................................................... .... 263 pools status register ......................................................................................................... ........ 265 pools control register ........................................................................................................ ....... 267 pools buffer threshold registers 0-4 ........................................................................................ 26 9 pools index threshold registers 0-4 ......................................................................................... 26 9 pools last primitive trap register ............................................................................................ . 270 pools last buffer map read on free register .......................................................................... 270 pools error lock enable register .............................................................................................. 270 pools packet and control memory access threshold ............................................................... 271 pools buffer map group ........................................................................................................ ..... 271
IBM3206K0424 ibm processor for network resources preliminary page 8 nrm.toc.01 august 14, 2000 transmit data path entities .........................................................................................273 transmit buffer (csked) ....................................................................................................... ............273 scheduling overview ........................................................................................................... ..........273 operational description ....................................................................................................... ..........274 lcd initialization ............................................................................................................ ................274 a scheduling example .......................................................................................................... .........274 csked initialization .......................................................................................................... .............275 packet initialization ......................................................................................................... ...............276 scheduling options ............................................................................................................ ............276 abr scheduling ................................................................................................................ .............276 frame scheduling .............................................................................................................. ............276 path scheduling ............................................................................................................... ..............277 primitives .................................................................................................................... ...................277 enqueue ....................................................................................................................... ..................277 close connection .............................................................................................................. .............277 start/stop timer .............................................................................................................. ...............278 transmit enqueue primitive .................................................................................................... .......278 resume transmission primitive ................................................................................................. ...278 start/stop timer primitive .................................................................................................... ..........279 close connection primitive .................................................................................................... ........279 timeslot prescaler register ................................................................................................... ........280 current timeslot counter ...................................................................................................... .........280 csked control register ........................................................................................................ ........281 transmit segmentation throttle register ......................................................................................2 83 transmit segmentation throttle counter .......................................................................................2 84 mpeg conversion register ...................................................................................................... .....284 abr timer prescaler register .................................................................................................. .....285 rm cell timer ................................................................................................................. ...............285 csked lcd update data registers .............................................................................................28 6 csked lcd update mask registers ............................................................................................286 csked lcd update operation registers .....................................................................................287 drop access control register .................................................................................................. ......288 performance registers ......................................................................................................... .............289 high priority bandwidth limit register ........................................................................................ ...289 medium priority bandwidth limit register .....................................................................................2 90 low priority bandwidth limit register ......................................................................................... ..290 high priority cells transmitted counter ....................................................................................... ..291 medium priority cells transmitted counter ...................................................................................29 1 low priority cells transmitted counter ........................................................................................ .292 bytes queued counters ......................................................................................................... ........293 debugging register access ..................................................................................................... .........294 fast serviced counters ........................................................................................................ .........294 slow serviced counters ........................................................................................................ .........294 timer serviced counters ....................................................................................................... ........295 csked status register ......................................................................................................... ........296 csked interrupt enable register ............................................................................................... ...297 csked timing data array pointer ............................................................................................... .297 csked timing data array data .................................................................................................. ..298 csked time wheel array pointer ................................................................................................ 298 csked time wheel array data ................................................................................................... .299 csked lcd cache array pointer ................................................................................................. 299
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 9 csked lcd cache array data .................................................................................................... 300 csked congestion control register ............................................................................................ 3 00 state machine variables ....................................................................................................... ......... 301 atm transmit buffer segmentation (segbf) ................................................................................. 302 segbf software lcd enqueue .................................................................................................... 305 segbf control register ........................................................................................................ ....... 306 segbf status register ......................................................................................................... ........ 308 segbf invalid lcd register .................................................................................................... .... 309 segbf software lcd complete ................................................................................................... 310 segbf interrupt enable register ............................................................................................... .. 311 segbf programmable counters .................................................................................................. 3 11 segbf transmit lcd size ....................................................................................................... .... 312 segbf cell queue status ....................................................................................................... ..... 313 segbf processor 1 control/status .............................................................................................. 314 segbf processor 2 control/status .............................................................................................. 315 segbf programmable counter source specification .................................................................. 316 segbf cell staging array pointer .............................................................................................. .. 317 segbf cell staging array data ................................................................................................. ... 318 segbf instruction sram pointer ................................................................................................ . 318 segbf instruction sram data ................................................................................................... .. 319 mpeg-2 pcr increment register ................................................................................................. 319 receive data path entities .......................................................................................... 320 cell/packet re-assembly (reasm) ............................................................................................... ... 320 miscellaneous reassembly functions .......................................................................................... 32 2 atm oam cell processing ....................................................................................................... ..... 322 tcp/ip receive checksum verification ........................................................................................ 32 3 scatter/cut through receive processing ..................................................................................... 324 reasm logical channel descriptor base register ...................................................................... 328 reasm mode register ........................................................................................................... ...... 329 reasm reassembly modes register ........................................................................................... 330 reasm status register ......................................................................................................... ....... 331 reasm interrupt enable register ............................................................................................... .. 332 reasm debug state selector register ...................................................................................... 332 rxbuf functional description .................................................................................................. .... 333 rxbuf cell data buffer address ................................................................................................ .. 333 rxbuf cell data buffer read/write port ..................................................................................... 334 rxbuf cell info buffer address ................................................................................................ ... 334 rxbuf cell info buffer read/write port ....................................................................................... 3 34 rxbuf receive buffer threshold ................................................................................................ . 335 rxxlt functional description .................................................................................................. .... 336 rxxlt register array address port ............................................................................................. 340 rxxlt register array read/write port ........................................................................................ 34 0 rxxlt processor state selector ................................................................................................ .. 341 rxxlt processor state read/write port ...................................................................................... 341 rxxlt instruction array address port .......................................................................................... 342 rxxlt instruction array read/write port ..................................................................................... 34 2 rxxlt last lcd index register ................................................................................................. .. 343 rxcrc functional description .................................................................................................. ... 344 rxcrc instruction array address port ......................................................................................... 3 44 rxcrc instruction array read/write port .................................................................................... 345
IBM3206K0424 ibm processor for network resources preliminary page 10 nrm.toc.01 august 14, 2000 rxcrc processor state selector ................................................................................................ .345 rxcrc processor state read/write port .....................................................................................346 rxcrc last lcd index register ................................................................................................. .346 rxcrc checksum protocol registers ..........................................................................................346 rxaal functional description .................................................................................................. .....347 rxaal instruction array address port .......................................................................................... 348 rxaal instruction array read/write port .....................................................................................34 8 rxaal processor state selector ................................................................................................ ..349 rxaal processor state read/write port ......................................................................................349 rxaal last lcd index register ................................................................................................. ..350 rxaal transmit queue length compression configuration ........................................................351 rxaal packet header configuration ............................................................................................3 52 rxaal error count register .................................................................................................... .....353 rxaal dropped count register .................................................................................................. .354 rxaal maximum sdu length register ........................................................................................354 rxaal oam lcd information register ........................................................................................354 rxall - scatter/cut through info registers .................................................................................355 rxall - scatter/cut through flag registers ................................................................................358 rxlcd functional description .................................................................................................. ....359 rxlcd cache data array address port .......................................................................................359 rxlcd cache data array read/write port ...................................................................................360 rxlcd cache line info registers ............................................................................................... .360 rxlcd mode register ........................................................................................................... .......361 rxrto functional description .................................................................................................. ....362 reassembly timeout (rto) processing ....................................................................................362 rxrto lcd update data registers .............................................................................................36 3 rxrto lcd update mask registers ............................................................................................363 rxrto lcd update op registers ................................................................................................3 64 rxrto rto lcd table bound registers ....................................................................................364 rxrto reassembly timeout value register ...............................................................................365 rxrto reassembly timeout pre-scaler register .......................................................................365 receive queues (rxque) ........................................................................................................ .........366 functional description ........................................................................................................ ...........366 receive queue interface ....................................................................................................... ........366 aal5 packet events ............................................................................................................ ..........370 cell events ................................................................................................................... ..................371 lc events ..................................................................................................................... .................372 abr events .................................................................................................................... ................372 rxque structure ............................................................................................................... ............377 rxque initialization .......................................................................................................... ............377 rxque event routing ........................................................................................................... ........378 rxque normal operation ........................................................................................................ .....379 rxque queue full operation .................................................................................................... ...379 rxque event timestamping ...................................................................................................... ..380 rxque system receive queues ..................................................................................................3 80 rxque lower bound registers ................................................................................................... .382 rxque properties registers .................................................................................................... .....383 rxque head pointer registers .................................................................................................. ..386 rxque tail pointer registers .................................................................................................. .....387 rxque length registers ........................................................................................................ ......388 rxque threshold registers ..................................................................................................... ....389
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 11 rxque dequeue registers ....................................................................................................... ... 390 rxque enqueue registers ....................................................................................................... ... 391 rxque next lower bound registers ........................................................................................... 392 rxque last event dropped register ........................................................................................... 39 3 rxque timestamp register ...................................................................................................... ... 393 rxque timestamp pre-scaler register ....................................................................................... 393 rxque timestamp shift register ................................................................................................ 394 rxque event routing registers ................................................................................................. . 394 rxque event latency timer register ......................................................................................... 395 rxque queues status register .................................................................................................. . 396 rxque interrupt enable registers .............................................................................................. . 397 rxque status and enabled status registers .............................................................................. 398 rxque control register ........................................................................................................ ....... 400 debugging register access ..................................................................................................... ..... 401 rxque rxq state machine variable register ............................................................................ 401 rxque rxq enq state machine variable register .................................................................... 401 rxque enq fifo head ptr register ............................................................................................ 40 2 rxque enq fifo tail ptr register .............................................................................................. 402 rxque enq fifo array .......................................................................................................... ...... 402 phy level interfaces ................................................................................................... 403 the phy interface (linkc) ..................................................................................................... ........... 403 functional description ........................................................................................................ ........... 403 multi-drop .................................................................................................................... .................. 403 pos-phy ....................................................................................................................... ............... 403 moving cells to and from the IBM3206K0424 ............................................................................. 404 linkc global control register ................................................................................................. ..... 404 linkc configuration 0 transmit & receive control register ....................................................... 407 linkc configuration 1 transmit & receive control register ....................................................... 410 linkc configuration 2 transmit & receive control register ....................................................... 413 linkc configuration 3 transmit & receive control register ....................................................... 416 linkc map transmit configurations to port addresses ............................................................... 419 linkc map receive configurations to port addresses ................................................................ 420 linkc transmitted hec control byte ........................................................................................... 4 21 linkc interrupt/status register ............................................................................................... ..... 422 linkc interrupt enable register ............................................................................................... .... 424 linkc prioritized interrupts .................................................................................................. ......... 424 linkc transmit state machine register ....................................................................................... 42 5 linkc receive state machine register ........................................................................................ 42 5 linkc lan address register .................................................................................................... ... 426 linkc canonical lan address register ...................................................................................... 426 linkc passed tx data register ................................................................................................. . 427 nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data ............................................................................................................... ......... 428 npbus control register ........................................................................................................ ....... 428 npbus status register ......................................................................................................... ........ 431 npbus interrupt enable register ............................................................................................... .. 432 npbus eprom address/command register .............................................................................. 433 npbus eprom data register ..................................................................................................... 434 phy 1 registers ............................................................................................................... ............. 434 phy 2 registers ............................................................................................................... ............. 434
IBM3206K0424 ibm processor for network resources preliminary page 12 nrm.toc.01 august 14, 2000 hardware protocol assist entities ..............................................................................435 on-chip checksum and dram test support (chksm) ..................................................................435 functional description ........................................................................................................ ...........435 chksm base address register ................................................................................................... .435 chksm read/write count register ..............................................................................................4 36 chksm tcp/ip checksum data register ....................................................................................437 chksm ripple base register .................................................................................................... ...437 chksm ripple limit register ................................................................................................... .....438 chksm interrupt enable register ............................................................................................... ..438 chksm status register ......................................................................................................... .......439 chksm control register ........................................................................................................ .......440 debugging register access ..................................................................................................... ......441 chksm internal state .......................................................................................................... ..........441 software use of chksm ......................................................................................................... ......442 running a tcp/ip checksum in packet/control memory ..............................................................443 processor core (pcore) ........................................................................................................ ..........444 dcr interface ................................................................................................................. ...............444 interrupt controller .......................................................................................................... ...............444 bridge-address translation .................................................................................................... .......444 ocm sram ...................................................................................................................... .............444 control memory ................................................................................................................ .............444 packet memory ................................................................................................................. .............444 pci master interface-external ................................................................................................. .......444 processor register space ...................................................................................................... .......444 address translation examples .................................................................................................. ....445 cobra structure ............................................................................................................... ...............445 cobra core "glossy" description ............................................................................................... ....446 features ...................................................................................................................... ...................446 interfaces .................................................................................................................... ...................448 performance ................................................................................................................... ...............449 instruction set ............................................................................................................... .................449 cobra instruction overview .................................................................................................... ........449 cobra facilities overview ..................................................................................................... .........450 cobra specific register definitions ........................................................................................... ....455 hardware implementation detail 0 register (hid0) .......................................................................456 machine state register (msr) .................................................................................................. ....458 exception status register (esr) ............................................................................................... ....460 machine check enable register (mchk) ......................................................................................461 pcore register definitions .................................................................................................... ......463 pcore control register ........................................................................................................ .......463 pcore reset control register .................................................................................................. ...466 pcore status register ......................................................................................................... ........467 pcore user status register .................................................................................................... ....468 pcore cobra core external status register ...............................................................................469 pcore cobra core external machine check status register .....................................................471 pcore jtag debug control register .........................................................................................473 pcore jtag debug status register ...........................................................................................474 pcore jtag instruction stuff buffer ........................................................................................... 475 pcore jtag debug data register .............................................................................................476 pcore cobra core boot address ................................................................................................4 77 pcore cobra core access priority control register ...................................................................478
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 13 pcore transaction dead man timer value registers ................................................................ 480 pcore high priority access timer value registers .................................................................... 481 pcore transaction dead man timer register ............................................................................ 481 pcore IBM3206K0424 shadow status register ........................................................................ 481 pcore IBM3206K0424 packet last write with error address .................................................... 482 pcore IBM3206K0424 rxque master status register ............................................................. 482 pcore IBM3206K0424 rxque enabled status register 1 ....................................................... 482 pcore IBM3206K0424 rxque enabled status register 2 ....................................................... 483 pcore IBM3206K0424 rxque upper queues status register ................................................ 483 pcore IBM3206K0424 rxque lower queues status register ................................................ 483 pcore dmaqs master status register ...................................................................................... 484 pcore dmaqs enabled status register .................................................................................... 484 pcore rxque queue length registers .................................................................................... 484 pcore dmaqs queue length registers .................................................................................... 485 pcore interrupt enable register ............................................................................................... .. 485 pcore user interrupt enable ................................................................................................... .... 485 pcore cobra core interrupt enable register ............................................................................. 486 pcore cobra core external machine check enable register .................................................... 486 pcore error lock enable register .............................................................................................. 486 pcore user error lock enable register ..................................................................................... 487 pcore rxque event interface enqueue register ..................................................................... 487 pcore dmaqs dma enqueue register ..................................................................................... 487 pcore rxque event interface deque register ......................................................................... 488 pcore cobra spr read data access register ......................................................................... 488 pcore cobra spr write data access register .......................................................................... 488 pcore cobra spr access address register ............................................................................. 489 pcore address translation offset address facilities ................................................................. 490 pcore pci 64 bit address translation facilities ......................................................................... 491 pcore pci master target tag controls ...................................................................................... 492 pcore last packet address register ......................................................................................... 494 pcore last control address register ......................................................................................... 49 4 pcore last pci lower address register .................................................................................... 494 pcore last register address register ....................................................................................... 495 pcore sram base address ....................................................................................................... 495 pcore read data transfer buffers ............................................................................................. 4 96 pcore write data transfer buffers ............................................................................................. 496 pcore polling register ........................................................................................................ ........ 497 pcore integer input rate conversion register .......................................................................... 497 pcore abr output rate register ............................................................................................... 4 98 pcore debug states control .................................................................................................... .. 498 pcore debug states config ..................................................................................................... ... 499 powerpc on-chip memory (ppocm) entity .................................................................................... 500 dma controller ................................................................................................................ .............. 500 ppocm control register ........................................................................................................ ...... 500 ppocm status register ......................................................................................................... ....... 501 ppocm interrupt enable register ............................................................................................... . 502 ppocm dma off-chip effective address register ....................................................................... 502 ppocm dma on-chip effective address register ....................................................................... 503 ppocm dma length register ..................................................................................................... . 504 ppocm dma timeout timer register .......................................................................................... 504
IBM3206K0424 ibm processor for network resources preliminary page 14 nrm.toc.01 august 14, 2000 rs-232 interface logic (rs-232) ............................................................................................... ........505 rs-232 interface logic registers .............................................................................................. ....505 rs-232 control register ....................................................................................................... .........505 rs-232 status register ........................................................................................................ .........506 rs-232 interrupt enable register .............................................................................................. ....507 rs-232 transmit buffer ........................................................................................................ .........507 rs-232 receive buffer ......................................................................................................... .........508 rs-232 baud rate register ..................................................................................................... .....508 rs-232 cts/dsr glitch timer rate .............................................................................................5 09 rs-232 reset register ......................................................................................................... .........509 rs-232 error forcing register ................................................................................................. .....510 reset and power-on logic (crset) .............................................................................................. ...511 reset and power-on logic registers ............................................................................................ 511 reset status register ......................................................................................................... ...........511 software reset enable register ................................................................................................ ....512 software reset register ....................................................................................................... .........512 memory type register .......................................................................................................... .........513 crset pll range debug ......................................................................................................... ...514 crset control register ........................................................................................................ ........515 clock control register (nibble aligned) ....................................................................................... .516 cbist prpg results ............................................................................................................ ........518 cbist misr results ............................................................................................................ .........518 cbist bist rate ............................................................................................................... ............518 cbist prpg expected signature ................................................................................................. 518 cbist misr expected signature ................................................................................................. .519 cbist cyct load value ......................................................................................................... .....519 jtag interface logic (cjtag) .................................................................................................. ........520 scanning ...................................................................................................................... ..................520 instruction format ............................................................................................................ ..............521 instructions .................................................................................................................. ...................522 idcode ........................................................................................................................ .................522 sample/preload ................................................................................................................ ......522 extest ........................................................................................................................ .................522 bypass ........................................................................................................................ .................522 runbist ....................................................................................................................... ................523 bist_results .................................................................................................................. ..........523 walnut_mode ................................................................................................................... ........523 compliant_mode ................................................................................................................ .....523 stop .......................................................................................................................... ...................523 scan .......................................................................................................................... ...................523 scan_in ....................................................................................................................... ................524 scan_out ...................................................................................................................... .............524 private_rw1 ................................................................................................................... ...............524 private_rw2 ................................................................................................................... ...............524 private_rw3 ................................................................................................................... ...............524
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 15 sonet framer core (framr chiplet address mapping) .......................................... 525 gppint architecture ........................................................................................................... ............... 525 overview ...................................................................................................................... .................. 525 reset register ................................................................................................................ ............... 525 interrupt registers ........................................................................................................... .............. 525 handshaking error registers ................................................................................................... ..... 526 clock monitor status registers ................................................................................................ ..... 526 local gppint configuration registers .......................................................................................... .. 526 global static configuration registers ......................................................................................... ... 526 status registers .............................................................................................................. .............. 526 gppint register description ................................................................................................... ......... 528 chiplet reset register (resgp) ................................................................................................ ... 528 chiplet interrupt and mask registers (irqgp1 (irmgp1)) .......................................................... 529 handshaking error indication and mask registers (hshake1) ..................................................... 530 clock monitor status and mask registers (clkstat1 (clkmask1)) ................................................ 531 clock monitor test period register (cmongp1) ........................................................................... 532 watchdog timer period register (wdtgp1) ................................................................................ 532 gppint local configuration registers (confgp1) ....................................................................... 533 vital macro data register (vpd) ............................................................................................... .... 534 static configuration register (gatmcs) ...................................................................................... 53 4 gcasc ......................................................................................................................... ................... 535 glooptx ....................................................................................................................... ................. 535 glooprx ....................................................................................................................... ................ 536 gextres ....................................................................................................................... ................. 536 ofptxgp ....................................................................................................................... .............. 537 ofprxgp1 ...................................................................................................................... ............. 537 ofprxgp2 ...................................................................................................................... ............. 538 pimrconf2 ..................................................................................................................... ............... 538 simstat ....................................................................................................................... ................... 539 gpphandler architecture ....................................................................................................... ........... 540 overview ...................................................................................................................... .................. 540 counter registers ............................................................................................................. ............. 540 reset registers ............................................................................................................... .............. 540 command registers ............................................................................................................. ......... 540 event latch registers ......................................................................................................... .......... 541 interrupt registers ........................................................................................................... .............. 541 configuration registers ....................................................................................................... .......... 541 register types ................................................................................................................ .............. 541 atm cell handler architecture : transmit direction ...................................................................... 542 ach tx register description ................................................................................................... ......... 543 counter registers ............................................................................................................. ............. 543 rofmid ........................................................................................................................ ................. 543 rofhi ......................................................................................................................... ................... 543 acbc .......................................................................................................................... ................... 544 iuc ........................................................................................................................... ..................... 544 acbe .......................................................................................................................... ................... 545 acbeth11 ...................................................................................................................... ............... 546 cnten1 ........................................................................................................................ ................... 546 reset register (reset) ........................................................................................................ ....... 547 status registers .............................................................................................................. .............. 548 stat1 ......................................................................................................................... .................. 548
IBM3206K0424 ibm processor for network resources preliminary page 16 nrm.toc.01 august 14, 2000 iucstat1 ...................................................................................................................... ................549 interrupt request and mask registers .......................................................................................... 549 mainirq ....................................................................................................................... ..................549 m_mainirq ..................................................................................................................... ...............550 cntrirq1 ...................................................................................................................... ..................551 m_cntrirq1 .................................................................................................................... ...............552 configuration registers ....................................................................................................... ..........553 celltenable ................................................................................................................... ...........553 acbtxthrpae ................................................................................................................... .........554 sdbtxthrpaf ................................................................................................................... ..........554 headerbyte1 ................................................................................................................... ..........555 headerbyte2 ................................................................................................................... ..........555 headerbyte3 ................................................................................................................... ..........556 headerbyte4 ................................................................................................................... ..........556 headerbyte5 ................................................................................................................... ..........557 payloadbyte ................................................................................................................... ..........557 hecenctrl ..................................................................................................................... ............558 hecoffset ..................................................................................................................... ............559 hecmaskand .................................................................................................................... ..........559 hecmaskor ..................................................................................................................... ...........560 atm cell handler architecture: receive direction .........................................................................561 ach_rx register description ................................................................................................... .....562 counter registers ............................................................................................................. .............562 rofmid ........................................................................................................................ ..................562 rofhi ......................................................................................................................... ....................562 fhr ........................................................................................................................... .....................563 ihr ........................................................................................................................... ......................563 ehr1 .......................................................................................................................... ...................564 ehr1th11 ...................................................................................................................... ...............564 eht1th12 ...................................................................................................................... ................565 bhr ........................................................................................................................... ....................565 bhrth11 ....................................................................................................................... ................566 bhrth12 ....................................................................................................................... ................566 cnten1 ........................................................................................................................ ...................567 reset register (reset) ........................................................................................................ ........568 command register (cmd1) ....................................................................................................... ...568 status register (stat1) ....................................................................................................... .........569 interrupt request and mask registers .......................................................................................... 570 mainirq ....................................................................................................................... ..................570 m_mainirq ..................................................................................................................... ...............571 cntrirq1 ...................................................................................................................... ..................572 m_cntrirq1 .................................................................................................................... ...............573 configuration registers ....................................................................................................... ..........574 conf5 ......................................................................................................................... ..................574 conf6 ......................................................................................................................... ..................575 confc ......................................................................................................................... .................575 h1conf ........................................................................................................................ ................576 h2conf ........................................................................................................................ ................576 h3conf ........................................................................................................................ ................577 h4conf ........................................................................................................................ ................577 h5conf ........................................................................................................................ ................578
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 17 overhead frame processor architecture: transmit direction ...................................................... 579 ofp_tx register description ................................................................................................... ..... 582 counter registers ............................................................................................................. ............. 582 ptrinc ........................................................................................................................ ................. 582 ptrdec ........................................................................................................................ ................ 582 nd_evcnt ...................................................................................................................... ............. 583 juscnt ........................................................................................................................ ................ 583 juscntth11 .................................................................................................................... ............ 584 cnten1 ........................................................................................................................ ................... 584 reset register (reset) ........................................................................................................ ....... 585 command register (cmd1) ....................................................................................................... ... 586 status registers .............................................................................................................. .............. 587 stat1 ......................................................................................................................... .................. 587 stat2 ......................................................................................................................... .................. 587 interrupt and mask registers .................................................................................................. ...... 588 mainirq ....................................................................................................................... ................. 588 m_mainirq ..................................................................................................................... .............. 589 cntrirq1 ...................................................................................................................... ................. 590 m_cntrirq1 .................................................................................................................... .............. 591 irq3 .......................................................................................................................... .................... 592 m_irq3 ........................................................................................................................ ................. 593 configuration registers ....................................................................................................... .......... 594 conf1 ......................................................................................................................... ................. 594 conf2 ......................................................................................................................... ................. 595 conf3 ......................................................................................................................... ................. 595 conf4 ......................................................................................................................... ................. 596 conf5 ......................................................................................................................... ................. 596 conf6 ......................................................................................................................... ................. 597 conf7 ......................................................................................................................... ................. 598 conf8 ......................................................................................................................... ................. 598 conf9 ......................................................................................................................... ................. 599 conf10 ........................................................................................................................ ................ 599 overhead frame processor architecture: receive direction ........................................................ 600 counter registers ............................................................................................................. ............. 604 rofmid ........................................................................................................................ ................. 604 b1bitcnt ...................................................................................................................... ............... 604 b1bitcntth11 .................................................................................................................. ........... 605 b1bitcntth12 .................................................................................................................. ........... 605 b1blkcnt ...................................................................................................................... .............. 606 b1blkcntth11 .................................................................................................................. .......... 606 b1blkcntth12 .................................................................................................................. .......... 607 b2bitcnt ...................................................................................................................... ............... 607 b2bitcntth11 .................................................................................................................. ........... 608 b2bitcntth12 .................................................................................................................. ........... 608 b2bitcntth21 .................................................................................................................. ........... 609 b2bitcntth22 .................................................................................................................. ........... 609 b2blkcnt ...................................................................................................................... .............. 610 b2blkcntth11 .................................................................................................................. .......... 610 b2blkcntth12 .................................................................................................................. .......... 611 b2blkcntth21 .................................................................................................................. .......... 611 b2blkcntth22 .................................................................................................................. .......... 612
IBM3206K0424 ibm processor for network resources preliminary page 18 nrm.toc.01 august 14, 2000 b3bitcnt ...................................................................................................................... ................612 b3bitcntth11 .................................................................................................................. ...........613 b3bitcntth12 .................................................................................................................. ...........613 b3blkcnt ...................................................................................................................... ..............614 b3blkcntth11 .................................................................................................................. ..........614 b3blkcntth12 .................................................................................................................. ..........615 msreicnt ...................................................................................................................... ..............615 msreicntth11 .................................................................................................................. ..........616 msreicntth12 .................................................................................................................. ..........616 hpreicnt ...................................................................................................................... ...............617 hpreicntth11 .................................................................................................................. ..........617 hpreicntth12 .................................................................................................................. ..........618 pj_evcnt ...................................................................................................................... ...............618 nj_evcnt ...................................................................................................................... ..............619 nd_evcnt ...................................................................................................................... ..............619 cnten1 ........................................................................................................................ ...................620 cnten2 ........................................................................................................................ ...................621 reset register (reset) ........................................................................................................ ........622 status registers .............................................................................................................. ...............622 stat1 ......................................................................................................................... ...................622 stat2 ......................................................................................................................... ...................623 stat3 ......................................................................................................................... ...................624 stat4 ......................................................................................................................... ...................625 interrupt and mask registers .................................................................................................. .......626 mainirq ....................................................................................................................... ..................626 m_mainirq ..................................................................................................................... ...............627 cntrirq1 ...................................................................................................................... ..................628 m_cntrirq1 .................................................................................................................... ...............629 cntrirq2 ...................................................................................................................... ..................630 m_cntrirq2 .................................................................................................................... ...............631 cntrirq3 ...................................................................................................................... ..................632 m_cntrirq3 .................................................................................................................... ...............633 irq6 .......................................................................................................................... .....................634 m_irq6 ........................................................................................................................ ..................635 irq7 .......................................................................................................................... .....................636 m_irq7 ........................................................................................................................ ..................637 irq8 .......................................................................................................................... .....................638 m_irq8 ........................................................................................................................ ..................639 configuration registers ....................................................................................................... ..........640 conf1 ......................................................................................................................... ..................640 conf2 ......................................................................................................................... ..................641 conf3 ......................................................................................................................... ..................642 conf4 ......................................................................................................................... ..................643 conf7 ......................................................................................................................... ..................644 conf8 ......................................................................................................................... ..................645 conf9 ......................................................................................................................... ..................645
IBM3206K0424 preliminary ibm processor for network resources nrm.toc.01 august 14, 2000 page 19 memory map for registers and arrays ...................................................................... 647 signal pin listing by signal name ............................................................................. 648 ac timing characteristics .......................................................................................... 653 synchronous dram timing diagrams ............................................................................................ 65 6 sram timing diagrams .......................................................................................................... .......... 666 eprom timing diagrams ......................................................................................................... ......... 670 phy timing diagrams ........................................................................................................... ............. 674 revision log ................................................................................................................ 67 6
IBM3206K0424 ibm processor for network resources preliminary page 20 nrm.toc.01 august 14, 2000
pnr25.chapt01.01 august 14, 2000 IBM3206K0424 preliminary ibm processor for network resources features page 21 of 676 features ? supports multiple protocols, including atm, pos, frame relay, and 10/100/gigabit ethernet has a customizable on-chip 133 mhz pow- erpc ? processor core manages up to 65535 simultaneous logical channels, individually or in groups integrated 155 mb/s sonet (synchronous optical network) framer for simpler, low band- width designs flexible atm forum-compliant utopia ii inter- face with up to four phys switch interface extensions pci 32/64-bit interface up to 66mhz. configurable for sustained performance through the subsystem: - 155mb/s full duplex internal sonet framer - 622mb/s full duplex using an external sonet framer - 622mb/s across up to four full duplex 155mb/s links using an external quad framer jtag test interface package: 624 lead, 32 mm x 32 mm cbga power supply: 2.6 v 2%; 3.3 v 5%. description the ibm processor for network resources (IBM3206K0424) is an asynchronous transfer mode (atm) support device. it is an interface and translator between a peripheral component inter- connect (pci) bus and an atm utopia or similar interface to an atm phy. the IBM3206K0424 has an integrated packet/frame memory (dram con- troller) and performs segmentation and reassembly (sar) functions for several of the atm adaptation layers (aals). the IBM3206K0424 functions are illustrated in the block diagram on page 21. a net- work interface card example is shown in system context of an atm subsystem on page 34. block diagram (see page 29 for descriptions of subsystems) virtual/real memory interfaces each supports up to 4mb sram or 128mb dram dma engine phy interface sar transmit queuing interface powerpc ? 133mhz (abr & user fxn) 66mhz pci bus interface control bus control memory packet memory eprom (init) cell scheduling & segmentation cell buffering frame reassembly receive queuing interface ibm processor for network resources sonet framer (155mb/s) utopia (622mb/s) .
IBM3206K0424 ibm processor for network resources preliminary conventions page 22 of 676 pnr25.chapt01.01 august 14, 2000 conventions the bit notation is non-ibm, meaning that bit zero is the least significant bit and bit 31 is the most significant bit for a four-byte word. the internal addressing view of the IBM3206K0424 registers and memory is big endian. in most cases, a sys- tem will wire its pci bus interface to make the register view transparent, that is, the most significant bit in this specification will be the most significant bit in the register. if registers are read and written 32 bits at a time (which is the only way to access many of the registers), the endian-ness should not be a programming issue with respect to the registers. the IBM3206K0424 dma controller can transfer data in either big endian or little endian mode. see general purpose dma (gpdma) on page 175 for details. numeric notation is as follows: hexadecimal values are usually preceeded by x or x. for example: x ? 0b00 ? . for individual registers, address values are hexadecimal without any special markings. for example, xxxx 1c3c. binary values in text are either spelled out (zero and one) or appear in quotation marks. for example: ? 10101 ? . binary values in the default and description columns of the register sections are often isolated from text as in this example: 0: no action on read access 1: auto-reset interrupt request register upon read access ordering information part number description IBM3206K0424 network resource manager
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 standards compliance page 23 of 676 standards compliance the ibm processor for network resources, part number IBM3206K0424, has been designed with a number of standards in mind. these standards are listed below, grouped according to the area of IBM3206K0424 functionality they address. network (defined by itu-ts (formerly ccitt), ansi and atm forum) - itu recommendation i-361 - b-isdn atm layer specification - itu recommendation i.362 - b-isdn atm adaptation layer (aal) functional description - itu recommendation i.363 - b-isdn atm adaptation layer (aal) specification - itu recommendation i.413 - b-isdn user-network interface - itu recommendation i-432 - b-isdn user-network interface - physical layer specification - itu recommendation i-610 - oam principles of b-isdn access - ansi t1.atm-199x draft, broadband isdn - atm layer functionality and specification - ansi t1.cbr-199x draft, broadband isdn - atm adaptation layer for constant bit rate service functionality and specification - atm forum 93-620r2 - atm user-network interface specification - version 2.3 (july 27, 1993) - bellcore ta-nwt-001248 generic requirements for operations of broadband switching systems (october 1993) system interface - pci local bus specification, production version, revision 2.1, june 1, 1995. interface technical ref- erence, 11/89, part number 15f2160 phy interface - saturn user network interface, pmc-sierra, inc., february 1995 - atm forum 93-727 an atm phy data path interface, version 2.01, march 24, 1994 - am7968/am7969 taxichip(tm) handbook, transparent asynchronous transmitter/receiver inter- face, published by advanced micro devices, 1994
IBM3206K0424 ibm processor for network resources preliminary standards compliance page 24 of 676 pnr25.chapt01.01 august 14, 2000 environmental ratings absolute maximum ratings parameter rating unit note supply voltage, v dd 1 2.3 to 2.7 v 1 supply voltage, v dd 2 3.0 to 3.6 v 1 storage temperature -65 to 150 c 1 ambient temperature with power applied -40 to 100 c 1 1. these are the maximum ratings that can be applied to the device without damage. the device function and specifications are va lid only within the recommended operating conditions. recommended operating conditions parameter rating unit junction temperature 0 to 85 c supply voltage, v dd 1, with respect to ground 2.6 2% v supply voltage, v dd 2, with respect to ground 3.3 5% v power dissipation parameter rating unit v dd 1 (nominal) 6w v dd 2 (nominal) 2w
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 standards compliance page 25 of 676 package diagram this view 1.75 min 2.15 max also no ball a01 locator IBM3206K0424 linear tolerances: +- 0.5mm top view 0.9 0.1 side view 32.5mm 32.5mm
IBM3206K0424 ibm processor for network resources preliminary standards compliance page 26 of 676 pnr25.chapt01.01 august 14, 2000 pinout viewed from above
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 standards compliance page 27 of 676 dataflow te st entities crset cbist sclck cjtag phy bus interface npbus interrupt status intst checksum chksm pci interface pcint processor core pcore dma queues dmaqs general dma gpdma bus cache bcach rxq mgmt rxque eprom access/ phy control pci bus pci master interface internal memory bus segmentation segbf reassembly reasm arbiter arbit virtual vimem memory pools control pools control mem controller packet mem controller sonet framer framr async cell interface linkc memory cell csked scheduler control memory packet memory serial interface 8/16 bit phy interface
IBM3206K0424 ibm processor for network resources preliminary standards compliance page 28 of 676 pnr25.chapt01.01 august 14, 2000 functional description the IBM3206K0424 has been designed by breaking the implementation of the various functions and data- flows into separate entities (major functional units). this processor acts as a conversion unit from a bus memory interface (which is work queue oriented) to a phy level atm. to accomplish this, the IBM3206K0424 contains the major functional units listed below and shown in the dataflow on page 27. control processor bus interface memory control transmit data path receive data path phy level interfaces hardware protocol assist base device functions pcint pci interface entity intst interrupt status entity gpdma general purpose dma entity dmaqs queue control for dma activity memry dram controlling entity containing the comet (control) and pakit (packet) memory controllers vimem virtual memory controller arbit memory subsystem requestor arbitration bcach bus cache entity pools memory pool manager csked cell scheduler segbf cell segmentation entity reasm cell re-assembly entity raall aal processor rxque receive queue manager linkc asynchronous physical layer interface npbus nodal processor bus interface framr full sonet framing support logic chksm tcp/ip checksum logic pcore embedded 401 processor core sclck system clock generation and repowering entity crset hardware and software reset controlling entity cbist built-in self test logic entity cjtag jtag test interface logic entity
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 subsystem blocks page 29 of 676 subsystem blocks the ibm processor for network resources provides the host bus interfacing, memory management for buffers and control, cell segmentation and reassembly, and phy hardware control for an atm adapter. external memory consists of a number of sram modules, or two sdram arrays used for the storage of packet data and the control structures used by the IBM3206K0424. both the packet and control memory arrays consist of two 32-bit wide banks. when running at 102mb/s or slower (full duplex aggregate throughput), a single array of memory can be used. both control and data store are contained in this single array of memory. for a detailed description of the external memory organization refer to the dram controllers (comet/pakit) on page 184. the phy (physical) layer interface connects to several available hardware support devices. this layer of hardware converts a parallel data stream into a serial data stream to be shipped to and from the pmd layer. the phy and pmd end of a card design can be implemented as one of several encoding schemes and speeds, supporting both copper and fibre optic serial links. the interface will support the atm forum ? utopia spec, ? the pmc chip, and a 25mb/s serial interface to the ibm utp solution. (see standards compliance on page 23 for documents which describe these interfaces.) the pmd (physical media dependent) laye r interface connects to the line drivers and receivers. this could be either a copper or a fibre optic transceiver.
IBM3206K0424 ibm processor for network resources preliminary external architecture page 30 of 676 pnr25.chapt01.01 august 14, 2000 external architecture the ibm processor for network resources has four major interfaces: a system bus which acts as an actively cached memory slave and as a master for the pci 32-bit bus. the physical (phy) interface which supports several physical layer hardware devices that perform parallel to serial data conversion and the rest of the transmission convergence. an external dram interface that controls one or two arrays of two-bank interleaved dram with 60 ns access time for packet and control memory. the interface is direct drive to the dram. the control and configuration interface which covers a number of functions. it gives access from the sys- tem bus to the phys and to eprom. the eprom can also be used to hold initial device configuration, up to and including pvc configurations. note: IBM3206K0424 has built-in, self-test logic. the four major interfaces allow the ibm processor for network resources to be used in both "deep" and "shallow" adaptors with minimal external logic. (see block diagrams of possible systems on page 33 for examples.)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 internal architecture page 31 of 676 internal architecture logical channel support the logical channel is the unit of resource allocation in atm. at one level, the end station negotiates with the network interface to determine the characteristics of each end station-to-end station connection. the resources that may be reserved in the network are defined in the atm uni (user network interface) specifi- cation (see references in standards compliance on page 23). these resources include (but are not limited to) the peak and average bandwidth to be used by the logical channel, the maximum burst length that may be transmitted at the burst rate, the latency and variance of the connection, and the loss probability. the term logical channel rather than virtual circuit or vpi/vci is used in this databook to provide a level of abstraction from these specific instances. a switched virtual circuit (svc) can be negotiated with specific characteristics specifically for it. a virtual path can be negotiated with the network . several virtual circuits within that path can then be multi- plexed, using the vci on that single vpi, without having to renegotiate for each additional vci. the logical channel, with respect to the network, would be the virtual path. there would be multiple logical channels internal to the end station based on the virtual circuits used within the path. using atm adaptation layers 3 and 4, a multiplexing identifier (mid) can be used to provide multiple logical channels across a single vpi/vci. all of these logical channels are dealt with uniformly in IBM3206K0424. a hierarchy of logical channel descriptors can be built up, and frames or buffers can be queued to each of the lcds. see transmit buffer (csked) on page 273 for details. virtual memory support the packet memory space appears on the bus as a group of up to 128k buffers (configurable size). a level of indirection has been added to the addressing of packet memory to provide these large frame buffers without requiring memory behind all of them at the same time. this has been done for a number of reasons: the frames on the network can be up to 64kb long. the receiver does not know how long a frame will be until it is completely received. software generally has a much easier time dealing with contiguous memory. the memory does not page or swap. there are two major efficiencies used internally: the first n bytes of memory in a buffer are directly referenced. the blocks that make up the buffers are of multiple sizes.
IBM3206K0424 ibm processor for network resources preliminary internal architecture page 32 of 676 pnr25.chapt01.01 august 14, 2000 queues the ibm processor for network resources makes extensive use of cached single memory operation atomic queues: note: in order to maintain the atomicity of 64-bit atomic transfers, the user must ensure that 64-bit transfers are bus atomic within the particular bus system in which the IBM3206K0424 is being used. scheduling there is extensive support for transmit scheduling. please see transmit path on page 37 and transmit scheduling capabilities on page 38 for details. transmit queues the interface to the scheduling entity. blocks and frames can be queued to logical channels. receive queues based on the settings in the logical channel descriptor (receive side). cells arriving can be queued indi- vidually, collected into frames, or stored in fifo buffers. event queues when a frame is transmitted, its memory can be ? garbage collected ? or a reference to the frame can be placed on an event queue for software to handle. if either a fifo buffer scheme or frame buffer scheme is used to source or sink data on a logical channel, it is possible to set thresholds on the buffering that will cause events to be queued. when a threshold is crossed (for instance if a transmitting lc is about to run out of data to transmit), an event will be queued. software can read these events either by polling or by being interrupted and can schedule tasks to pro- vide more data. events can be scheduled on the reception of the first n bytes of a frame so that header processing can begin even before the complete frame is received. this will allow ? cut-through ? routing to be supported.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 internal architecture page 33 of 676 block diagrams of possible systems memory 2-256mb ecc optical transceiver IBM3206K0424 memory 2-256mb ecc short pci card pci bus shallow adapter for 155mb/s optical transceiver transmit device IBM3206K0424 short pci card pci bus receive device 100 mb/sec card using a taxi chipset
IBM3206K0424 ibm processor for network resources preliminary system environment page 34 of 676 pnr25.chapt01.01 august 14, 2000 system environment the dataflow context of an atm subsystem is shown in the diagram below. the purpose of the communica- tions subsystem of any digital device is to allow the application to share data and to adjudicate the flow of control with other devices. as shown in the figure above, data, in the form of application objects or control structures, are divided into communication frames at the communication stack interface. the stack may further partition the frames to fit reliability, efficiency, latency, and protocol requirements. in most cases, the communication stack encapsulates the data frame with protocol headers and/or trailers. these header blocks are often located in memory in areas apart from the data frames. a device driver is often given the task of moving this scattered memory to the actual transmission device. scatter dma is often used to make this operation efficient. in the case of the ibm processor for network resources, the data can be dmaed into virtually contiguous buffers connected to and controlled by the IBM3206K0424. it is also possible to write the frame headers directly from the processor to the IBM3206K0424 memory. the fully assembled frame is enqueued for trans- mission over a particular logical channel. (see more on the richness of logical channels in atm and the IBM3206K0424 in data structures on page 61). the logical channels with pending work are serviced by the atm segmentation layer which breaks the enqueued data into 48-byte chunks (depending on the atm adaptation layer (aal)) and prefixes it with a five-byte header (yielding the prime number 53) in preparation for transmission. a transmission convergence (tc) sublayer appropriate for the physical layer (phy) and physical media dependent (pmd) connection is then exercised, making atm cells suitable for transmission. the receiving process is the reverse of the transmission process, except that the scheduling performed dur- ing transmission is replaced by an identification-demultiplexing step during the reception of cells. system context of an atm subsystem object data object data application data frames frame headers and data packet memory local channels lan emulation tcp/ip mapping communication stack device driver atm cells segmentation scheduling physical layer (tc) pmd / transceiver control memory application
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 system environment page 35 of 676 note: not all of these separate parts or steps described in this section are necessary for a dedicated function system. IBM3206K0424 can easily be used in dedicated systems due to the goal of minimal processor inter- vention for steady state operations.
IBM3206K0424 ibm processor for network resources preliminary system environment page 36 of 676 pnr25.chapt01.01 august 14, 2000 data flows this section describes the data and control flow to and through the IBM3206K0424. in order for cell traffic to flow through an atm interface, the cells require that logical channels be allocated. for information on logi- cal channels, please see data structures on page 61. feature summary virtual memory memory pools register read/write interface for memory allocation transmit path scheduling receive path demultiplexing event queues operation summary basic assurance tests (bats) initialize and configure test path to switch permanent virtual circuit setup identify lan servers initialize svcs run, initializing circuits (q.93b) and transmitting data
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 transmit path page 37 of 676 transmit path a typical transmit operation begins with the software requesting a buffer from pools and filling it with data via slave dma, master dma, or processor writes. if virtual buffers are being used, the data write operation can fail due to lack of physical buffers. in the event of a failure, the header of the packet is updated to indicate the failure. the software can audit the header after the buffer has been completely transferred, and either take action to recover the data immediately or allow csked to generate an event later in the transmit cycle for any buffers that have had a data write failure. before the data can be transmitted, the buffer header must be updated to contain information required for cor- rect transmission. information such as data length, starting offset, and logical channel (lc) address are just a few of the fields that must be correctly reflected in the buffer header. for a complete list of the fields in the buffer header refer to packet header on page 61. in addition to the fields in the buffer header, the scheduling and segmentation sections of the logical channel descriptor (lcd), such as peak rate, average rate, and aal type, must also be set up correctly prior to trans- mission. for a complete list of the fields in the lcd, refer to transmit logical channel descriptor data struc- tures on page 66. after the data have been transferred into packet storage and both the buffer header and the lcd structure have been correctly initialized, the buffer address is queued to csked. when it receives a buffer, c sked checks the buffer header (packet memory) to make sure that the data transfer operation that filled the buffer completed without error. if it finds an error, csked posts an event to software and does nothing further with this buffer. if no error is indicated in the buffer header, csked fetches several fields from the lcd (control memory) indicated in the buffer header to determine the current state of that lcd. if the lcd is busy sending another buffer, the new buffer is queued to this lcd and will be processed when all previously enqueued buffers have been transmitted. if the lcd is not busy, csked updates the lcd based on several fields in the buffer header and queues the lcd to the next time slot on the time wheel (control memory). when csked detects a previously enqueued lcd on the time wheel, several fields are retrieved from the lcd. among other things, these fields are used by csked to determine where on the time w heel to resched- ule this lcd. the lcd address is then provided to segbf for processing. when csked provides an lcd address to segbf, the segmentation portion of the lcd is retrieved from control memory to determine both the current address at which to continue buffer segmentation and the type of cell to construct. depending on the aal type bits in the segmentation portion of the lcd, the cell is con- structed in an internal array using data from the lcd as well as data fetched from packet memory. when the cell construction is complete, status is raised to linkc indicating that a new cell is available for transmission. transmit opportunities are repeatedly provided to segbf by csked at the desired rate until all the data in the buffer has been passed to linkc via the cell buffer array. when segbf detects that no more data exists for a buffer, the lcd address is passed back to csked, indicating buffer completion. at this point, c sked removes the lcd from the time wheel if no more buffers are queued in it. if more buffers are queued, the lcd is updated and the segmentation process continues until all buffers on the lcd queue are serviced. a bit in the buffer header generates a transmit complete event when no buffers remain in the queue.
IBM3206K0424 ibm processor for network resources preliminary transmit path page 38 of 676 pnr25.chapt01.01 august 14, 2000 transmit scheduling capabilities vci desc. frame frame frame head pointer ta il pointer frame frame frame frame vci desc. vci desc. pointer fifo extra pin external control fixed rate vci start variable length frames as fixed intervals vpi/vci vpi 3 level priority scheduling wheels cell based transmission stream based transmission frame based transmission transmit queues and logical channel traffic shaping add block byte count threshold
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt01.01 august 14, 2000 receive path page 39 of 676 receive path as cells arrive, they pass from linkc to reasm. reasm uses a portion of the atm header to look up the lcd address for this cell. the lcd address is then passed to raall. raall reads the receive portion of the lcd, and then processes the cell based on the lcd information. for example, the lcd specifies what aal to use and maintains the current reassembly state. using the current reassembly state, the cell data is written to packet memory. while the data is written to packet memory, other functions such as crc generation and verification are performed in parallel. if a packet is complete, all trailer verification is performed. if the packet is good, an event is placed on a receive queue in the rxque entity. for error scenarios, see receive queues (rxque) on page 366. at this point, software can dequeue the packet event from rxque using the dequeue operation. it can then examine headers, dma the data into user space, and perform tcp check- sums. when these actions are complete, the buffer is returned to the IBM3206K0424 by performing a pools-free buffer operation.
IBM3206K0424 ibm processor for network resources preliminary receive path page 40 of 676 pnr25.chapt01.01 august 14, 2000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 dram memory bus interface page 41 of 676 input/output definitions the several interfaces to IBM3206K0424 are described in the following sections. there are 443 active i/o pins, assigned as follows: 90 for the pci bus 86 for the npbus 76 for the phy bus 156 for the packet memory interface 35 strictly for configuration and testing dram memory bus interface pci bus connections IBM3206K0424 mframe pcbe(3-0) mserr pad(31-0) ppar mperr minta mint2 pidsel mdevsel mtrdy mirdy mstop mgnt pcbe64(7-4) mreq64 mack64 ppar64 mpmevent mextpmevent pci bus mreq pad64(63-32)
IBM3206K0424 ibm processor for network resources preliminary dram memory bus interface page 42 of 676 pnr25.chapt02.01 august 14, 2000 pci bus interface pin descriptions quantity pin name input/output pin description 1mframe s/t/s 1 cycle frame is driven by the current master to indicate the beginning and duration of an access. 4 pcbe(3-0) t/s bus command and byte enables are multiplexed on the same pci pins. during address phase they define the bus command; during data phase they define the byte enables. 1mserr o/d system error reports address parity errors, data parity errors on the special cycle com- mand, or any other system error where the result will be catastrophic. 32 pad(31-0) s/t/s 1 address and data are multiplexed on the same pins. a bus transaction consists of one address phase and one or more data phases. 1ppar t/s parity is even parity across ad(31-0) and c/be(3-0). parity generation is required by all pci agents. 1mperr s/t/s 1 parity error is for reporting data parity errors during all pci bus transactions except spe- cial cycle. 1 minta o/d interrupt a is used to request an interrupt. 1mint2 o/d or s/t/s 1 this is an interrupt line that will go active low when sources within the IBM3206K0424 go active. it can be optionally connected to pci interrupt b. see entity 2: on page 135 for more details. 1 pidsel in initialization device select is a chip select during configuration transactions. 1 mdevsel s/t/s 1 device select indicates the driving device has decoded its address as the target of the current transaction. 1mtrdy s/t/s 1 target ready signals the target agent ? s ability to complete the current data phase of the transaction. 1 mirdy s/t/s 1 initiator ready indicates the bus master ? s ability to complete the current data phase. 1mstop s/t/s 1 stop indicates the current target is requesting the master to stop the current transaction. 1 mgnt in receives the bus grant line after a request has been made. 1mreq s/t/s 1 requests the bus for an initiator transfer. 32 pad64(63-32) s/t/s 1 address and data are multiplexed on the same pins and provide 32 additional bits. also, these pins are multiplexed with the enstate outputs, which allow debug of various inter- nal state machines and signals. 4 pcbe64(7-4) t/s bus command and byte enables are multiplexed on the same pci pins for 64-bit transfer support. 1mreq64 s/t/s 1 request 64-bit transfer. has the same timing as mframe. 1mack64 s/t/s 1 acknowledge 64-bit transfer. has the same timing as mdevsel. 1 ppar64 s/t/s 1 parity upper dword is the even parity bit that protects mad64(63-32) and pcbe(7-4). when not on a pci bus supporting 64 bits, this will drive enstate outputs. 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin l ow must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner t hat one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 dram memory bus interface page 43 of 676 1 mpmevent o/d as a pme source, this signal is active low and indicates a power management event sig- nalled from the IBM3206K0424. the output need to be conditioned with a card-level fet circuit so that the resulting signal (pme# on the pci bus) can be driven with the proper driver characteristics. this signal can also function as the pme_enable function for an external source when pro- grammable in this mode in pcint. 1 mextpmevent in active low by default but programmable, this input indicates a power management event signalled from some other card component to the IBM3206K0424. pci bus interface pin descriptions (continued) quantity pin name input/output pin description 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin l ow must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner t hat one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource.
IBM3206K0424 ibm processor for network resources preliminary dram memory bus interface page 44 of 676 pnr25.chapt02.01 august 14, 2000 dram memory bus interface one control memory and one packet memory bus provide the attachment to the external dram. up to two arrays of 32 data bits plus potential error detection bits may be connected to each bus. dram memory bus connections IBM3206K0424 pm n cs (3-0) pm n dqm (3-0) pmsynras (1-0) pmsyncas (1-0) pmclke pmaddr(20-0) pmdata(38-0) cm n cs (3-0) cm n dqm (3-0) cmsynras (1-0) cmsyncas (1-0) cmsynras cmwe (1-0) cmclk(4-0) cmclke cmaddr(20-0) cmdata2(38-0) packet memory bus control memory bus pmwe (1-0) pmclk(4-0)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 dram memory bus interface page 45 of 676 dram memory bus interface pin descriptions quantity pin name input/output pin function pin description 4pm n cs (3:0) output packet memory sram chip selects pm n cs(3:2) are bank address lines 1 and 0 and pm n cs(1:0) are the chip selects for the two arrays when using sdram for packet memory. when using sram, they are either the four chip selects or are eight-encoded chip selects and a valid signal. 4cm n cs (3:0) output control memory sram chip selects cm n cs(3:2) are bank address lines 1 and 0 and cm n cs(1:0) are the chip selects for the two arrays when using sdram for control memory. when using sram, they are either the four chip selects or are eight-encoded chip selects and a valid signal. 2 pm n dqm (3:0) output packet memory dqm lines pmdqm (3:0) are the dqm lines when using sdram for packet memory. they are identical cop- ies of output enable when using sram. pmdqm (3:2) is just another copy of pmdqm (1:0) to reduce loading on the nets. 2 cm n dqm (3:0) output control memory dqm lines cm0dqm (3:0) are the dqm lines when using sdram for control memory. they are identical copies of output enable when using sram. cmdqm (3:2) is just another copy of cmdqm (1:0) to reduce loading on the nets. 2 pmsynras (1:0) output ras signal for packet synchronous dram pmsynras (1:0) are identical copies of the ras signal for packet memory when using sdram. they are byte enables (3:2) when using sram. 2 cmsynras (1:0) output ras signal for control synchronous dram cmsynras (1:0) are identical copies of the ras signal for control memory when using sdram. they are byte enables (3:2) when using sram. 2 pmsyncas (1:0) output cas signal for packet synchronous dram pmsyncas (1:0) are identical copies of the cas signal for packet memory when using sdram. they are byte enables (1:0) when using sram. 2 cmsyncas (1:0) output cas signal for control synchronous dram cmsyncas (1:0) are identical copies of the cas signal for control memory when using sdram. they are byte enables (1:0) when using sram. 2pmwe (1:0) output packet memory write enable packet memory write enable. 2cmwe (1:0) output control memory write enable control memory write enable. 5 pmclk(4:0) output packet memory clock there are five copies to minimize loading. 1 pmclke input/output packet memory clock enable clock enable for packet memory when using sdram. 5 cmclk(4:0) output control memory clock there are five copies to minimize loading. 1 cmclke input/output control memory clock enable clock enable output for control memory when using sdram. 21 pmaddr(20:0) output address signals to packet memory 21 cmaddr(20:0) output address signals to control memory 39 pmdata(38:0) input/output data signals to and from the packet memory 39 cmdata(38:0) input/output data signals to and from the control memory.
IBM3206K0424 ibm processor for network resources preliminary dram memory bus interface page 46 of 676 pnr25.chapt02.01 august 14, 2000 memory i/o cross reference by device type IBM3206K0424 i/o sync dram 2-bank device sync dram 4-bank device sram xxaddr(20:0) address(20:0) address(20:0) address(20:0) xxcs (3) n/a bank address(1) chip select(3) xxcs (2) bank address(0) bank address(0) chip select(2) xxcs (1:0) chip select(1:0) chip select(1:0) chip select(1:0) xxdqm (3:2) dqm(1:0) dqm(1:0) oe(1:0) 1 xxdqm (1:0) dqm(1:0) dqm(1:0) oe(1:0) 1 xxclke cke cke xxwe (1:0) we(1:0) 1 we(1:0) 1 we(1:0) 1 xxsynras (1:0) ras(1:0) 1 ras(1:0) 1 byte enable(3:2) xxsyncas (1:0) cas(1:0) 1 cas(1:0) 1 byte enable(1:0) xxdata(31:0) data(31:0) data(31:0) data(31:0) xxdata(35:32) ecc(3:0) ecc(3:0) parity(3:0) xxdata(38:36) ecc(6:4) ecc(6:4) n/a 1. all signal groups marked by an asterisk are active at the same time. 2. xx = cm for control memory or pm for packet memory. 3. for sdrams, the dqm signals are active independently for shared ecc configurations. 4. for sdrams with split ecc, the dqms are usually active unless doing burst length two and the dqm is needed to terminate a burst.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 dram memory bus interface page 47 of 676 possible memory configurations using sdram with shared ecc module size one array plus ecc two arrays plus ecc storage size number of devices storage size number of devices 1mx16 4mb 3 8mb 5 2mx8 8mb 5 4mx16 16mb 3 32mb 5 8mx8 32mb 5 16mx16 64mb 3 128mb 5 32mx8 128mb 5 note: while it is possible to connect more than five sdram modules to each controller on the IBM3206K0424, it is likely the capacitiv e loading will not allow the interface to work at 7.5ns. the memory interface would need to be slowed down to allow the interface to work. possible memory configurations using sram module size memory size for one module memory size for two modules memory size for four modules 2mx18 n/a 8mb 16mb 1mx18 n/a 4mb 8mb 512kx18 n/a 2mb 4mb 256kx18 n/a 1mb 2mb 1mx36 4mb 8mb 16mb 512kx36 2mb 4mb 8mb 256kx36 1mb 2mb 4mb 128kx36 n/a 1mb 2mb 1. for x18 sram modules, half the data bus goes to one module, and the other half goes to a second module. the chip select to th e two modules is common. therefore, two x18 modules can be connected to a single chip select while only one x32 module can. therefore, given a constant number of chip selects, using pairs of x18 "x" mb modules results in a memory that is twice as deep as what is possible with x32 modules. using x18 modules also lowers the overall capacitance on the memory data nets. 2. while it is possible with the number of chip selects available (multiplexed or not) to connect more than four sram modules to each controller on the IBM3206K0424, it is likely the capacitive loading will not allow the interface to work at 7.5ns. the mem ory interface would need to be slowed down to allow the interface to work.
IBM3206K0424 ibm processor for network resources preliminary npbus page 48 of 676 pnr25.chapt02.01 august 14, 2000 npbus the npbus supports access to either an eprom or phy level hardware microprocessor interface. the npbus can operate with an eight-bit multiplexed addr/data bus or an eight-bit data bus with 18 separate address pins. generic transfer control signals work with the phy level hardware microprocessor interface or eprom to accomplish data transfers. npbus connections pb n phy1 pb n phy2 pb n eprm pbale1 pbale2 pbaddr16 pbaddr17 pbsclk pbsdata pbrnwrt pbrdrdy pbdata(7-0) pbintra pbphyrst IBM3206K0424 npbus signals enstate 8
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 npbus page 49 of 676 npbus pin descriptions quantity pin name input/output pin function pin description 1 pb n phy1 output select phy 1 when low, indicates that the IBM3206K0424 has selected phy 1 to write to control registers inside phy 1 or to read either the control or status registers. 1 pb n phy2 output select phy 2 when low, indicates that the IBM3206K0424 has selected phy 2 to write to control registers inside phy 2 or to read either the control or status registers. see npbus control register on page 428 for more details. if configured, this pin can also be odd parity across the eight-bit wide bidirectional data bus. it can also be configured as mpmdsel - this control pin, under register bit control, can drive a logical value out. the intention is to select between the different pmd types on the 155 mb/s copper card (utp verses stp). if it is in cascade mode, this bit functions as pidselo (+idsel out), which the primary IBM3206K0424 will drive to the secondary IBM3206K0424 when trying to update configuration space via configuration cycles. this multiplexed pin also carries the pbdatap signal. 63 enstate (63-0) output when programmed, drives out the real-time state-of-entity state machines, counters, etc. for debug purposes. the (47-32) bits of this bus are also pbaddr(15 - 0), which are the address lines for the external parallel eprom or phy. additionally, bits 47 - 40 can be used as bi-directional data bus bits to extend the pbdata bus by providing bits 15 - 8 of this bus. this allows operation with phy parts that have a fixed 16-bit data but limits the addressing to this phy to only eight address bits. ( lssd test function - scanout(13 to 0) -so -bdy ) 1 pb n eprm output eprom select when low, indicates that the IBM3206K0424 has selected the external eprom to read from. after reset, the IBM3206K0424 will start accessing the optional on-card rom/eprom and do the chip initialization function if it does not find a serial eprom attached. 1 pbale1 output address latch enable 1 when high, indicates that the IBM3206K0424 has generated an address on the pbdata bus and should be latched by either a phy that supports this muxing or an external octal latch ttl part. for an external eprom, it will also latch bits 7-0 of the address for an external eprom access. 1 pbale2 output address latch enable 2 when high, indicates that the IBM3206K0424 has generated an address on the pbdata bus and should be latched by an external octal latch ttl part that holds bits 15-8 of the address for an exter- nal eprom or phy access. 1 pbaddr16 output address send 16 supplies address 16 to an external eprom. the pin will also func- tion as pbale3, an address latch enable, that indicates that the IBM3206K0424 has generated an address on the pbdata bus and should be latched by an external octal latch ttl part that holds bits 23-16 of the address for an external eprom access. the mechanism used to set this mode is to put a pull-down resistor on this pin. at reset time, it will be detected and set this bit in pbale3 mode. otherwise it will be in pbaddr16 mode. 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin l ow must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner t hat one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it and must be provided by the central resource.
IBM3206K0424 ibm processor for network resources preliminary npbus page 50 of 676 pnr25.chapt02.01 august 14, 2000 1 pbaddr17 output address send 17 supplies address 17 to an external eprom. 1 pbsclk output clock for the i 2 c serial eprom accesses 1 pbsdata output or data this is the data bit that connects to the external serial eprom to read from or write to. it must have a pullup resistor attached and supports the i 2 c protocol. the range of supported serial eprom is from 256 to 2k bytes. after reset, the IBM3206K0424 will start accessing the optional on-card serial eprom and do the chip ini- tialization function. if this chip is pulled down (or no pullup), the IBM3206K0424 will assume that no serial eprom is attached and will go try to fetch from a parallel eprom. 1 pbrnwrt output read or write this pin allows the IBM3206K0424 to read from or write to internal registers of the phy parts. this signal acts as the write strobe when talking to pmc-sierra chips such as the suni-lite. 1 pbrdrdy s/t/s 1 this pin allows the IBM3206K0424 to read from or write into inter- nal registers of the phys by acting as a data acknowledge signal from the memory slaves. this signal acts as the read strobe when talking to pmc-sierra chips such as the suni-lite. 8 pbdata(7-0) input or output the pb-bus is an eight-bit wide bidirectional data bus used to inter- face the phys to the IBM3206K0424. when a data transfer is not happening, the lower four bits act as mled(3-0) - four control pins that, under register bit control, can drive general status to led devices. 1 pbintra input this input from phy a is an attention line that, when low, indicates that one or more unmasked flags are set in the status registers of phy 1. if additional phy parts are added, they should also dot their inter- rupt line onto this input. 1 pbphyrst output implements the network safety features of the device this signal implements the network safety features of the IBM3206K0424. it is the ored value of reset and all of the status bits cause the IBM3206K0424 to stop transferring data. it is asserted for a pulse, and then removed. this signal is asserted low. npbus pin descriptions (continued) quantity pin name input/output pin function pin description 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin l ow must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner t hat one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it and must be provided by the central resource.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 atm phy bus interface page 51 of 676 atm phy bus interface the phy bus consists of a transmit data path, receive data paths, and control signals. phy bus interface connections 16 fytdat(15-0) fytpar(1-0) fytwrb fytsoc fyrrdb fy n renb fy n tenb fyrrdb fyrdat(15-0) fyrpar(1-0) fyrca fytca fyrsoc fy n ful IBM3206K0424 2 16 2 16 fyemp fyradr(4-0) fytadr(4-0) fyreop fyteop fyrmod fytmod fytsdatp/n 2 fytsclkp/n 2 fyrsdatp/n 2 fyrsclkp/n 2 fydtct fydiscrd atm phy signals
IBM3206K0424 ibm processor for network resources preliminary atm phy bus interface page 52 of 676 pnr25.chapt02.01 august 14, 2000 : phy bus pin descriptions (page 1 of 3) quantity pin name input/output pin function pin description 16 fytdat (15 - 0) output phy transmit data when using an external phy, this 16-pin bus carries the atm cell octets that are loaded in the phy transmit fifo. when using the internal framer, bits 15, 14, and 13 are used for the rx hdlc interface signals ofprxr1data, ofprxr1ds, and ofprxrclk, respectively. 2 fytpar (1 - 0) output transmit data parity when using an external phy, these are byte parity signals for fytdat. when using the internal framer, bit 1 provides the rx out-of-frame indication, oof, and bit 0 provides the optical/ electrical module transmit shutdown control signal, ofptxs- down. when using a pos-phy, bit zero provides the terr signal. 1 fytsoc output transmit start of cell when using an external phy, this indicates the start of cell on fytdat. when using the internal framer, this provides the tx hdlc interface signal, ofptxt1dclk. when using a pos-phy, this indicates tsop. 1 fytwrb output transmit write strobe when using an external phy, this signal is used to write atm cells to the transmit fifo. when using the internal framer, this signal provides the 19.44mhz tx clock, refclkt. when using a utopia cell or pos-phy interface, this signal provides the write clock based on the clock received on the txclk pin. 1fy n tenb output transmit write enable when using an external phy, this indicates that transmit data to the phy is valid. when using the internal framer, this pro- vides the tx hdlc interface signal, ofptxt1ds. 1fy n renb output receive write enable when using an external phy, this indicates to the phy that the IBM3206K0424 is ready to accept data. when using the inter- nal framer, this provides the clock recovery reset signal, rstcrec1. 1 fyrrdb output receive ready strobe when using an external phy, this is used to read atm cells from the phy receive fifo. when using the internal framer, this signal provides the 19.44mhz rx clock, rxbyclk. when using a utopia cell or pos-phy interface, this signal provides the write clock based on the clock received on the rxclk pin. 16 fyrdat(15 - 0) input phy receive data when using an external phy, this 16-pin bus carries the atm cell octets that are read from the phy receive fifo. 2 fyrpar(1 - 0) input phy receive data parity when using an external phy, these are byte parity signals for fyrdat. when using the internal framer, bit 1 provides the optical/electrical module low power indication signal, ofptx- lpow, and bit 0 is not used. when using a pos-phy, bit 0 should be connected to rerr. note: because some of the phy transmit i/os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. if the transmit path is using an external phy and the receive path is using the internal framer, fytpar(1) will assume the oo f function and not be available as a parity output. this is only a concern if the phy uses a 16-bit data interface and parity is being used. 2. if the receive path is using an external phy and the transmit path is using the internal framer, fyrpar(1) will assume the of ptx- lpow function and not be available as a parity input. this is only a concern if the phy uses a 16-bit data interface. 3. if the transmit path is using an external phy and the receive path is using the internal framer, and the external phy has a 1 6-bit data interface, then the receive hdlc interface cannot be used. the three i/o for the rx hdlc interface will instead take on th e function of fytdat(15-13).
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 atm phy bus interface page 53 of 676 1 fyrsoc input receive start of cell when using an external phy, this signal indicates the start of cell on the fyrdat bus. 1 fyrca input receive cell available when using an external phy, this indicates that a cell is avail- able in the receive fifo. when using an internal framer, this signal is not used. when using a pos-phy, this signal must be connected to prpa. 1 fytca input transmit cell available when using an external phy, this indicates that a cell is avail- able in the phy transmit fifo. when using the internal framer, this provides the tx hdlc interface signal, ofptxt1data. when interfacing to pos-phy, this signal should be connected to ptpa. 1 fy n ful input phy transmit full when using an external phy, this is asserted low by the phy when it can accept no more than four more data transfers before it is full. this pin should be pulled up to the inactive state when using a phy that does not drive it. when using the inter- nal framer, this provides the tx hdlc interface signal, ofptxt1dfrm. when using a pos-phy interface, this signal must be connected to stpa 1 fyemp input phy receive empty when using an external phy, this is asserted low by the phy to indicate that in the current cycle there is no valid data for delivery to the IBM3206K0424. when the phy does not drive fyemp, this input should be tied to the inactive state. when using the internal framer, this signal is not used. when using a pos-phy interface, this signal is connected to rval. 5 fyradr(4-0) output phy receive address when using an external phy (cell or pos-phy based), this address is used to select and poll up to 31 phys on the receive side. bits (1-0) are used to select which of the four phys and bit two is used to indicate the null address. when bit two is b ? 1 ? , bits 1-0 are also ? 1 ? . when bit 2 is ? 0 ? , bits 1-0 are ? 00 ? , ? 01 ? , ? 10 ? , or ? 11 ? . 5 fytadr(4-0) output phy transmit address when using an external phy (cell or pos-phy based), this address is used to select and poll up to 31 phys on the trans- mit side. bits (1-0) are used to select which of the four phys and bit two is used to indicate the null address. when bit two is ? 1 ? , bits 1-0 are also ? 1 ? . when bit 2 is ? 0 ? , bits 1-0 are ? 00 ? , ? 01 ? , ? 10 ? , or ? 11 ? . 1 fyreop input phy receive eop when using an external pos-phy, this signal indicates if the fyrdata (15-0) contains the last data of a packet. if the external phy is not a pos-phy, this signal should be tied to gnd. phy bus pin descriptions (page 2 of 3) quantity pin name input/output pin function pin description note: because some of the phy transmit i/os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. if the transmit path is using an external phy and the receive path is using the internal framer, fytpar(1) will assume the oo f function and not be available as a parity output. this is only a concern if the phy uses a 16-bit data interface and parity is being used. 2. if the receive path is using an external phy and the transmit path is using the internal framer, fyrpar(1) will assume the of ptx- lpow function and not be available as a parity input. this is only a concern if the phy uses a 16-bit data interface. 3. if the transmit path is using an external phy and the receive path is using the internal framer, and the external phy has a 1 6-bit data interface, then the receive hdlc interface cannot be used. the three i/o for the rx hdlc interface will instead take on th e function of fytdat(15-13).
IBM3206K0424 ibm processor for network resources preliminary atm phy bus interface page 54 of 676 pnr25.chapt02.01 august 14, 2000 1 fyteop output phy transmit eop when using an external pos-phy, this signal indicates if the fytdata (15-0) contains the last data of a packet. if the exter- nal phy is not a pos-phy, this signal should ignored. 1 fyrmod input phy receive mod when using an external pos-phy, this signal indicates if the fyrdata (7-0) contains valid data. if fyrmod is ? 1 ? , fyr- data(7-0) is ignored. fyrmod is only relevant when fyreop is ? 1 ? . a value of ? 1 ? any other time will be ignored. if a pos-phy is not connected, this signal should be tied to gnd. 1 fytmod output phy transmit mod when using an external pos-phy, this signal indicates if the fytdata (7-0) contains valid data. if fytmod is ? 1 ? , fyr- data(7-0) will be ignored. fytmod is only driven to a ? 1 ? when fyteop is ? 1 ? . 2 fytsdatp/n output serdes transmit data (differential) when using the internal framer and the internal serdes, these signals provide the serial transmit data stream. when the transmit side of linkc is connected to an echo interface, this differential driver will provide the clock that goes with the data fyrdat(7-0), parity fytpar(7-0), and soc fytsoc. 2 fytsclkp/n input serdes transmit clock (differential) when using the internal framer and the internal serdes, the reference 155.52mhz clock is supplied on these signals. when not in use, these should be tied to (tbd). 2 fyrsdatp/n input serdes receive data (differential) when using the internal framer and the internal serdes, the recovered receive data is supplied on these signals. when not in use, these should be tied to (tbd). 2 fyrsclkp/n input serdes receive clock (differential) when using the internal framer and the internal serdes, the recovered 155.52mhz clock is supplied on these signals. when not in use, these should be tied to (tbd). 1 fydtct input phy carrier detect when using an external phy, the phy uses this signal to indi- cate carrier detect. when using the internal framer, this signal provides the deserializer lock detect signal, elockdet, from the deserializer. 1 fydiscrd input phy cell discard when using an external phy, this signal causes the current cell being received to be discarded. in this case it should only be asserted for the duration of one of the 53 bytes of the atm cell. when using the internal framer, this signal provides the optical/electrical module loss-of-signal indication, losssig. phy bus pin descriptions (page 3 of 3) quantity pin name input/output pin function pin description note: because some of the phy transmit i/os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. if the transmit path is using an external phy and the receive path is using the internal framer, fytpar(1) will assume the oo f function and not be available as a parity output. this is only a concern if the phy uses a 16-bit data interface and parity is being used. 2. if the receive path is using an external phy and the transmit path is using the internal framer, fyrpar(1) will assume the of ptx- lpow function and not be available as a parity input. this is only a concern if the phy uses a 16-bit data interface. 3. if the transmit path is using an external phy and the receive path is using the internal framer, and the external phy has a 1 6-bit data interface, then the receive hdlc interface cannot be used. the three i/o for the rx hdlc interface will instead take on th e function of fytdat(15-13).
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 atm phy bus interface page 55 of 676 transmit phy i/o cross reference IBM3206K0424 i/o suni-lite utopia pos-phy internal framer fytwrb tfclk txclk tfclk refclkt fytca tca txclav ptpa ofptxt1data fy n ful n/a txfull stpa ofptxt1dfrm fy n tenb twrenb txenb tenb ofptxt1ds fytsoc tsoc txsoc tsop ofptxt1dclk fytdat(15) n/a txdata(15) tdata(15) ofprxr1data fytdat(14) n/a txdata(14) tdata(14) ofprxr1ds fytdat(13) n/a txdata(13) tdata(13) ofprxr1dclk fytdat(12-8) n/a txdata(12-8) tdata(12-8) n/a fytdat(7-0) tdat(7-0) txdata(7-0) tdata(7-0) txextdat(7-0) fytpar(1) n/a txprty(1) tprty oof fytpar(0) n/a txprty(0) terr ofptxsdown fytadr(4-0) n/a txaddr(4-0) tadr(4-0) n/a fytmod n/a n/a tmod n/a fyteop n/a n/a teop n/a fytdatp n/a n/a n/a tsdatp fytdatn n/a n/a n/a tsdatn fytclkp n/a n/a n/a tsclkp fytclkp n/a n/a n/a tsclkn note: signals marked with an overbar are active low. inputs listed as n/a should be tied to their inactive utopia state.
IBM3206K0424 ibm processor for network resources preliminary atm phy bus interface page 56 of 676 pnr25.chapt02.01 august 14, 2000 receive phy i/o cross reference IBM3206K0424 i/o suni-lite utopia pos-phy internal framer fyrrdb rfclk rxclk rfclk rxbyclk fyrca rca rxclav prpa n/a fyemp n/a rxempty rval n/a fyrenb rrdenb rxenb renb rstcrec1 fyrsoc rsoc rxsoc rsop n/a fyrdat(15-8) n/a rxdata(15-8) rdat(15-8) n/a fyrdat(7-0) rdat(7-0) rxdata(7-0) rdat(7-0) n/a fyrpar(1) n/a rxprty(1) rprty ofptxlpow fyrpar(0) n/a rxprty(0) rerr n/a fryadr(4-0) n/a rxaddr(4-0) radr(4-0) n/a fyrmod n/a n/a rmod n/a fyreop n/a n/a reop n/a fyrsdatp n/a n/a n/a rsdatp fyrsdatn n/a n/a n/a rsdatn fyrsclkp n/a n/a n/a rsclkp fyrsclkn n/a n/a n/a rsclkn fydtct n/a n/a n/a dtct fydiscrd n/a n/a n/a discrd fysetclp n/a n/a n/a setclp note: signals marked with an overbar are active low. inputs listed as n/a should be tied to their inactive utopia state.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 atm phy bus interface page 57 of 676 clock, configuration, and lssd connections mpcirst pciclk txclk rxclk mpegclk jtagtck jtagtms jtagtdi pdblclk ppllout bist n di1 dtr cts txd rxd rts dsr ibdinh1 ibdinh2 ibdrinh leaktst plltune(1:0) mpllreset jtcomply testm mhaltppc pffcfg(2-0) pffosc pllti pvdda nselft jtag n rst jtagtd0 pintclk 16 IBM3206K0424 signals pm66en
IBM3206K0424 ibm processor for network resources preliminary atm phy bus interface page 58 of 676 pnr25.chapt02.01 august 14, 2000 clock, configuration, and lssd pin descriptions quantity pin name input/output pin description 1 mpcirst input this signal causes a hardware reset when asserted low. see entity 20: on page 511 for more details on resets. 1 pciclk input the pciclk is a 0-33, 66mhz clock. 1 pm66en input this pin is high when on a pci bus that runs at 33mhz - 66mhz. it is used to tell the on-chip pll how to generate clocks. 1 txclk input this is the linkc asynchronous transmit clock. 1 rxclk input this is the linkc asynchronous receive clock. an oscillator should be con- nected to rxclk even if it is not functionally used. without the rxclk input oscillating, the chip may not reset properly. 1 mpegclk input this is the mpeg asynchronous clock. 1 testm input when the test mode pin is not asserted, this chip runs as specified. when the test mode pin is asserted, the chip is in lssd test mode. transparent latches become clocked latches and i/os change to primary test inputs and test out- puts. the precise connections are specified in the vhdl. this signal is asserted high when in test mode. 1 mhaltppc input used by riscwatch to halt the power pc core for debug purposes. this does not need to be in a test/noscan i/o location. 3 pffcfg (2 - 0) input these bits control the "find frequency" function which sets the range bits of the pll. below is the encoded meaning of these bits. 000 = enable internal register of these bits in crset 001 = disable auto range function: set range to < 25.0mhz operation 010 = disable auto range function: set range to 25.0mhz - 33.3mhz-011 = dis- able auto range function: set range to 50.0mhz operation 100 = enable auto range function for 19.44mhz 101 = reserved 110 = enable auto range function for 25.0mhz 111 = enable auto range function for 32.0mhz 1 pffosc input this input is the auto range known frequency input that is used to time the pci clock input. this should be connected to some oscillator on the card, for exam- ple, the phy oscillator. this is also used as the bist clock. without this input oscillator, the chip will not run bist nor will it properly reset; it is required for proper operation. 1pllti input when tied to ? 1 ? , this input will cause the pll to do a parametric testing at the wafer and module level. normal mode for this pin is a ? 0 ? . 1 pvdda input filtered vdd source to the pll logic. see technology application notes for filter circuit. 1 nselft input minus active selftest input. normal mode is a ? 1 ? . 1jtag n rst input jtag test reset provides an asynchronous initialization of the tap controller. 1jtagtck input jtag test clock is used to clock state information and test data into and out of the device during operation of the tap. 1jtagtms input jtag test mode select is used to control the state of the tap controller in the device. ( lssd test function - rarrytclkc - sc ) 1jtagtdi input jtag test data input is used to serially shift test data and test instructions into the device during tap operation. ( lssd test function - clkdivtclkc-sc )
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt02.01 august 14, 2000 atm phy bus interface page 59 of 676 1 jtagtdo output test data output is used to serially shift test data and test instructions out of the device during tap operation. ( lssd test function - prsramabdone and plllock output ) 1 pintclk output this is the external test point to measure the jitter effects of the phase-lock loop circuit. pintclk does not serve any lssd or mfg test function. it does not need to be on a test/noscan location. 1 pdblclk output this is the external test point that is double the frequency of the pintclk. it is used to clock enstate state signals at this frequency. pdblclk does not serve any lssd or mfg test function. it does not need to be on a test/nos- can location. 1 ppllout output this is an observation output only. this makes the output of the pll observ- able. this is also the dtr signal when the selrs232 is active. 1bist n di1 output drives the di input during bist. 1 dtr input or output rs232 dtr for the core debugger. ( lssd test function - tclka-ac) 1 cts input rs232 cts for the core debugger. ( lssd test function - lpra bypass-ti) 1 txd input or output rs232 txd for the core debugger. ( lssd test function - clkdivtclkb-bc) 1 rxd input or output rs232 rxd for the core debugger. ( lssd test function - bscantclkb-bc) 1 rts input or output rs232 rts for the core debugger. ( lssd test function - bscantclkc-sc) 1 dsr input or output rs232 dsr for the core debugger. ( lssd test function - pll testout) 1 ibdinh1 input this is the boundary scan input for bsinh1. 1 ibdinh2 input this is the boundary scan input for bsinh2(*). 1 ibdrinh input this is the boundary scan input for rinh. 1 leaktst input this is the sti driver/receiver leak test input. 2 plltune(1:0) input these inputs help tune the pll operation. ( lssd test function - scanout(15,14)) 1 mpllreset input this input is active low and resets the pll at power up to avoid vco runaway. this requires a reset circuit that delays a low-to-high level after power-on-reset by 150 s. ( lssd test function - this pin functions as the testct [test clock tree] input. when not asserted, this chip runs as specified. when asserted, the clock tree uses this input to control the clokc tree outputs - ti) 1 jtcomply input this input is high for jtag compliance and low for riscwatch/bist-friendly use. when this pin is high, jtag boundary scan operations may be used to test chip i/o operation and card wiring without supplying clocks to the rest of the chip. also, when the tap controller enters the test logic reset state, the jtag instruction is idcode. when this pin is low, the jtag boundary scan logic works only if the other chip clocks are running in a normal functional man- ner. when the tap controller enters the test logic reset state, the jtag instruction is bypass in order to make this more compatible with riscwatch. ( lssd test function - sram bist result output) clock, configuration, and lssd pin descriptions (continued) quantity pin name input/output pin description
IBM3206K0424 ibm processor for network resources preliminary atm phy bus interface page 60 of 676 pnr25.chapt02.01 august 14, 2000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 61 of 676 data structures these structures reside in control memory for each of the logical channels that are set up for transmission or reception. packet header each packet buffer consists of two parts. the first part is the control information used by the IBM3206K0424. the second portion of the packet buffer is used to hold the actual packet data. the following figures show the structure of the transmit and receive packet headers: the minimum transmit packet header size (and transmit offset) is 0xc bytes. see rxaal packet h eader configuration on page 352 for available word choices and definitions. transmit packet header structure struct tx_min_packhead { struct tx_packhead { bit32 next_buffer; bit32 next_buffer; bit8 aal5_user_byte1; bit8 aal5_user_byte; bit8 buffer_offset; bit8 buffer_offset; bit16 buffer_length; bit16 buffer_length; bit25 lc_address; bit25 lc_address; bit1 efci_status; bit1 efci_status; bit1 reserved; bit1 reserved; bit1 dma_on_xmit; bit1 dma_on_xmit; bit1 generate_crc10; bit1 generate_crc10; bit1 free_on_xmit; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 queue_on_xmit; bit1 cell_loss_priority; bit1 cell_loss_priority; }; bit32 dma_desc_addr; bit16 aal5_user_byte1_2; bit16 reserved }; receive packet header structure struct rx_packhead { bit32 rx_label_flags; bit8 aal5_user_byte1; bit8 buffer_offset; bit16 buffer_length; bit25 lc_address; bit1 efci_status; bit5 reserved; bit1 cell_loss_priority; bit32 optional_words[7]; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 62 of 676 pnr25.chapt03.01 august 14, 2000 the minimum receive packet offset is 0xc bytes. when the optional fields are enabled, the receive packet off- set increases and should be set appropriately in the receive lcd. see rxaal packet header configuration on page 352 for available word choices and definitions. receive packet definitions // aal 5 definition // raw definition // packet mode definition struct rx_label flags { struct rx_label flags { struct rx_label flags { bit16 rx_label; bit16 rx_label; bit16 rx_label; bit2 ip_chksm_flags; bit2 reserved; bit2 ip_chksm_flags; bit2 proto_chksm_flags; bit2 reserved; bit2 proto_chksm_flags; bit1 toobig_status; bit1 toobig_status; bit1 toobig_status; bit1 memchk_status; bit1 memchk_status; bit1 memchk_status; bit1 fabort_status; bit1 reserved; bit1 reserved; bit1 badlen_status; bit1 reserved; bit1 reserved; bit1 badcpi_status; bit1 reserved; bit1 reserved; bit1 badcrc_status; bit1 badcrc_status; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 route_status; bit1 route_status; bit1 route_status; bit1 error_status; bit1 error_status; bit1 error_status; bit1 done_status; bit1 done_status; bit1 done_status; }; }; }; transmit and receive packet header field descriptions (page 1 of 3) field name field description next_buffer this field is used by the hardware to chain buffers together on queues. it contains the address of the next buffer if one exists. for transmit buffers allocated in virtual memory, this field is written by the hardware with a distinctive pattern ( ? zzzzzbad ? x) where zzzzz is the offset of the failure when a write operation was not able to complete due to a shortage of the real buffers needed to map into the virtual address space. this field can be checked after all buffer write operations and the appropriate recovery actions are taken immediately, or when a buffer that has had a write failure is enqueued to csked (an event will be generated and the buffer will not be processed by csked). a status bit also exists in the bcach status register indicating that a write to virtual memory has failed. with cache performance in mind, this status bit could be checked first; if it is not set, there is no need to access the header of the packet. note: this automatic error recovery mechanism results in the restriction that this first four bytes of a transmit packet must never be written via programmed io or dma during preparation for transmission. if this field is written by a software or dma operation, the automatic error detection will not work properly and undesirable results are likely. aal5_user_byte1 on transmit, this field contains the value to be sent in the user byte in the last cell of an aal5 packet, if intst is configured for one user byte. on receive, this field contains the user byte from the aal5 trailer, if intst is configured for one user byte. when not configured for aal5, this field is redefined. the two most significant bits contain the drop number. when in packet mode, the low five bits of this byte contain the number of bytes dropped due to the dropn- bytes field in the lcd. dma_on_xmit if this bit is set, a dma descriptor address placed in the packet header (offset 0xc) will be queued for execu- tion. generate_crc10 if this bit is set, crc10 will be generated over the cell(s) in this packet. free_on_xmit if this bit is set, the buffer will be freed after the transmission completes. queue_on_xmit if this bit is set, the buffer will be queued on the transmit complete queue after the transmission completes.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 63 of 676 efct_status this bit is used on both transmit and receive: transmit - if this bit is set, the efci bit in the atm cell header will be set for each cell in this packet. receive - this bit contains the ored efci bits across all the cells that comprised this packet if this lcd is using aal5. cell_loss_priority this bit is used on both transmit and receive: transmit -if this bit is set, the cell loss priority bit in the atm cell header will be set for each cell in this packet receive - this bit contains the ored cell loss priority bits across all the cells that comprised this packet if this lcd is using aal5. buffer_offset this field contains the offset into the buffer where the data starts. buffer_length this field contains the length of the packet. lc_address this is the address of the logical connection descriptor on which this packet was received. rx_atm_header on reception, the four-byte atm header (no hec) is copied from the first and last cell into this area. this is an optional header word. aal5_user_byte2 (tx) this field contains the value to be sent in the user bytes, one and two, in the last cell of an aal5 packet if intst is configured for two-user byte. the normal one-byte aal5 user byte field is not used. aal5_user_byte2 (rx) this field contains the aal5 user bytes, one and two, in the last cell of an aal5 packet if intst is configured for two-user byte. the normal one-byte aal5 user byte field is not filled in. this is an optional packet header word. bit16 rx_label this field is written with "ra" in ascii (0x5241) to signal that this buffer was used by raall. bit2 ip_chksm_flags this field contains the ip checksum status if enabled. the possible values are: 00 not checked 01 good 10 bad 11 unknown bit2 proto_chksm_flags this field contains the protocol checksum status if enabled. the possible values are: 00 not checked 01 good 10 bad 11 unknown bit1 toobig_status indicates the current packet exceeded the maximum packet size. bit1 memchk_status indicates the current packet had a memory check (real size exceeded or virtual error). bit1 fabort_status indicates the current packet was aborted (aal5 forward abort). bit1 badlen_status indicates the current packet had a bad aal5 length in the trailer. bit1 badcpi_status indicates the current packet had a bad aal5 cpi field (not zero). bit1 badcrc_status indicates the current packet had a bad aal5 crc. bit1 route_status this bit is written when the packet is completed if it is internally routed. bit1 error_status this bit is written when the packet is completed if an error condition occurs. bit1 done_status this bit is written when the packet is completed. it can be used when thresholding. host_data this is an optional word that can be copied from the lcd to the packet header. transmit and receive packet header field descriptions (page 2 of 3) field name field description
IBM3206K0424 ibm processor for network resources preliminary packet header page 64 of 676 pnr25.chapt03.01 august 14, 2000 vba this is the IBM3206K0424 virtual buffer address of the current receive buffer. this is an optional packet header word. txqueuelenh/m/l these words provide the current transmit queue length. see rxaal transmit queue length compression configuration on page 351 for more information on the format of these words. these are optional packet header words. start_timestamp a timestamp can be inserted in the packet header when the packet is started. the timestamp is sourced from the rxque timestamp register. the location of this timestamp is important so it is not overwritten when the packet is completed. for this reason, it should be the last word in the packet header. this is an optional header word. end_timestamp a timestamp can be inserted in the packet header when the packet is started. the timestamp is sourced from the rxque timestamp register. this is an optional header word. dma_desc_addr if the dma_on_xmit bit is set in the packet header, this field contains the address of the dma descriptor that will be queued when transmission is complete. transmit and receive packet header field descriptions (page 3 of 3) field name field description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 65 of 676 logical channel data structure transmit portion receive portion user data offset 0x00 0x50 0x78 csked scheduling information (3) 64-bit words csked/segbf shared information (2) 64-bit words segbf segmentation (0-3) 64-bit words 128-byte lcd if lcd-based memory management is used, a 64-bit section with the following layout is inserted at byte offset 18x: threshold threshold pool id1 bytes waiting to be transmitted 12 pool id1 four different formats, determined by whether scheduling is based on virtual path parameters or is configured for abr. see scheduling portion of a transmit descriptor. tx length misc. flags atm header 16 16 4 4 24 16 16 32 total user cells total user cells 32 32 segmentation pointer partial crc 16 32 oam data fixed blocking data 32 32 oam data fixed blocking data 32 32 mpeg-2 or abr data 32 32 unused abr 56 8 with clp=0 lcd cell status total user cells total user cells 32 32 with clp=0 lcd cell status total user cells total user cells 32 32 with clp=0 lcd cell status oam data fixed blocking data 32 32 abr code variables 64 variables on abr connections, the abr code running in pcore uses ten bytes of the lcd starting at offset 0x46 for managing the connection. for aal type 0x7 for aal types 0x4 and 0x6 for all other aal types abr code portion information
IBM3206K0424 ibm processor for network resources preliminary packet header page 66 of 676 pnr25.chapt03.01 august 14, 2000 transmit logical channel descriptor data structures logical channel data structure on page 65 and scheduling portion of a transmit descriptor on page 67 show the layout of the transmit portion of a logical channel descriptor. when initializing an lcd, any loca- tions that are not written to a specific value should be initialized to zeros. fields that typically need to be ini- tialized to a non-zero value are flagged with a # in the structure below. note: this is only one possible layout of the transmit portion of the lcd. some field locations vary and are further defined later in this section. care must be taken when updating fields in the lcd and then immediately causing the updated fields to be accessed by other IBM3206K0424 entities. for example, it is possible, although not likely, under the right conditions, for a normal lcd update followed by a segbf cell enqueue operation to actually execute in reverse order. this is due to IBM3206K0424 internal priority levels and could result in segbf fetching the lcd data before it has been updated to the new value. for this reason, it is highly advisable to use the lcd update mechanism in cell/packet re-assembly (reasm) . the transmit portion of the lcd can be subdivided into three distinct parts based on which chip functions or entities access that particular part of the lcd. the first three 64-bit words are scheduling related and are accessed only by csked. the next two 64-bit words (four if using switch fabric header) are related to both scheduling and segmentation and are accessed and shared by both c sked and segbf. the words follow- ing these shared locations are related only to segmentation and are accessed only by segbf. the number of 64-bit words in this portion of the lcd can vary from one to three. the actual number being used in an lcd is determined by the segmentation processor code entry point field of that lcd. the following figure is the layout of the entire transmit portion of the lcd. the three 64-bit words containing csked scheduling information can have four different formats depending upon whether scheduling is based on virtual path parameters or is configured for abr. if lcd-based memory management is used, a 64-bit section is inserted at byte offset ? 18 ? x. general lcd layout struct lcd_struct { tx_lcd_struct tx_lcd ;/* transmit portion of the lc descriptor */ bit8 fill[n] ;/* the fill area depends on the type of tx lcd */ rx_lcd_struct rx_lcd ;/* receive portion of the lc descriptor */ }; overall transmit lcd layout csked scheduling information three 64-bit words csked/segbf shared information two 64-bit words segbf segmentation information zero - three 64-bit words
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 67 of 676 on abr connections, the abr code running in pcore will use ten bytes of the lcd for managing the con- nection, starting at offset 0x46 in the lcd. scheduling portion of a transmit descriptor 32 time stamp timing data 32 32 32 32 32 virtual path descriptor reserved 32 32 32 32 next descriptor in chain 32 16 time stamp timing data 32 32 transmit packet 32 32 32 abr values and timing data 64 32 32 next descriptor in chain next descriptor in chain next descriptor in chain peak interval average interval 16 16 peak interval average interval 16 16 peak interval average interval 16 16 peak interval abr parameters 16 queue head pointer transmit packet queue tail pointer for a standard virtual circuit using abr for a virtual circuit on a virtual path for a virtual path transmit packet queue head pointer transmit packet queue tail pointer transmit packet queue head pointer transmit packet queue tail pointer transmit lcd queue head pointer transmit lcd queue tail pointer address csked scheduling information (3) 64-bit words
IBM3206K0424 ibm processor for network resources preliminary packet header page 68 of 676 pnr25.chapt03.01 august 14, 2000 transmit logical channel descriptor structure . typedef struct { bit32 next_lcd; bit16 #peak_interval; bit16 #average_interval; bit32 #timestamp; bit11 reserved; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit1 #max_resolution; bit3 #max_burst_mult; bit10 #max_burst_value; bit26 head_packet_pointer; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 conn_suss; bit1 #drop; bit26 tail_packet_pointer; bit6 reserved; bit16 transmit_length; bit8 buffer_offset; bit2 xmt_cmp_evt_mod; bit2 reserved; bit4 seg_prc_entry_point; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 xmit_stat1; bit32 xmit_stat2; } tx_lcd_struct, *tx_lcd_struct_ptr;
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 69 of 676 transmit logical path descriptor structure . typedef struct { bit32 next_lcd; bit16 #peak_interval; bit16 #average_interval; bit32 #timestamp; bit11 reserved; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit1 #max_resolution; bit3 #max_burst_mult; bit10 #max_burst_value; bit26 forward_lcd_pointer; bit6 reserved; bit26 backwared_lcd_pointer; bit6 reserved; } tx_lpd_struct, *tx_lpd_struct_ptr;
IBM3206K0424 ibm processor for network resources preliminary packet header page 70 of 676 pnr25.chapt03.01 august 14, 2000 redefinition of transmit logical channel descriptor for connections sharing (logical path bandwidth) typedef struct { bit32 next_lcd; bit32 reserved; bit32 lcd_pointer; bit11 reserved; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit14 reserved; bit26 head_packet_pointer; bit1 free_on_transmit; bit1 queue_on_transmit; bit1 dma_on_transmit; bit1 conn_suss; bit2 #drop; bit26 tail_packet_pointer; bit6 reserved; bit16 transmit_length; bit8 buffer_offset; bit2 xmt_cmp_evt_mod; bit2 reserved; bit4 seg_prc_entry_point; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 xmit_stat1; bit32 xmit_stat2; } tx_lcd_struct, *tx_lcd_struct_ptr;
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 71 of 676 owing to the use of certain lcd fields, a connection running abr cannot be set up for segmentation aal types 0x6 (fixed-sized blocking) or 0x7 (mpeg-2 assist). redefinition of shared and segmentation portion of transmit lcd for abr typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 xmt_cmp_evt_mod; bit2 reserved; bit4 seg_prc_entry_point; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 xmit_stat1; bit32 xmit_stat2; bit16 reserved; bit16 explicit_rate; bit16 current_rate; bit16 minimum_rate; bit32 backward_ptr; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr;
IBM3206K0424 ibm processor for network resources preliminary packet header page 72 of 676 pnr25.chapt03.01 august 14, 2000 redefinition of segmentation portion of transmit lcd for fixed size aal5 blocking (segmentation type 0x6) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 xmt_cmp_evt_mod; bit2 reserved; bit4 seg_prc_entry_point; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 xmit_stat1; bit32 xmit_stat2; bit8 #packets_per_aal5_frame bit8 #blocking_size (4 bytes x2f for mpeg-2) bit8 current_transport_stream_packet bit8 current_blocking_count (4 bytes) bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; redefinition of segmentation portion of transmit lcd for mpeg2 (segmentation type 0x7) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 xmt_cmp_evt_mod; bit2 reserved; bit4 seg_prc_entry_point; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 xmit_stat1 bit32 xmit_stat2 bit8 #packets_per_aal5_frame bit8 #blocking_size (4 bytes x2f for mpeg-2) bit8 current_transport_stream_packet bit8 current_blocking_count (4 bytes) bit32 reserved; bit32 reserved; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr;
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 73 of 676 redefinition of scheduling portion of transmit lcd for abr typedef struct { bit32 next_lcd; bit16 #peak_interval; bit3 #nrm; bit3 #trm; bit10 #tadtf; bit8 #nc; bit8 #ncrm; bit16 reserved; bit11 tlrm1; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit1 #max_resolution; bit13 tlrm2; bit26 head_packet_pointer; bit1 free_on_xmit; bit1 queue_on_xmit; bit4 reserved; bit26 tail_packet_pointer; bit6 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; redefinition of scheduling portion of transmit lcd for timers typedef struct { bit32 next_lcd; bit32 #timer_period; bit32 #timestamp; bit12 reserved; bit1 lc_on_timewheel; bit1 reserved; bit2 #timer_type; bit2 #transmit_priority; bit1 #max_resolution; bit13 reserved; bit32 #dma_desc_addr; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; definition of lcd-based memory management of transmit lcd typedef struct { bit16 #threshold_1; bit16 #threshold_2; bit4 #pool_id1; bit4 #pool_id2; bit24 #bytes_queued; } tx_lcd_struct, *tx_lcd_struct_ptr;
IBM3206K0424 ibm processor for network resources preliminary packet header page 74 of 676 pnr25.chapt03.01 august 14, 2000 field definitions the following is a detailed description of the fields listed above. this data structure should be initialized at connection setup but not modified while transmission is occurring on the connection. only those fields marked with a # typically need to be initialized to something other than zero. definition of abr code variables typedef struct { bit8 #crm; bit8 #icdf; bit16 #imcr; bit16 #pcr; bit8 #irdf; bit8 #irif; bit16 #icr; } tx_lcd_struct, *tx_lcd_struct_ptr; abr code variables definitions (page 1 of 4) field name field description next_lcd this field is used by the hardware to chain lcds together on queues. it contains the address of the next lcd if one exists. peak_interval # this field contains the minimum spacing allowed between consecutive cells on this connection. this spacing is expressed in cell times. a connection that can transmit every cell time would have a value of ? 1 ? for this field. average_interval # this field contains the minimum average spacing allowed between cells transmitted on this connec- tion. it is the inverse of the sustainable cell rate. the value for this field is expressed in cell times. nrm # this field specifies the maximum number of cells a source may send for each forward rm cell. num- ber of cells = (2**nrm)+1. trm # this field provides an upper bound on the time between forward rm cells for an active source. time = 100 ? (2**-trm) msec. tadtf # the acr decrease time factor is the time permitted between sending rm cells before the rate is decreased to icr. time = tadtf ? 0.01 sec. nc # this field is used as a counter to determine when IBM3206K0424 cells have been sent. it should be initialized at connection setup time to ? 0 ? . ncrm # this field is used as a counter to determine when crm rm cells have been sent. it should be initial- ized at connection setup time to crm. timestamp # this field contains a timestamp used by the hardware to determine if transmit opportunity credits exist and if the burst tolerance has been exceeded. it should be initialized at connection setup time to the value in the current timeslot counter. tlrm1 & 2 these fields are used by the hardware to determine when the last rm cell was sent. they should be initialized to ? 0 ? . lc_on_timewheel # this field indicates if the lcd is currently queued to the timewheel. it should be initialized to ? 0 ? . remove_lcd # if this bit is set, the lcd will be removed from the time wheel at next transmission opportunity. it should be initialized to ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 75 of 676 alter_sched # these encoding bits alter the scheduling of cells on a virtual circuit (vc) 000 = normal scheduling scheduling is not altered. 001 = vc on vp this vc is contained on a virtual path and will share the vp band- width after one packet is sent. the scheduling parameters are con- tained in the descriptor for the virtual path that is pointed to by the virtual path descriptor address field in this lcd. 010 = mpeg-2 scheduling the cells being sent out on this connection are monitored for a peak cell rate (pcr). if a pcr is found, the aal5 packet is termi- nated at the end of the mpeg-2 frame and the last cell is sched- uled to go out at the time specified in the pcr. 011 = packet-based scheduling packets will be scheduled at the average interval and cells within the packet will be scheduled at the peak interval. this is useful for sending information where variably-sized packets need to be sent at regular intervals. 100 = abr scheduling this vc will send resource management cells and adjust its trans- mission rate according to the behaviors specified in the atm forum traffic management specification, version 4.0. 101 = fair vc on vp this vc is contained on a virtual path and will share the vp band- width after one cell is sent. the scheduling parameters are con- tained in the descriptor for the virtual path which is pointed to by the virtual path descriptor address field in this lcd. 110 = reserved for mpeg-2 scheduling. 111 = reserved transmit_priority # this field specifies the priority of transmission on this connection: 0=high, 1=medium, 2=low. max_resolution # if this bit is set, the lower eight bits of the average interval and peak interval parameters contain a fractional component. this allows a finer resolution for scheduling. for example, for a peak interval of 1.5 time units, the value written to the peak_interval field should be hex 0180. if this bit is set, the initial value of timestamp should contain the current timeslot counter shifted 16 bits to the left. max_burst_mult # the values in this field and the next field are used to limit the number of cells that can be transferred at the peak rate. the max_burst_value will be multiplied by four to the power of the value in this field to yield the maximum credit time. this time is expressed in cell times and represents the time it would take to acquire the maximum number of cell credits. this maximum credit time should equal the maximum number of cells that can be transferred at the peak rate (mbs) times the difference between the average and intervals. maximum credit time = mbs * (ai-pi) where mbs = maximum burst size, ai = average interval, and pi = peak interval. mbs must be at least one to transmit at peak rate. if mbs is not at least one, the peak interval should be set to the average interval. max_burst_value # the value in this field will be multiplied by four to the power of the value in the max_burst_mult field to yield the maximum credit time. head_packet_pointer this field is used to chain buffers to lcds. tail_packet_pointer this field is used to chain buffers to lcds. transmit_length this field contains the length of the currently transmitted packet. free_on_xmit this bit is set if the header of the currently transmitted packet has specified that the packet is to be freed after transmission. queue_on_xmit this bit is set if the header of the currently transmitted packet has specified that the packet is to be queued after transmission. dma_on_xmit this bit is set if the header of the currently transmitted packet has specified that a dma descriptor is to be queued after transmission. abr code variables definitions (page 2 of 4) field name field description
IBM3206K0424 ibm processor for network resources preliminary packet header page 76 of 676 pnr25.chapt03.01 august 14, 2000 conn_suss this bit is used on abr connections to suspend transmission. it should be initialized to ? 0 ? . drop these two bits are used to indicate which physical drop will be used for this connection. traffic can be scheduled on up to four drops. buffer_offset this field contains the offset into the buffer that the transmit data starts. xmt_cmp_evt_mod this two-bit field can optionally (based on a bit in the segbf control register) be logically ored with bits 8-7 of a transmit complete buffer event when it is generated by the segmentation logic. this field will only be ored when buffer address events are being generated. it will have no affect when lcd addresses are being enqueued when a transmit complete event occurs. seg_prc_entry_point # this four-bit field is loaded into the instruction pointer for both the lcd update processor and the cell generation processor when a cell opportunity occurs for the lcd. the value loaded into this field defines what type of cell will be generated by the segmentation logic. possible types include raw 48- and 52-byte cells, aal5 cells, switch bound cells (48-byte payload), extended switch bound cells (54-byte payload), and frame-based cells. the actual values that are associated with each type of cell will be defined at a later time. atm_header # this field contains the first four bytes of the atm header. segmentation_pointer this field contains a pointer to the next data to be transmitted. in normal operation, this field is initial- ized by the cell scheduler when a new frame is queued for segmentation. current_crc this field contains the crc as it is being built. current_blocking_count this eight-bit field contains the current count of four-byte values that have been assembled into cells and sent out on this lcd for all fix block or mpeg aal types. other than initialization, this field should only be accessed by the hardware. fixed_blocking_size # this eight-bit field should be initialized by the software to contain the number of four-byte values that constitute a packet. for mpeg2, this register should be set to x ? 2f ? (4 ? x ? 2f ? = 188 byte transport stream packet). current_transport_stream_packet this eight-bit field contains the number of the current transport stream packet that is being seg- mented. other than initialization, this field should only be accessed by the hardware. packets_per_aal5_frame # this eight-bit field should be initialized by the software to indicate how many packets should be con- catenated into an aal5 frame. explicit_rate this 16-bit field contains the explicit cell rate as defined for abr traffic on this lcd. current_rate this 16-bit field contains the current cell rate as defined for abr traffic on this lcd. minimum_rate this 16-bit field contains the minimum cell rate as defined for abr traffic on this lcd. backward_ptr when software needs to send a backward rm cell, this 32-bit field should be updated with the address of a buffer that contains the desired backward rm cell. after the segmentation logic trans- mits the cell, this field is cleared by the hardware. xmit_stat1 this 32-bit field contains a count of one of three things: the total number of user cells that have been sent on this lcd, the total number of bytes that have been sent on this lcd, or the total number of frames that have been sent on this lcd. this field should zeroed when the connection is initialized. an event will be generated when this count wraps. xmit_stat2 this 32-bit field contains a count of one of three things: the total number of user cells that have been sent on this lcd, the total number of bytes that have been sent on this lcd, or the total number of frames that have been sent on this lcd. this field should be zeroed when the connection is initial- ized. an event will be generated when this count wraps. threshold_1&2 these fields are compared to the upper 24 bits of the bytes_queued field to determine when a threshold is crossed and the pool id for the received lcd should be changed. abr code variables definitions (page 3 of 4) field name field description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 77 of 676 pool_id1&2 these fields are used to change the pool id when a threshold is crossed. bytes_queued this field is used to keep track of the number of bytes queued for transmission on this lcd. timer_type # these encoded bits determine the time of timer: 00 = relative non-periodic timer the expiration time will be in one timer period. the timer will not be scheduled again automatically. 01 = relative periodic timer the expiration time will be in one timer period. the timer will be automatically scheduled again. 10 = absolute non-periodic timer the timer will expire at the time specified by the timestamp field. the timer will not be automatically scheduled again. 11 = absolute periodic timer the timer will expire at the time specified by the timestamp field. the timer will be scheduled again, automatically, using the time specified in the timer_period field. timer_period # this field specifies the number of timeslots before the timer expires. dma_desc_addr # the dma descriptor pointed to by this field will be queued for execution when the timer expires. crm missing rm cell count. crm limits the number of forward rm cells that may be sent in the absence of received backward rm cells. cdf is written to the ncrm field whenever a backward rm cell is detected. icdf cutoff decrease factor (cdf) controls the decrease in acr associated with crm. cdf is zero or a power of 2 value in the range of 1/64 to 1. icdf represents the power of 2 that is in the denominator of cdf. cdf = 1/(2**icdf) so icdf = log (base 2) of 1/cdf. range = 1 to 6. a zero value for cdf should be represented as 0xff for icdf. imcr this is the reciprocal of the minimum cell rate (mcr). mcr is represented in the abr rate format. imcr needs to be an integer representing the interval between cells, in units of timeslots per cell. the following formula illustrates the conversion from mcr to imcr. imcr = 1/(mcr) * 53 * 8 * (tsp/ci*(2**23)). the timeslot prescalar (tsp) is defined by the csked timeslot prescalar register. the clock interval (ci) is determined by the crset clock control reg- ister. with the tsp set to one timeslot per cell transmission time, imcr =1 for a full bandwidth, 2 for a half bandwidth, etc. pcr the peak cell rate (pcr) is the cell rate that the source may never exceed. pcr should be in the abr rate format. irdf rate decrease factor (rdf) controls the decrease in the cell transmission rate. rdf is a power of 2 value in the range of 1/32,768 to 1. irdf represents the power of 2 that is in the denominator of rdf. rdf = 1/(2**irdf) so irdf = log (base 2) of 1/rdf. range = 1 to 15. irif rate increase factor (rif) controls the increase in the cell transmission rate. rif is a power of 2 value in the range of 1/32,768 to 1. irif represents the power of 2 that is in the denominator of rif. rif = 1/(2**irif) so irif = log (base 2) of 1/rif. range = 1 to 15. icr the initial cell rate is the rate at which a source should send initially and after an idle period. icr should be in the abr rate format. abr code variables definitions (page 4 of 4) field name field description
IBM3206K0424 ibm processor for network resources preliminary packet header page 78 of 676 pnr25.chapt03.01 august 14, 2000 receive lcd data structure and modes the format of the receive lcd structure depends on which aal is being configured and which options are used. it is also dependent on if tcp/ip checksum verification has been enabled. when tcp/ip checksum verification is enabled, 16 additional bytes are added to the lcd format. tcp/ip checksum is enabled in the reasm mode register. the following are the basic layouts of the receive lcd: transmit data structure linkage lc cb next lcd@ head pointer tail pointer lc cb next lcd@ head pointer tail pointer lc cb next lcd@ head pointer tail pointer lc cb next lcd@ head pointer tail pointer packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 79 of 676 the basic layout is the same for all lcd types. only the packed info and misc fields vary between the differ- ent lcd types. the following sections detail the receive lcd and the differences from the basic layout for each major option. basic receive lcd layout struct basicrxlcd { struct basicrxlcdip { bit32 packedinfo; bit32 packedinfo; bit32 crcstate; bit32 crcstate; bit32 misc; bit32 ipwrd0; bit32 buffptr; bit32 ipwrd1; bit32 ipwrd2; bit32 stat0; bit32 ipwrd3; bit32 stat1; bit32 misc; bit32 hostdata; bit32 buffptr; bit32 misc2; bit32 stat0; bit32 reserved; bit32 stat1; bit32 reserved; bit32 reserved; bit32 hostdata; bit32 reserved; bit32 misc2; }; }; struct ipwrd0 {; bit32 ipwrd0; bit4 frametype; bit6 skipcount; bit6 reserved; bit16 reserved; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 80 of 676 pnr25.chapt03.01 august 14, 2000 raw lcd a raw lcd allows raw atm cells to be received with no reassembly. the user can select to receive 52- or 48-byte cells. the packet header may or may not contain the atm header. the cell data is then placed after the packet header at the configured receive offset. the 52-byte mode stores the entire cell minus the hec, and the 48-byte mode stores only the atm cell payload. optional crc-10 checking is available in raw modes. raw lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0000 - raw bit2 ppmode; // 00 - normal bit2 state; // 00->down 01->idle/enabled bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 size; // 1->52 byte cell 0->48 byte cell bit1 storecrc10; bit3 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 reserved; };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 81 of 676 raw routed lcd a raw routed lcd receives data in the same way that a raw lcd does. once received, the cell buffer is routed internally to the scheduler and rescheduled for transmission. normally, when a cell is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a cell is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows cells to be routed out the transmit interface with the same or different vpi/vci. the low order bits in the routedlcd field should be set correctly to free the buffer on transmission. these bits correspond to the flag bits in the packet header. raw routing is also called forwarded or fast forward mode. raw routed lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0000 - raw bit2 ppmode; // 01 - routed bit2 state; // 00->down 01->idle/enabled bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 size; // 1->52 byte cell 0->48 byte cell bit1 reserved; bit3 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 routedlcd; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 82 of 676 pnr25.chapt03.01 august 14, 2000 raw routed early drop lcd a raw routed early drop lcd receives data in the same way that a raw lcd does. once received, the cell buffer is then routed internally to the scheduler and rescheduled for transmission. normally when a cell is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a cell is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows cells to be routed out the transmit interface with the same or different vp/vc. this mode should only be used when the routed cell stream is actually an aal5 packet stream. in this mode, a cell being dropped due to resource causes the lcd to go into error mode until the cell that contains the user indicate (uind) bit is received. all cells received in error mode are dropped, except the final cell which is for- warded. this conserves bandwidth while maintaining the aal5 integrity. the finalpoolid provides a second poolid for the final cells to use to be sure that these final cells are always forwarded even when resources are low. the finalpoolid is only used if no buffers are available in the normal pool. the low order bits in the routedlcd field should be set correctly to free the buffer on transmit. these bits cor- respond to the flag bits in the packet header. this is also called forwarded or fast forward mode. raw routed early drop lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0001 - raw early drop bit2 ppmode; // 01 - routed bit2 state; // 00->down 01->idle/enabled 11->error bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 size; // 1->52 byte cell 0->48 byte cell bit4 finalpoolid; // pool id bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 routedlcd; };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 83 of 676 raw scatter/cut-through lcd a raw scatter/cut-through lcd receives data in the same way that a raw lcd does. once received, the cut- thrusel field is used to select one of four configurations. each configuration specifies a receive queue and a dma queue. the cut-through selector is used to select a cut-through/scatter configuration. the dma descrip- tor is then built using the cell buffer address and the data length and the flags specified in the cut-through configuration. after being built, it is enqueued to the dma queue specified. if there is no dma descriptor avail- able, then a no descriptor event is enqueued. raw scatter/cut-through lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0000 - raw bit2 ppmode; // 10 - scatter/cut through bit2 state; // 00->down 01->idle/enabled bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 reserved; // set to zero bit1 size; // 1->52 byte cell 0->48 byte cell bit1 storecrc10; bit1 reserved; bit2 cutthrusel; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 reserved; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 84 of 676 pnr25.chapt03.01 august 14, 2000 aal5 lcd an aal5 lcd allows aal5 packets to be received with no special processing. aal5 lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0101 - aal5 bit2 ppmode; // 00 - normal bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit3 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 reserved; };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 85 of 676 aal5 routed lcd an aal5 routed lcd allows aal5 packets to be received. once received, the packet buffer is then routed internally to the scheduler and rescheduled for transmission. normally when a packet is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a packet is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows packets to be routed out the transmit interface with the same or different vp/vc. the low order bits in the routedlcd field should be set correctly to free the buffer on transmission. these bits correspond to the flag bits in the packet header. aal5 routing is also called forwarded or fast forward mode. note: non-user data cells are terminated. aal5 routed lcd layout struct packed { bit4 aaltype; // 0101 - aal5 bit2 ppmode; // 01 - routed bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit3 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit32 routedlcd; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 86 of 676 pnr25.chapt03.01 august 14, 2000 aal5 cut-through/scatter mode lcd aal5 cut-through/scatter mode lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0101 - aal 5 bit2 ppmode; // 10 - scatter bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 reserved; bit2 cutthrusel; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 numdesc; bit2 packheadsel; bit8 reserved; bit16 oammask; }; struct misc2 { bit5 reserved; bit1 usecrcnumhead; bit10 numheadbytes; bit16 reserved; };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 87 of 676 packet lcd a packet lcd allows packets from the pos-phy to be received with no special processing. the header- thresh can be used to allow packet header thresholding events to be surfaced. packet lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0111 - packet bit2 ppmode; // 00 - normal bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit5 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 reserved; }; struct misc2 { bit5 dropnbytes; bit11 reserved; bit16 reserved; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 88 of 676 pnr25.chapt03.01 august 14, 2000 packet routed lcd a packet routed lcd allows packets to be received from the pos-phy. once received, the packet buffer is then routed internally to the scheduler and rescheduled for transmission. normally, when a packet is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a packet is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows packets to be routed out the transmit interface with the same or different lcd. the low order bits in the routedlcd field should be set correctly to free the buffer on transmit. these bits cor- respond to the flag bits in the packet header. this is also called forwarded or fast forward mode. packet routed lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0111 - packet bit2 ppmode; // 01 - routed bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit5 reserved; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 reserved; bit2 packheadsel; bit8 reserved; bit16 reserved; }; struct misc2 { bit32 routedlcd; };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 89 of 676 packet cut-through scatter mode lcd packet scatter mode lcd packed and miscellaneous field layouts struct packed { bit4 aaltype; // 0111 - aal5 bit2 ppmode; // 10 - scatter bit2 state; // 00->down 01->idle/enabled 10->reasm 11->error bit1 reserved; // set to zero bit1 rtotest; // set to zero bit1 rtoenable; bit3 reserved; bit2 cutthrusel; bit4 rxqnum; bit4 rxpoolid; bit8 rxoffset; }; struct misc { bit6 numdesc; bit2 packheadsel; bit8 reserved; bit16 reserved; }; struct misc2 { bit5 dropnbytes; bit1 usecrcnumhead; bit10 numheadbytes; bit16 reserved; };
IBM3206K0424 ibm processor for network resources preliminary packet header page 90 of 676 pnr25.chapt03.01 august 14, 2000 field definitions the following are the definitions of the lcd fields, grouped by major function. all reserved fields should be set to zero. common field definitions field name field description note aaltype specifies the aal for this lcd. the following are the valid values: 0000 = raw mode 0001 = raw mode - early drop 0101 = aal5 0110 = aal5 - 54-byte mode 0111 = packet 1 ppmode specifies the post processing mode for this lcd. the following are the valid values: 00 = normal 01 = routed 10 = scatter/cut-through 11 = reserved 1 state this specifies the reassembly state for this lcd. this field is used by the IBM3206K0424, but in order to receive cells, an lcd must be initialized to idle state. the following are the valid values: 00 = down state 01 = idle state 10 = reassembling state 11 = error state 1 cutthrusel specifies a cut-through configuration. the cut-through configuration specifies a receive queue to get a descriptor from, a dma queue to enqueue the descriptor to, and a set of cut-through flags. 1 rxqnum specifies to which receive queue normal events should be posted. note: some events may be routed to the error queue based on your rxque setup. 1 rxpoolid specifies which pool id should be used when getting buffers for received packets. 1 rxoffset specifies the offset into the IBM3206K0424 buffer where the received packet should be placed. a value of ? 0 ? is equivalent to 256 bytes. 1 stat0 lc statistic word zero. default counts the total users cells with clp=0 received on this lc. for accurate counts, this should be initialized to zero. 1 stat1 lc statistic word one. default counts the total users cells received on this lc. for accurate counts, this should be initialized to ? 0 ? . 1 hostdata if enabled, the contents of this field are placed in packet of each received packet for this lcd. one use of this is to place a correlator to a host-specific data structure for this lcd. 1 ipwrd0-3 when tcp/ip verification is enabled, these words are used by the IBM3206K0424 to store state between cells for the tcp/ip verification process. the frametype field specifies an offset for the checksum nano- program. this field is used to jump to a specific algorithm to find the ip header. the skipcount field allows the user to specify a fixed amount that is always skipped before looking for the ip header using the spec- ified algorithm. the remainder of the words should be initialized to ? 0 ? . 1 1. software should set up this field.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt03.01 august 14, 2000 packet header page 91 of 676 raw mode field definitions field name field description note size this field specifies how many bytes are stored when cell is received: 01 = 52-byte cell (no hec) 00 = 48-byte cell 1 storecrc10 when set, the crc-10 state bit is written into the packet header. a ? 1 ? is written in the error status bit in word 0 if a bad crc-10 is detected. 1 routedlcd when routing cells, this field is used to fill in the lcd field of the packet header. this allows the user to dynamically route cells back out the interface using a different lcd. the user should be sure to set the free on transmit bit in this field as if it were in a packet header. 1 1. software should set up this field.
IBM3206K0424 ibm processor for network resources preliminary packet header page 92 of 676 pnr25.chapt03.01 august 14, 2000 packet/aal5 field definitions field name field description note rtotest this is the reassembly timeout processing test-and-set bit. it is used by the IBM3206K0424 but should be initialized to ? 0 ? . 1 rtoenable if set, reassembly processing is enabled for this lc, if the lc is running aal5. 1 tmpclp used by the IBM3206K0424 to track the current state of the ored clp bit for the current aal5 packet. this field should be set to ? 0 ? at initialization. after initialization, the IBM3206K0424 maintains this field. 1 tmpcongestion used by the IBM3206K0424 to track the current state of the ored congestion bit for the current aal5 packet. this field should be set to ? 0 ? at initialization time. 1 headerthresh specifies how much data should be received before poping a packet start event. if it is set to ? 0 ? , only complete packet events will be popped. 1 buffptr this field is used by the IBM3206K0424, but should be initialized to zero by software. this field is used to track the current packet under reassembly. 1 crcstate this field is used by the IBM3206K0424 to maintain the crc residue as the current packet is reas- sembled. it should be initialized to ? 0 ? . routedlcd when routing cells, this field is used to fill in the lcd field of the packet header. this allows the user to dynamically route cells back out the interface using a different lcd. the user should be sure to set the free on transmit bit in this field as if it were in a packet header. 1 cutthruthresh used to determine how much cut-through data is dmaed. 1 dmaedheader this is used by the IBM3206K0424 for cut-through mode 7 processing. this should be initialized to ? 0 ? . 1 numdesc this is used by theIBM3206K0424 for scatter processing, and should be initialized to ? 0 ? . 1 packheadsel specifies which packet header should be used for this connection. see rxaal packet header config- uration on page 352 for more information. 1 oammask specifies how oam traffic should be filtered. see atm oam cell processing on page 322 for more information. usecrcnumhead when set, specifies that receive crc will determine how many bytes to use for numheadbytes. this is useful when a connection is carrying ip traffic, and the tcp/ip header lengths can be determined. 1 numheadbytes specifies how many bytes of data should be kept with the packet header when dmaing the final dma list for a completed scatter packet. must be less than the page size. 1 dropnbytes allows 0 - 31 bytes of packet data to be dropped from the beginning of the packet on pos-phy net- works. 1 1. software should set up this field.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 93 of 676 internal organization: entity descriptions this part contains detailed descriptions of the entities which, working together, make up the IBM3206K0424. the data flows through the chip have already been described; now the details of the registers and algorithms will be revealed. the entity descriptions are numbered for easy reference. note on set/clear type registers there are many registers in IBM3206K0424 that operate as a set/clear type. these registers have two addresses. the base address is for clearing bits in the register, and base address +4 bytes is for setting bits in the register. the setting or clearing operations occur only for those bits that have the value of ? 1 ? on the write of the register. either of the addresses can be used for reading the register. control processor bus interface entities entity 1: the iop bus specific interface controller (pcint) this entity provides pci specific interfacing between the external connection and the internal entities. it will support the following functions: pci memory target pci master address and data latching provide parity error detection and generation provide configuration space registers 64-bit data path for master and slave operation 64-bit addressing support for master and slave operation auto 64-bit slot detection supported 66mhz pci bus clock operation supported pci options taken medium address decode design point locking as a memory target supported interrupt a will be supported, with interrupt 2 as a the sideband signal registers will not burst, but cause retries when a burst is attempted bist defaults set at the pci 2 second maximum pci target response a target retry is issued if a burst crosses the end of the IBM3206K0424 ? s memory space. a target abort will be issued if ad and command bus have bad parity (address phase parity error). optionally, if serr is enabled, it will also be returned. if enabled, the perr signal will be driven on bad parity during data write cycles (data phase parity error) when the IBM3206K0424 is the target of the command. a target retry will be issued by the IBM3206K0424 if internal contention will cause a large bus access delay. pci master response a master abort will be issued if devsel is not asserted after five clocks. if enabled, the perr signal will be driven on bad parity during data read cycles (data phase parity error) when the IBM3206K0424 is the initiator of the command. .
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 94 of 676 pnr25.chapt04.01 august 14, 2000 pci master retry IBM3206K0424 will retry when requested by the slave. 1.1: pcint config word 0 identifies this device and vendor type, allocated by pci sig. length 32 bits type read only address xxxx 0000 restrictions can be read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00a11014 ? , but alterable at power-up/reset time with crisco code. see entity 15: on page 428 for details. power on reset value (little endian) x ? 1410a100 ? device id vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-16 15-0 device id this is a unique two-byte device id assigned to this adapter. 15-0 15-0 vendor id this is a unique two-byte vendor id.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 95 of 676 1.2: pcint config word 1 the status register is used to record status information for the pci bus related events. writing ? 1 ? to a bit in this register will reset that bit. the command register provides coarse control over a device ? s ability to gener- ate and respond to pci cycles. access type of the command register is read/write. see bit definitions. length 32 bits type read/write and read/reset address xxxx 0004 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 02b00000 ? power on reset value (little endian) x ? 0000b002 ? detected parity error signaled system error received master abort received target abort signaled target abort devsel timing data parity detected fast back-to-back capable udf supported 66mhz capable reserved reserved fast back-to-back enable serr enable wait cycle control parity error response vga palette snoop memory write and invalidate enable special cycles bus master enable memory space enable i/o space enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31 15 detected parity error this bit is set by the device whenever it detects a parity error, even if par- ity error handling is disabled (as controlled by bit 6 of pcint configuration word 1). 30 14 signaled system error this bit is set whenever the device asserts serr . 29 13 received master abort this bit is set by a master device whenever its transaction is terminated with master-abort, except for special cycle. 28 12 received target abort this bit is set by a master device whenever its transaction is terminated with target-abort. 27 11 signaled target abort this bit is set by a target device whenever its transaction is terminated with target-abort. 26-25 10-9 devsel timing these bits are hard-wired to ? 01 ? , assuming medium address decode. 24 8 data parity detected this bit is implemented by this bus master. it is set when this agent asserts perr or observes perr asserted, and this agent setting the bit acted as the bus master for the operation in which the error occurred, and bit 6 of pcint configuration word 1 is set.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 96 of 676 pnr25.chapt04.01 august 14, 2000 23 7 fast back-to-back capable defaults to ? 1 ? unless by crisco code. see entity 15: on page 428 for details. 22 6 reserved defaults to ? 0 ? unless set by crisco. see entity 15: on page 428 for details. 21 5 66mhz capable defaults to ? 1 ? unless set by crisco. see entity 15: on page 428 for details. 20 4 capabilities list this bit on indicates that this device implements the pointer for a new capabilities linked list at the offset 34th. see the pci spec revision 2.2 for more details on new capabilities. defaults to ? 1 ? unless set by crisco code. see entity 15: on page 428 for details for more on crisco. 19-16 3-0 reserved reserved 15-10 15-10 reserved reserved 9 9 fast back-to-back enable this bit can be set to a value, but is ignored by this dma master since it never drives these types of cycles. this slave, as indicated by bit 23, how- ever, can handle fast back-to- back addresses to it. initialization software will set this bit if all targets are fast back-to-back capable. 8 8 serr enable if this bit is ? 1 ? , the serr driver is enabled. 7 7 wait cycle control this bit is hard-wired to ? 0 ? because stepping is not supported by this mas- ter. 6 6 parity error response when this bit is ? 1 ? , normal action is taken when a parity error is detected. when it is ? 0 ? , any parity errors detected are ignored and normal operation is continued. 5 5 vga palette snoop this bit is not implemented. 4 4 memory write and invalidate enable this bit is not implemented. 3 3 special cycles this bit is set to ? 0 ? , and will not monitor special cycle operations. 2 2 bus master enable if this bit is ? 1 ? , this device will be allowed to act as a bus master. 1 1 memory space enable if this bit is ? 1 ? , this device will respond to memory space accesses. 0 0 i/o space enable if this bit is ? 1 ? , this device will respond to i/o space accesses. bit(s) pci spec name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 97 of 676 1.3: pcint config word 2 the class code is used to identify the generic function for this device. the revision id is used to identify the level of function for this device. see bit definitions. length 32 bits type read only address xxxx 0008 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 02030025 ? power on reset value (little endian) x ? 25000302 ? upper byte middle byte lower byte revision id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-24 23-16 upper byte the upper byte of the class code is a base code that broadly classifies the type of function this device performs. code chosen is: x ? 02 ? - network controller 23-16 15-8 middle byte the middle byte of the class code is a sub-class code that identifies more specifically the function of this device. code chosen is: x ? 03 ? - atm con- troller 15-8 7-0 lower byte the lower byte of the class code identifies a specific register-level pro- gramming interface so that device independent software can interact with this device. there are two secret functions here. by writing bit 15 to ? 1 ? , the class code of ? 03 ? (atm) changes to ? 00 (ethernet). the read value of bit 15 remains ? 0 ? . by writing bit 14 to ? 1 ? , bit 23 of config word 3 (also known as bit 7 of the header type byte) will reflect a value of ? 1 ? , indicating that it is a multi-function device. the read value of bit 14 remains ? 0 ? . bits 13 down to eight are still available to be set to indicate a register-level pro- gramming interface. 7-0 7-0 revision id this is the revision level of this chip.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 98 of 676 pnr25.chapt04.01 august 14, 2000 1.4: pcint config word 3 this word specifies the system cache size in units of 32-bit words, the value of the latency timer for this pci bus master, the header type which identifies the layout of bytes in configuration space, and the register for the control and status of bist (built-in self-test). see bit definitions. length 32 bits type read/write address xxxx 000c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 80000000 ? power on reset value (little endian) x ? 00000080 ? bist capable start bist reserved completion code header type (read only) latency timer cache line size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31 7 bist capable this bit is a ? 1 ? because this device supports bist. 30 6 start bist writing this bit ? 1 ? invokes bist. this bit is reset to ? 0 ? after bist is com- plete. this bit has two seconds to reset after a start bist action. 29-28 5-4 reserved reserved 27-24 3-0 completion code a value of ? 0 ? means this device has passed bist. if bit 27 is on, the prpg value failed. if bit 26 is on, the misr value failed. bits 25 and 24 are always ? 0 ? . 23-16 7-0 header type (read only) the encoding chosen is x ? 00 ? . 15-8 7-0 latency timer this register specifies a value of latency in units of pci bus clocks. 7-0 7-0 cache line size this register is used to best determine what read command should be used by this master. any cache line size is supported.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 99 of 676 1.5: pcint base address 1 (i/o for register) this register specifies the base address of where in pci i/o or memory space the IBM3206K0424 registers will be mapped. when written with ? 1 ? s and read back, the least significant bits read back as ? 0 ? will indicate the amount of i/o space required for this device to operate. for example, when a value of ? ffffffff ? is writ- ten, a value read of ? ffffff00 ? indicates that 256 bytes of address space is required. see bit definitions. the programming of this bit depends on whether the IBM3206K0424 is in 64-bit addressing mode or not. when in 64-bit addressing mode, bit 4 of the pcint 64-bit controller register is set to ? 1 ? , and this register specifies a memory address. when the IBM3206K0424 is not in 64-bit addressing mode because bit 4 of the pcint 64-bit control register is set to ? 0 ? , this register specifies an i/o address. see bit definitions and pcint 64-bit control register on page 116. when in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ?1?): length 32 bits type read/write address xxxx 0010 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. bit 17 in the pcint base address control register must be set to allow the IBM3206K0424 to decode addresses for this range. power on reset value (big endian) x ? 00000001 ? power on reset value (little endian) x ? 01000000 ? base address prefetchable memory space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-4 31-4 base address this register is used to hold the address where the target device will decode for memory accesses. the size is 32k of addressing, naturally aligned. this means that only bits 31-15 are writable. 3 3 prefetchable reserved and set to ? 0 ? . 2-1 2-1 this base address can be mapped anywhere in 32-bit address space. the value of these bits is 00b. 0 0 memory space this is memory space, so the bit is set to ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 100 of 676 pnr25.chapt04.01 august 14, 2000 when not in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ? 0 ? ): base address reserved i/o space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-2 31-2 base address. this register is used to hold the address where the target device will decode for i/o accesses. the size is 16k of addressing, naturally aligned. this means that only bits 31-14 are writable. the pci specification only allows 256 bytes of i/o base address, so this address is only for special applications. using the feature of non-postable writes for i/o cycles must accompany enough i/o space in the system memory map. 1 1 reserved. reserved and set to ? 0 ? . 0 0 i/o space. this is i/o space, so this bit is set to a ? 1 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 101 of 676 1.6: pcint base address 2 (mem for register) this register specifies the base address of where in pci memory space the IBM3206K0424 registers will be mapped. when written with ? 1 ? s and read back, the least significant bits read back as ? 0 ? will indicate the amount of memory space required for this device to operate. for example, when a value of ? ffffffff ? is written, a value read of ? ffffff00 ? indicates that 256 bytes of address space this required. see bit defini- tions. the programming of this bit depends on whether the IBM3206K0424 is in 64-bit addressing mode or not. when in 64-bit addressing mode, bit 4 of the pcint 64 bit controller register is set to ? 1 ? , and this register specifies a memory address. when the the IBM3206K0424 is not in 64-bit addressing mode because bit 4 of the pcint 64-bit control register is set to ? 0 ? , this register specifies an i/o address. see bit definitions and pcint 64-bit control register on page 116. when in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ? 1 ? ): length 32 bits type read/write address xxxx 0014 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. bit 16 in the pcint base address control register must be set to allow the IBM3206K0424 to decode addresses for this range. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-0 31-0 upper part of base address this register is used to hold the upper 32 bits of address during a 64 bit addressing dual cycle access.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 102 of 676 pnr25.chapt04.01 august 14, 2000 when not in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ? 0 ? ): base address prefetchable 00 memory space 313029282726252423222120191817161514131211109876543210 bit(s) pci spec name description 31-4 31-4 base address this register is used to hold the address where the target device will decode for memory accesses. the size is 32k of addressing, naturally aligned. this means that only bits 31-15 are writable. 3 3 prefetchable this memory space is non-prefetchable, so this bit is set to ? 0 ? . this means that there are side effects on reads. 2-1 2-1 this base address can be mapped anywhere in 32 bit address space. the value of these bits is ? 00 ? . 0 0 memory space this is memory space, so this bit is set to ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 103 of 676 1.7: pcint base addresses 3-6 (memory) this register specifies the base address of where in pci memory space the IBM3206K0424 memory will be mapped. when written with ? 1 ? s and read back, the least significant bits read back as ? 0 ? will indicate the amount of memory space required for this device to operate. for example, when a value of ? ffffffff ? is written, a value read of ? ffffff00 ? indicates that 256 bytes of address space this required. see bit defini- tions. the mapping for the base address of registers into IBM3206K0424 memory is one-to-one, assuming a mem- ory windowing option is not set in the pcint base addr control register for that base address register (bar). multiple bars are only used to use a given system memory map more efficiently. as required by the bar, the addresses are size-aligned. for example, that means a 16mb size could be represented with one bar as one 16mb size aligned on a 16mb boundary. however, four-4mb bars could represent the same 16mb size but be aligned on any 4mb boundary. the value in any of the bars does not map directly to any particular IBM3206K0424 memory structure, such as control memory. the addresses are mapped using the virtual, packet, and control base address registers in vimen. when in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ? 1 ? ): length 32 bits type read/write address reg 3 xxxx 0018 reg 4 xxxx 001c reg 5 xxxx 0020 reg 6 xxxx 0024 power on reset value (big endian) x ? 00000008 ? power on reset value (little endian) x ? 08000000 ? restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. if one of these registers is not enabled (see pcint base address control regis- ter), then a read of that register will return all ? 0 ? s. the power on value stated below assumes that the register is enabled. normally, configuration code will just read these registers to find out what is there. to enable more that the default of registers 3 and 4, the use of crisco code could be used. see entity 15: on page 428 for details. base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-0 31-0 upper part of base address this register is used to hold the upper 32 bits of address during a 64 bit addressing dual cycle access.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 104 of 676 pnr25.chapt04.01 august 14, 2000 when not in 64-bit addressing mode (that is, bit 64 of pcint 64-bit control register is set to ? 0 ? ): note: these registers power up to x ? 08000000 ? if accessed little endian. base address prefetchable type memory space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-4 31-4 base address this register is used to hold the address where the target device will decode for memory accesses. the size of addressing is naturally aligned and determined by what is set in the pcint base address control regis- ter. 3 3 prefetchable this memory space is prefetchable, so this bit is set to a ? 1 ? . this means that there are no side effects on reads, all bytes are returned on reads regardless of byte enables, and host bridges can merge processor writes into this range without causing errors. 2-1 2-1 type this base address can be mapped anywhere in 32-bit address space. the value of these bits is 00b. 0 0 memory space this is memory space, so this bit is set to a ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 105 of 676 1.8: pcint cardbus cis pointer this register contains the offset to where the card information structure (cis) is located. see bit definitions. length 32 bits type read/write address xxxx 0028 restrictions cannot be written unless by crisco, or the pci configuration space override write bit is on. see entity 15: on page 428 for details. power on reset value x ? 00000000 ? reserved address space indicator address space offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reserved reserved 30-27 address space indicator can be set by crisco code, likely to be in expansion rom space. see entity 15: on page 428 for details. 26-0 address space offset this field has the offset into expansion rom that is the location of the cis. see the pcmcia v2.10 specification for details of the cis.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 106 of 676 pnr25.chapt04.01 august 14, 2000 1.9: pcint subsystem id/vendor id this register contains the subsystem id and subsystem vendor id. see bit definitions. other possible codes that could be returned for the subsystem id are listed below. the correctness of their value is superseded by higher (ioa card) levels of documentation. length 32 bits type read/write address xxxx 002c restrictions cannot be written unless by crisco, or the pci configuration space override write bit is on. power on reset value (big endian) x ? xxxx1014 ? power on reset value (little endian) x ? 1410xxxx reserved subsystem id subsystem vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reserved reserved 31-16 subsystem id generally will be set by crisco code. if not set by crisco, this value defaults to zero. see entity 15: on page 428 for details. 15-0 subsystem vendor id default value is the ibm vendor id.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 107 of 676 1.10: pcint rom base address this register specifies the base address of where in pci memory space the IBM3206K0424 rom will be mapped. when written with ones and read back, the least significant bits read back as ? 0 ? will indicate the amount of memory space required for this device to operate. for example, when a value of ? ffffffff ? is written, a value read of ? ffffff00 ? indicates that 256 bytes of address space is required. see bit definitions. length 32 bits type read/write address xxxx 0030 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value x ? 00000000 ? base address reserved address decode enable 313029282726252423222120191817161514131211109876543210 bit(s) pci spec name description 31-10 31-11 base address this register is used to hold the address where the target device will decode for expansion rom. the size is fixed at 2k of addressing, natu- rally aligned. 9-1 10-1 reserved reserved and set to ? 0 ? . 0 0 address decode enable this bit set to ? 1 ? will enable accesses to expansion rom only if memory space enable bit (bit 1 in pcint configuration word 1) is also set.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 108 of 676 pnr25.chapt04.01 august 14, 2000 1.11: capabilities pointer this register contains the capabilities pointer. see bit definitions. length 8 bits type read only address xxxx 0034 restrictions cannot be written by crisco or when the pci configuration space override write bit is on. power on reset value (big endian) x ? 000000c0 ? power on reset value (little endian) x ? c0000000 ? capabilities pointer 876543210 bit(s) name description 7-0 capabilities pointer used to point to a linked list of new capabilities implemented by this device. the reg- ister is valid only if bit 4 of pcint config word 1 is set. bits 0 and 1 are always ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 109 of 676 1.12: pcint config word 15 this register is used to communicate interrupt line routing information, tell which interrupt pin this device uses, and specify the desired setting for latency timer values. see bit definitions. length 32 bits type read/write address xxxx 003c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00010100 ? power on reset value (little endian) x ? 00010100 ? max_lat (read only) min_gnt (read only) interrupt pin (read only) interrupt line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-24 7-0 max_lat (read only). this value specifies a period of time in units of 1/4 microsecond. max_lat is used for specifying how often this device needs to gain access to the pci bus. 23-16 7-0 min_gnt (read only). this value specifies a period of time in units of 1/4 microsecond. min_gnt is used for specifying how long a burst period this device needs, assuming a 33mhz clock rate. 15-8 7-0 interrupt pin (read only). this device used inta for its pci bus interrupt. value of this field is ? 01 ? . 7-0 7-0 interrupt line. software will write the routing information into this register as it initializes and configures the system.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 110 of 676 pnr25.chapt04.01 august 14, 2000 1.13: pcint endian control register this register allows control and status to the big/little endian address selection. it controls the byte order across the pci bus. see bit definitions. length 32 bits type read/write address xxxx 0058 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. power on reset value x ? 00000000 ? reserved see bits 4 - 0 reserved byte swap for expansion rom (on-card flash) reverse the byte order for the vpd data register byte swap for configuration registers byte swap for register accesses (memory or i/o space) byte swap for memory 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-29 reserved reserved. 28-24 same as the definitions for bits 4-0 23-5 reserved reserved. 4 byte swap for expansion rom (on-card flash) when this bit is set to ? 1 ? , the bytes of an internal expansion rom access (big endian view) will be swapped to and from the pci interface. 3 reverse the byte order for the vpd data register when this bit is set to ? 1 ? , the bytes of the vital product data interface - word 2 reg- ister access will be swapped in reverse order to which bits 2 or 1 are set. 2 byte swap for configuration registers when this bit is set to ? 1 ? , the bytes of an internal configuration register access (big endian view) will be swapped to and from the pci interface. 1 byte swap for register access (memory or i/o space) when this bit is set to ? 1 ? , the bytes of an internal register access (big endian view) will be swapped to and from the pci interface. 0 byte sway for memory when this bit is set to ? 1 ? , the bytes of an internal packet memory access (big endian view) will be swapped to which bits 2 or 1 are set.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 111 of 676 1.14: pcint base address control register this register controls all the base address registers that map to memory. see bit definitions. length 32 bits type read/write address xxxx 005c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 0001000f ? power on reset value (little endian) x ? 0f001100 ? reserved allow decoding for zero base address values enforce sequential pci register writes enforce sequential pci register reads disable retrying on the 1st cycle of a memory access enable writing to special config registers disable incremental latency time-out retries enable pcint base address 1 (i/o for regs) enable pcint base address 2 (mem for regs) encoded control for pcint base address 6 (memory) encoded control for pcint base address 5 (memory) encoded control for pcint base address 4 (memory) encoded control for pcint base address 3 (memory) 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-24 reserved reserved 23 allow decoding for zero base address values setting this bit to ? 1 ? will enables decoding of a bar address that is set to ? 0 ? . normally, the pci specification does not allow for a zero address to be a valid decode. 22 enforce sequential pci register writes setting this bit to ? 1 ? ensures that pci register writes will occur in sequential order of prior memory accesses or register reads. the cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete. 21 enforce sequential pci register reads setting this bit to ? 1 ? ensures that pci register reads will occur in sequential order of prior memory accesses or register writes. the cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 112 of 676 pnr25.chapt04.01 august 14, 2000 20 disable retrying on the 1st cycle of a memory access. setting this bit to ? 1 ? disables the retrying of a memory access to IBM3206K0424. this causes a pci spec violation, but not a data integrity problem. it solves the rare problem in which two masters are accessing control memory at the same time and retries hap- pen to both endlessly. 19 enable writing to special config registers setting this bit to ? 1 ? enables writing to certain registers that are normally read-only. an example of this is the vendor and function id register (pcint configuration word 0). 18 disable incremental latency time- out retries setting this bit to ? 1 ? disables pci retries due to cycles taking more than eight cycles on burst accesses after the first access. 17 enable pcint base address 1 (i/o for regs) setting this bit to ? 1 ? enables pcint base address 1 (i/o for registers). this does the same function as bit 0 in the pcint configuration word 1 register, but also makes the pcint base address 1 (i/o for regs) read back ? 0 ? s even when written to with values. it guards against anything that bios code may do to pcint configuration word 1 reg- ister bit 0 if i/o accesses are not desired. 16 enable pcint base address 2 (mem for regs) setting this bit to ? 1 ? enables pcint base address 2 (mem for regs) so IBM3206K0424 registers can be accessed by pci memory cycles. 15-12 encoded control for pcint base address 6 (memory) same as bits 3-0. 11-8 encoded control for pcint base address 5 (memory) 7-4 encoded control for pcint base address 4 (memory) 3-0 encoded control for pcint base address 3 (memory). encoding of bits: x'0': disable this base address. x'1': configured to respond to a 2 gb address size. x'2': configured to respond to a 1 gb address size. x'3': configured to respond to a 512 mb address size. x'4': configured to respond to a 256 mb address size. x'5': configured to respond to a 128 mb address size. x'6': configured to respond to a 64 mb address size. x'7': configured to respond to a 32 mb address size. x'8': configured to respond to a 16 mb address size. x'9': configured to respond to a 8 mb address size. x'a': configured to respond to a 4 mb address size. x'b': configured to respond to a 2 mb address size. x'c': configured to respond to a 1 mb address size. x'd': configured to respond to a 64k address size, and enables internal windowing of memory. x'e': configured to respond to a 32k address size, and enables internal windowing of memory. x'f': configured to respond to a 16k address size, and enables internal window bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 113 of 676 1.15: pcint window offsets for base addresses 3-6 these registers specify the amount of memory space required for this device to operate. see bit definitions. length 32 bits type read/write address reg 3 xxxx 0060 reg 4 xxxx 0064 reg 5 xxxx 0068 reg 6 xxxx 006c power on value x ? 00000000 ? restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. windowing offset range reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-14 windowing offset range. this register is used to hold the address offset, which is added to the pci address (when windowing is enabled) to form the internal memory address. bits 15 and 14 may or may not be used, depending on how bits are set in the pcint base address control register. when bit 20 of pcint count timeout register is set, window offset register three can be updated with the address returned from a good get buffer from pools. this will save a write from code to this register. when bit 20 of pcint count timeout register is set, window offset register four can be updated with the address returned from a dequeue from the receive queue. this will save a write from code to this register. 13-0 reserved. reserved
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 114 of 676 pnr25.chapt04.01 august 14, 2000 1.16: pcint count timeout register this register holds the count limit of pci slave retry cycles. see bit definitions. length 32 bits type read/write address xxxx 0070 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 0200ffff ? power on reset value (little endian) x ? ffff0003 ? reserved register read retry timeout value reserved enable dynamic window offset updates disable register retry accesses disable pci locking function disable slave machine crisco retry active slave transaction timeout retry timeout count 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-27 reserved reserved 26-24 register read retry timeout value the bits can be set to determine how many pci cycles a register access will wait for an internal cycle to complete for a read access. it can be programmed to wait for up to seven cycles. a value of ? 0 ? will not timeout this access with a retry. 23-21 reserved reserved 20 enable dynamic window offset updates setting this bit to ? 1 ? enables the values of pcint window offsets for base addresses 3-6 so that it updated with a good get primitive or certain receive queue dequeues. 19 disable register retry accesses setting this bit to ? 1 ? disables pci retry signaling during a register or primitive access. 18 disable pci locking function setting this bit to ? 1 ? disables this pci locking function when set to ? 1 ? 17 disable slave machine this bit is for crisco code use. when set to ? 1 ? , it disables all responses to the pci bus in slave mode. in general, never turn this bit on. bit 19 of the pcint base address control register must be set before this bit can be changed. 16 reserved reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 115 of 676 15-8 slave transaction timeout these bits hold a value that is used to count the number of pci clocks times 256 when a pci slave cycle is in progress. if the count is reached, due to some internal chip hang condition, a target abort is issued. a value of ? 0 ? disables target aborts from this function. 7-0 retry timeout count these bits hold a value that is used to count the number of pci retries. the maximum count is 256 times 16 retries. if the count is reached, a target abort is issued. a value of ? 0 ? will disable target aborts from this function. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 116 of 676 pnr25.chapt04.01 august 14, 2000 1.17: pcint 64-bit control register this register contains miscellaneous control bits. length 9 bits type read/write address xxxx 0078 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00000xxx ? , where the 'x' values depend on whether bit 0 is set and values of the enable bits in pcint 64-bit enable register. power on reset value (little endian) x ? xx0x0000 ? , where the 'x' values depend on whether bit 0 is set and values of the enable bits in pcint 64-bit enable register. enable master 64-bit data path enable master 64-bit addressing enable slave register swap word mode enable slave 64-bit data path enable slave 64-bit addressing pci ad(63-32) driver control enable slave memory swap word mode enable 64bit data phase parity checking 64-bit slot detected 876543210 bit(s) name description 8 enable master 64-bit data path this bit set to ? 1 ? will enable master 64-bit data path for dma transfers. 7 enable master 64-bit addressing this bit set to ? 1 ? will enable master 64-bit addressing. 6 enable slave register swap word mode this bit set to ? 1 ? will enable word swapping of the each of the four groups of data bytes in an eight-byte register transfer. 2 5 enable slave 64-bit data path this bit set to ? 1 ? will enable the slave 64-bit data path for registers and packet mem- ory. 4 enable slave 64-bit addressing this bit set to ? 1 ? will enable slave 64-bit addressing, making base addresses 1 and 2 available for register accesses (memory cycles only) and base addresses 3 and 4 available for packet memory. 3 pci ad(63-32) driver control this bit set to ? 1 ? will cause the ad(63-32) pci drivers to force to tri-state unless a 64-bit access is occurring. otherwise, when set to ? 0 ? , the drivers will always drive active. 2 enable slave memory swap word mode this bit set to ? 1 ? will enable word swapping of the each of the four groups of data bytes in an eight-byte slave memory transfer through bcach. 2
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 117 of 676 1 enable 64bit data phase parity checking this bit set to ? 1 ? will enable the data phase parity checking on bits 32 to 63 of the ad pci bus. 0 64-bit slot detected this bit will set when the req64# i/o pin was low bus when rst# went inactive. this bit is a read-only status bit. this bit on, combined with the status of the corre- sponding bit in the pcint 64-bit enable register will determine the value of other bits in this register. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 118 of 676 pnr25.chapt04.01 august 14, 2000 1.18: pcint 64-bit enable register see the pcint 64-bit control register on page 116 for the bitwise description that the corresponding bit in this register will enable (a value of ? 1 ? means enabled). any bit in this register anded with bit 0 of pcint 64-bit control register will determine if the other bits in pcint 64-bit control register are set. length 9 bits type read/write address xxxx 0088 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 0000012a ? power on reset value (little endian) x ? 2a010000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 119 of 676 1.19: pcint perf counters control register this register contains control bits for the pcint performance counter 1 and pcint performance counter 2. length 32 bits type read/write address xxxx 007c restrictions can be written or read during configuration cycle, memory cycle when enabled (see the pcint base address control register on page 111 ), or an i/o cycle. this reg- ister is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? reserved inject target abort inject inverted par64 inject inverted par inject serr inject perr data transfer width control - counter 2 data transfer width control - counter 1 data direction - counter 2 data direction - counter 1 counter modes master/slave types - counter 2 cycles types - counter 2 master/slave types - counter 1 cycles types - counter 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 28 inject target abort this bit on will make the target respond with a target abort sequence, provided all the other conditions are set correctly in this register. 27 inject inverted par64 this bit on will invert the value of pci par64, provided all the other conditions are set correctly in this register. 26 inject inverted par this bit on will invert the value of pci par, provided all the other conditions are set correctly in this register. 25 inject serr this bit on will flow a pci serr#, provided all the other conditions are set correctly in this register. bit 8 of the pcint config word 1 does not need to be set to cause this condition. 24 inject perr this bit on will flow a pci perr#, provided all the other conditions are set correctly in this register. bit 6 of the pcint config word 1 does not need to be set to cause this condition. 23-22 data transfer width control - counter 2 these bits will determine which kind of cycle to count based on the transfer size for counter 2. the defines are the same as bits 21-20.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 120 of 676 pnr25.chapt04.01 august 14, 2000 21-20 data transfer width control - counter 1 these bits will determine which kind of cycle to count based on the transfer size for counter 1. x ? 0 ? : all transfers x ? 1 ? : 32 bit transfers only x ? 2 ? : 64 bit transfers only x ? 3 ? : enable data direction (bits 18 or 19) 19 data direction - counter 2 these bits will determine which kind of cycle to count based on the data direction - in or out of the IBM3206K0424 for counter 2. 18 data direction - counter 1 these bits will determine which kind of cycle to count based on the data direction - in or out of the IBM3206K0424 for counter 1. x ? 0 ? : data in x ? 1 ? : data out 17-16 counter modes these bits will determine which kind of mode both counters will operate in. x ? 0 ? stop on overflow x ? 1 ? interrupt on wrap x ? 2 ? event on wrap x ? 3 ? inject active errors on overflow 15-12 master/slave types - counter 2 these bits determine which kind of pci cycle owners to be counted for counter 2. the definitions are the same as bits 7-4. 11-8 cycles types - counter 2 these bits determine what kind of pci events are to be counted for counter 2. the definitions are the same as bits 3-0. 7-4 master/slave types - counter 1 these bits determine which kind of pci cycle owners to be counted for counter 1. x ? 0 ? all devices on the pci bus x ? 1 ? all devices but IBM3206K0424 x ? 2 ? IBM3206K0424 only (master or slave) x ? 3 ? IBM3206K0424 master x ? 4 ? IBM3206K0424 slave (all types) x ? 5 ? IBM3206K0424 slave register accesses x ? 6 ? IBM3206K0424 slave memory accesses 3-0 cycles types - counter 1 these bits will determine what kind of pci events are to be counted for counter 1. x ? 0 ? off x ? 1 ? all pci clock cycles x ? 2 ? active pci bus cycles (frame + irdy + trdy) x ? 3 ? pci data xfer opportunities ((irdy + trdy) & devsel) x ? 4 ? pci data xfers (irdy & trdy) x ? 5 ? pci retries (irdy & no trdy & devsel & stop) x ? 6 ? pci address phase (frame & not frame delayed) x ? 7 ? pci disconnects (irdy & trdy & devsel & stop) bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 121 of 676 1.20: pcint perf counter 1 this register contains pci performance counter 1. length 32 bits type read/write address xxxx 0080 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? counter 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 counter 1 see pcint perf counters control register on page 119 for information on how this counter will increment.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 122 of 676 pnr25.chapt04.01 august 14, 2000 1.21: pcint perf counter 2 this register contains pci performance counter 2. length 32 bits type read/write address xxxx 0084 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 111 ), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? counter 2 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-0 counter 2 see pcint perf counters control register on page 119 for information on how this counter will increment.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 123 of 676 1.22: pci master options control this register contains the control register when the IBM3206K0424 is the pci master. length 32 bits type read/write address xxxx 008c restrictions none power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? disable devto errors to gpdma disable master detected target abort errors to gpdma disable master detected perr errors to gpdma reserved disable master detected parity errors to gpdma reserved encoded control for dma reads reserved arbitration priority vshurryup rqhurryup prhurryup rd8bytes unused 4byte32 a32swapwords assume32 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 disable devto errors to gpdma setting this bit to ? 1 ? will disable device timeout errors from stopping a gpdma transfer. 30 disable master detected target abort errors to gpdma setting this bit to ? 1 ? will disable master detected target abort errors from stopping a gpdma transfer. 29 disable master detected perr errors to gpdma setting this bit to ? 1 ? will disable master detected perr errors from stopping a gpdma trans- fer. 28 reserved reserved 27 disable master detected parity errors to gpdma setting this bit to ? 1 ? will disable master detected parity errors from stopping a gpdma transfer 26 reserved reserved
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 124 of 676 pnr25.chapt04.01 august 14, 2000 25-24 encoded control for dma reads encoding of bits: x ? 0 ? : let the IBM3206K0424 pick the best memory read command based on the cacheline size bits and the dma count. x ? 1 ? : fix the read dma command to memory read multiple. x ? 2 ? : fix the read dma command to memory read line. x ? 3 ? : fix the read dma command to memory read. 23-16 reserved reserved 15-8 arbitration priority pci master will cease using a default round-robin scheme for internal requestor arbitration if these bits are not all ? 0 ? . bits 15-14 are the priority level for gpdma. bits 13-12 are the priority level for pcore. bits 11-10 are the priority level for rxque. bits 9 - 8 are the pri- ority level for intst. valid levels are 3,2,1, and 0. only 4 levels must be used. 7 vshurryup pci master will inform gpdma to hurryup if vstat is waiting. 6 rqhurryup pci master will inform gpdma to hurryup if rxque is waiting. 5 prhurryup pci master will inform gpdma to hurryup if pcore is waiting. 4 rd8bytes pci master will force all byte enables active for reads. 3 unused pci master does not use this bit. 2 4byte32 pci master will transfer a four-byte dma as a 32-bit transfer. 1 a32swapwords pci master will always swap words for any assume32 transfer. 0 assume32 pci master will not request a 64-bit transfer. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 125 of 676 1.23: power management program control this register contains the control register for power management signalling. length 32 bits type read/write address xxxx 0090 restrictions can be written or read during configuration cycle or memory cycle when enabled (see pcint base address control register on page 111 ), or as an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? reserved asserted ext_pme# powerstates deasserted ext_pme# powerstates reserved set external pme# input receiver polarity enable external pme# input reserved enable powerstate change interrupt set pme# driver behavior turn on power management event (pci pme#) 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-16 reserved reserved 15-14 asserted ext_pme# power- states these bits reflect what power state the ext_pme# pin will indicate that it is in when the ext_pme# is asserted. 13-12 deasserted ext_pme# power- states these bits reflect what power state the ext_pme# pin will indicate that it is in when the ext_pme# is de-asserted. also, these are the default bits read back for the pmi2 power- states bits 1-0 when ext_pme# is not enabled. 11-10 reserved reserved 9 set external pme# input receiver polarity setting this bit to ? 1 ? will make the chip input called ext_pme# to be used as a positive active signal. otherwise it is negative active. 8 enable external pme# input setting this bit to ? 1 ? will enable the chip input called ext_pme# to be used as a source to driver the pm# state. 7-3 reserved reserved 2 enable powerstate change interrupt setting this bit to ? 1 ? will enable a change of power states to cause an interrupt bit to turn on in intst.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 126 of 676 pnr25.chapt04.01 august 14, 2000 1 set pme# driver behavior setting this bit to ? 1 ? will make the pme# driver behave like a push-pull driver. setting this bit to ? 0 ? will make the pme# driver behave like an open-drain. 0 turn on power management event (pci pme#) setting this bit will assert the pci bus signal pme#. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 127 of 676 1.24: message signaled interrupts-word 1 this register contains the part of the message signaled interrupts structure. see bit definitions. length 32 bits type read only/read/write address xxxx 00c0 restrictions cannot be written unless by crisco, or the pci config space override write bit is on. power on reset value (big endian) x ? 0082d005 ? power on reset value (little endian) x ? 05d08200 ? message control next pointer capability id 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-16 message control see pci spec revision 2.2 for more details. bits 31-24 are 0, and bit 23 is 1. bits 22-20 are the multiple message enable field, and bits 19-17 are the multiple message capable field. bit 16 is msi enable. only bits 16, 20, 21, and 22 are writable. 15-8 next pointer pointer to the next item in the capabilities list. 7-0 capability id set to 05h to identify this function as message signaled interrupt capable.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 128 of 676 pnr25.chapt04.01 august 14, 2000 1.25: message signaled interrupts-word 2 this register contains the part of the message signaled interrupts structure. see bit definitions. length 32 bits type read/write address xxxx 00c4 restrictions power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? message address 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-0 message address see pci spec revision 2.2 for more details. bits 31-24 are ? 0 ? , and bit 23 is ? 1 ? . bits 22-20 are the multiple message enable field, and bits 19-17 are the multiple message capable field. bit 16 is msi enable. only bits 16, 20, 21, and 22 are writable.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 129 of 676 1.26: message signaled interrupts-word 3 this register contains the part of the message signaled interrupts structure. see bit definitions. length 32 bits type read/write address xxxx 00c3 restrictions power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? message upper address 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-0 message upper address see pci spec revision 2.2 for more details. bits 31-0 hold the upper 32 bits of system address for the msi memory write dma transaction.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 130 of 676 pnr25.chapt04.01 august 14, 2000 1.27: message signaled interrupts-word 4 this register contains the part of the message signaled interrupts structure. see bit definitions. length 16 bits type read/write address xxxx 00cc restrictions power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? message data 1514131211109876543210 bit(s) name description 15-0 message data see pci spec revision 2.2 for more details. bits 15-0 hold the data for the msi memory write dma transaction.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 131 of 676 1.28: power management interface-word 1 this register contains the part of the power management interface structure. see bit definitions. length 32 bits type read only address xxxx 00d0 restrictions cannot be written unless by crisco, or the pci config space override write bit is on. power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? power management capabilites next pointer capability id 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-16 power management capabilities see pci bus power management interface spec, version 1.0 for more details. bits 31-27 are for pme_support. bit 26 is for d2_support. bit 25 is for d1_support. bits 24-22 are reserved. bit 21 is the device specific initialization bit. bit 20 is reserved. bit 19 is for pme clock. bits 18-16 are version compliance level. 15-8 next pointer pointer to the next item in the capabilities list. 7-0 capability id set to 01h to identify this function as pci bus power management interface.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 132 of 676 pnr25.chapt04.01 august 14, 2000 1.29: power management interface-word 2 this register contains the part of the power management interface structure. see bit definitions. length 16 bits type read only/read clear/read write address xxxx 00d4 restrictions power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? power management capabilities 1514131211109876543210 bit(s) name description 15-0 power management capabilities see pci bus power management interface spec version 1.0 for more details. bit 15 is for pme_status. bit 14-13 are not used. bits 12-9 are not used. bit 8 is pme_en. bits 7-2 are reserved. bit 1-0 are the powerstate.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the iop bus specific interface controller (pcint) page 133 of 676 1.30: vital product data interface-word 1 this register contains the part of the vital product data interface structure. see bit definitions. length 32 bits type read only/read write address xxxx 00d8 restrictions cannot be written unless by crisco, or if the pci config space override write bit is on. power on reset value (big endian) x ? 00000003 ? power on reset value (little endian) x ? 00000000 ? flag bit vdp address next pointer capability id 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 flag bit see pci spec revision 2.2, appendix 1 for more details. read/write flag bit. for vpd reads, this bit is set to ? 0 ? and the vpd address is set. when the hardware sets the bit to ? 1 ? , valid vpd data can be read. for vpd writes, the vpd data is written first. then this bit is set to ? 1 ? , along with the vpd address. the write is active until the hardware resets this bit. 30-16 vdp address see pci spec revision 2.2, appendix 1 for more details. vpd address. 15-8 next pointer pointer to the next item in the capabilities list. 7-0 capability id set to 03h to identify this function as vital product data interface.
IBM3206K0424 ibm processor for network resources preliminary the iop bus specific interface controller (pcint) page 134 of 676 pnr25.chapt04.01 august 14, 2000 1.31: vital product data interface-word 2 this register contains the part of the vital product data interface structure. see bit definitions. length 32 bits type read/write address xxxx 00dc restrictions power on reset value (big endian) x ? 00000000 ? power on reset value (little endian) x ? 00000000 ? vpd data 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-0 vpd data see pci spec revision 2.2, appendix 1 for more details. four bytes of data are always read or written through this data field.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 135 of 676 entity 2: interrupt and status/control (intst) this entity contains the masking registers that choose which interrupt/status source will be gated onto one of the two available interrupt i/o pins. a new delayed interrupt function has been added. this function allows IBM3206K0424 status registers to be read and placed in system memory before the interrupt signal is raised. for details, see dma queues (dmaqs) on page 154. a bus timer function is provided in this entity that times a single bus access to make sure that the cycle is ter- minated before the system timer times out. this allows the user code an opportunity to recover from the error as opposed to the subsystem common code. below is a summary of this entity ? s functions: interrupt prioritized status registers interrupt source register interrupt enable registers bus timer function control processor error register with enable register 2.1: intst interrupt 1 prioritized status used to help quickly parse which interrupting entity of the IBM3206K0424 is active. length 32 bits type read only address xxxx 0400 restrictions none power on reset value x ? 00000000 ? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status reading this register will give a prioritized value of the bits in the intst interrupt source and intst enable for interrupt 1 (minta) registers anded together, returning a value that will be a hex number equal to bit number n + 1. for example, if bit 31 is on, x ? 20 ? will be read back.
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 136 of 676 pnr25.chapt04.01 august 14, 2000 2.2: intst interrupt 2 prioritized status used to help quickly parse which interrupting entity of the IBM3206K0424 is active. length 32 bits type read only address xxxx 0404 restrictions none power on reset value x ? 00000000 ? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status reading this register will give a prioritized value of the bits in the intst interrupt source and intst enable for interrupt 1 (mint2) registers anded together, returning a value that will be a hex number equal to bit number n + 1. for example, if bit 31 is on, x ? 20 ? will be read back.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 137 of 676 2.3: intst control register this register is used to control various IBM3206K0424 functions. see note on set/clear type registers on page 93 for more details on addressing. length 18 bits type clear/set address xxxx 0408 and 0c restrictions none power on reset value x ? 0010200 ? delayed interrupts - assume a 64bit pci target delayed interrupts - assume a 32bit pci target delayed interrupts - swap words control delayed interrupts - enable interrupt 1 delayed interrupts - enable interrupt 2 delayed interrupts - endian bit delayed interrupts - route interrupt 2 to interrupt 1 delayed interrupts - returned status word type pi bytes reserved disable the enstate output pins master chip enable for receiving master chip enable for transmitting master chip enable zeros on data parity treat mint2 as push-pull enable the pll output (hardware test only) disable the enstate clocks output pins 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 18 delayed interrupts - assume a 64bit pci target this bit set will help the mastering logic determine how to best move data to a 64-bit pci target. this bit is set when software has system knowledge of its targets. 17 delayed interrupts - assume a 32bit pci target this bit set will help the mastering logic determine how to best move data to a 32-bit pci target. this bit is set when software has system knowledge of its targets. 16 delayed interrupts - swap words control this bit determines the word order of the status word dma transfer for delayed ints. the default value of ? 1 ? is to swap the words. a value of ? 0 ? will not swap them. 15 delayed interrupts - enable inter- rupt 1 when set, the delayed int mechanism for int 1 is enabled. 14 delayed interrupts - enable inter- rupt 2 when set, the delayed int mechanism for int 2 is enabled. 13 delayed interrupts - endian bit this bit determines the endian of the status word dma transfer for delayed ints. when this bit is set, the endian is little. the default of ? 0 ? is big endian. 12 delayed interrupts - route inter- rupt 2 to interrupt 1 when set, the int 2 signal is routed and raised as int 1. this bit allows both sets of int masks in intst to be used, while still using only a single hardware int. when set, both delayed int's should be enabled if they are being used. 11 delayed interrupts - returned sta- tus word type when this bit is set, the intst interrupt source word will be anded with the corre- sponding enable register. otherwise, the intst interrupt source register alone will be returned.
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 138 of 676 pnr25.chapt04.01 august 14, 2000 10-9 pi bytes these bits are encoded to tell how many bytes long the aal 5 cpi field is. the follow- ing are the encodings: ? 00 ? cpi field is zero bytes long. in this case, the two bytes containing the cpi field and the aal5 user-to-user byte are copied into the packet header. see the definition of the packet header for the locations. ? 01 ? cpi field is one byte long and is always ? 0 ? . in this case, the one byte aal5 user-to-user byte is copied into the packet header. '10' cpi field is two bytes long and is always ? 0 ? . '11' treated the same as b'00' 8 reserved reserved 7 disable the enstate output pins when this bit is set to '0', the chip i/o enstates will be driven with the output of the internally muxed debug states. when set to '1', these outputs will be quiet. 6 master chip enable for receiving when this bit is set to '1', various state machines in the receive part of the chip will be enabled. 5 master chip enable for transmit- ting when this bit is set to '1', various state machines in the transmit part of the chip will be enabled. 4 master chip enable when this bit is set to '1', various state machines in the chip will be enabled. this must be set to '1' transmit or receive anything. 3 zeros on data parity when this bit is set to '1', zeros will be forced on the data bus parity line(s) during a slave read data phase or a master address phase or a master write data phase. 2 treat mint2 as push-pull when this bit is set to '1', the chip i/o mint2 will be driven active high as well as low, like a push-pull driver. this is for use as a specific sideband application, not as a gen- eral shared open-drain interrupt line. 1 enable the pll output (hardware test only) when this bit is set to '1', the chip i/o ppllout will be driven with the output of the internal pll. when set to '0', this output will be quiet. 0 disable the enstate clocks out- put pins when this bit is set to '0', the chip i/o pintclk and pdblclk will be driven with the output of the internal clock tree. when set to '1', these outputs will be quiet. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 139 of 676 2.4: intst interrupt source this register indicates the source(s) of the interrupt(s) pending. it can also be used as a status register when the bits are enabled. see note on set/clear type registers on page 93 for more details on addressing. note that bits in this register always reflect the state of the source register bit: writing a value will have no effect. reserved bits will not take on the written value. the delay of running through a latch has been removed. for the delayed interrupts feature, writing this register at the end of an interrupt handling routine will guarantee that interrupt1 and interrupt2 (if enabled) will pulse off, allowing the logic to get ready for the next interrupt dma. length 32 bits type read only address xxxx 0410 and 14 restrictions none power on reset value x ? 00000000 ? intst pcore comet or pakit intst gp timer bcach rxque 2 reserved rxque 4 gpdma dmaqs reasm reserved rxque 1 reserved reserved reserved pools pcore chksm external inta csked reserved segbf reserved linkc reserved intst gp timer reserved vimem reserved pbist spurious interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 intst a control processor related condition has occurred. a read of the intst cpb status and intst cpb status enable must be done for more information. see intst cpb status on page 142 and intst cpb status enable on page 144 . 30 pcore the pcore entity has hardware interrupts that need handling. 29 comet or pakit the comet or pakit entities have interrupts that need handling. 28 intst gp timer the intst general purpose timer counter has reach the intst general purpose timer compare value and caused an interrupt. 27 bcach the bcach entity has interrupts that need handling. 26 rxque 2 the rxque entity has interrupts that need handling. 25 reserved reserved 24 rxque 4 the rxque entity has interrupts that need handling. 23 gpdma the gpdma entity has interrupts that need handling. 22 dmaqs the dmaqs entity has interrupts that need handling. 21 reasm the reasm entity has interrupts that need handling. 20 reserved reserved 19 rxque 1 the rxque entity has interrupts that need handling. 18 reserved reserved 17 reserved reserved
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 140 of 676 pnr25.chapt04.01 august 14, 2000 2.5: intst enable for interrupt 1 (minta) this register serves as an enable for interrupt 1. see the intst interrupt source register on page 139 for the bitwise description that the corresponding bit in this register will enable. see note on set/clear type regis- ters on page 93 for more details on addressing. 16 reserved. reserved. 15 pools the pools entity has interrupts that need handling. 14 pcore the pcore entity has user defined interrupts that need handling. 13 chksm the chksm entity has interrupts that need handling. 12 external inta this bit will be set when the IBM3206K0424 detects that minta is low and, conditionally, when the same bit in intst enable for pcore normal interrupt or intst enable for pcore critical interrupt is set. this bit is for use by the pcore entity, and it is recom- mended that interrupts directed out which drive output (minta) be disabled. 11 csked the csked entity has interrupts that need handling. 10 reserved reserved 9 segbf the segbf entity has interrupts that need handling. 8 reserved reserved 7 linkc the linkc entity has interrupts that need handling. 6 reserved reserved 5intst gp timer the intst general purpose timer counter has reached the intst general purpose timer compare value and caused an interrupt. 4 reserved reserved 3 vimem the vimem entity has interrupts that need handling. 2 reserved reserved 1 pbist this bit is set when the pbist entity did not indicate that it was done. it is also not clear- able. 0 spurious interrupt under normal conditions, this bit should never be set. however, if one of the other bits in this register turns on, then off, a spurious interrupt condition will occur. the manual vector passed to the processor will point to this bit being on. length 32 bits type clear/set address xxxx 0418 and 1c restrictions none power on reset value x ? 00000000 ? bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 141 of 676 2.6: intst enable for interrupt 2 (mint2) this register serves as a enable for interrupt 2. see the intst interrupt source register on page 139 for the bitwise description that the corresponding bit in this register will enable. see note on set/clear type regis- ters on page 93 for more details on addressing. 2.7: intst interrupt source without enables this register is used to help quickly parse which interrupting bit of intst interrupt source is active. it does not matter what state the enable registers are set to because the value returned does not depend on them. length 32 bits type clear/set address xxxx 0420 and 24 restrictions none power on reset value x ? 00000000 ? length 32 bits type: read only address xxxx 0428 restrictions none power on reset value x ? 00000000 ? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status reading this register gives a prioritized value of the bits in the intst interrupt source, returning a value that is a hex number equal to bit number n + 1. for example, if bit 31 is on, x ? 20 ? will be read back.
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 142 of 676 pnr25.chapt04.01 august 14, 2000 2.8: intst cpb status this register holds the status bits for errors on the control processor bus. these bits, when disabled, will set a bit in the intst interrupt source register. see note on set/clear type registers on page 93 for more details on addressing. length 24 bits type clear/set address xxxx 0430 and 34 restrictions none power on reset value x ? 00000 ? internal dma masters signaled error indication power mgmt state change target abort: register access retry timeout target abort: slave access timeout pci timing changed arbit detected memory errors reserved reserved master pci parity error detected master detected perr active master termination: target abort received master termination: master-initiated abort target detected pci 64 bit data parity error target disconnect: memory addressing target detected pci data parity error target abort: memory access retry timeout target abort: address parity error target disconnect or retry: end of memory performance counter 2 performance counter 1 illegal register access 23222120191817161514131211109876543210 bit(s) function description 23-20 internal dma masters signaled error indication the pcint entity will set these bits when it signals a dma error indication to one of the internal requesting masters. bit 23 is gpdma, bit 22 is pcore, bit 21 is rxque, and bit 20 is intst. 19 power mgmt state change this bit is set when the conditions in pcint are met to trigger a power management state change. 18 target abort: register access retry timeout this bit is set when this slave does more retry cycles than the specified amount in the pcint count timeout register during a register access. 17 target abort: slave access tim- eout this bit is set when this slave does not access the IBM3206K0424 in the specified amount in the pcint count timeout register. 16 pci timing changed the pci bus clock has changed range. the IBM3206K0424 should be reset and re-initial- ized. 15 arbit detected memory errors this bit is set when error conditions detected by arbit are enabled. note: this bit is a reflection of the arbitrator status bits and does not need to be reset if the arbitrator condi- tion has been reset. 14 reserved reserved 13 reserved reserved 12 master pci parity error detected this bit is set when a pci bus data parity error is detected in master mode.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 143 of 676 11 master detected perr active this bit is set when a target has driven perr . 10 master termination: target abort received this bit is set when in master mode and the transfer is aborted by the target. 9 master termination: master-initi- ated abort this bit is set when in master mode and the transfer is aborted by this master. 8 target detected pci 64 bit data parity error this bit is set when a pci data parity error is detected in 64 bit target mode (the upper dword has the data parity error). 7 target disconnect: memory addressing this is set when a memory access is occurring and bits 0 and 1 of the address are not ? 0 ? . 6 target detected pci data parity error this bit is set when a pci data parity error is detected in target mode. 5 target abort: memory access retry timeout this bit is set when this slave does more retry cycles than the specified amount in the pcint count timeout register during a memory access. 4 target abort: address parity error this bit is set when an address parity error is detected. 3 target disconnect or retry: wrap of 2 gb internal address slave counter this bit is set when the slave address counter is its maximum counter value will indicate a termination condition on the pci bus. this is primarily a debug bit and can turn on during normal operation. it most likely will be useful when the IBM3206K0424 slave mode is con- figured in 64-bit addressing mode. 2 performance counter 2 the pcint performance counter 2 has overflowed. 1 performance counter 1 the pcint performance counter 1 has overflowed. 0 illegal register access this bit is set when an IBM3206K0424 register is being accessed by fewer than four bytes at a time. this is not true for configuration registers during a configuration cycle. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 144 of 676 pnr25.chapt04.01 august 14, 2000 2.9: intst cpb status enable this register serves as an enable for the intst cpb status register. see note on set/clear type registers on page 93 for more details on addressing. see the intst cpb status on page 142 for the bitwise descrip- tion that corresponding bit in this register will enable. this enable will initialize to the disabled state. 2.10: intst IBM3206K0424 halt enable this register serves as an enable for the intst cpb status register and gates which errors will reset bit 4 (master chip enable), bit 5 (master chip enable for transmitting), and bit 6 (master chip enable for receiving), all in the intst control register register. this allows selected bits to disable the IBM3206K0424, especially in the case of severe hardware detected errors. see the intst cpb status on page 142 for the bitwise description that corresponding bit in this register will enable. this enable will initialize to the disabled state. see note on set/clear type registers on page 93 for more details on addressing. 2.11: intst cpb capture enable this register serves as an enable for the intst cpb status that will determine on which error type the intst cpb captured address register will be updated. see the intst cpb status on page 142 for the bitwise description that corresponding bit in this register will enable. see note on set/clear type registers on page 93 for more details on addressing. length 19 bits type clear/set address xxxx 0438 and 3c restrictions none power on reset value x ? 00000 ? length 19 bits type clear/set address xxxx 0440 and 44 restrictions none power on reset value x ? 0009f71 ? length 19 bits type clear/set address xxxx 0450 and 54 restrictions none power on reset value x ? 00069f71 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 145 of 676 2.12: intst cpb captured address this information can be used to attempt a retry in the exception handling microcode. this register holds the value of the IBM3206K0424 register address on the pci during a bus error condition. this only latches values from sources that are enabled in the intst cpb capture enable register. 2.13: intst general purpose timer pre-scaler this is the pre-scaler for the intst general purpose timer compare.this register will hold the value of the pre-scale count. the default value is 1 tick every 10.02us, assuming a 33mhz or 66mhz pci bus clock, pro- ducing a 66mhz system clock (count is system clock). the pre-scale count value is n-1, where n is the desired increment count. owing to a physical design problem, the function of this register was lost. it should be set to a non-zero value, so that the intst general purpose timer counter can be used with a prescale of only the default clock (one tick every 30ns, assuming a 33-mhz system clock). length 32 bits type read/write address xxxx 0458 restrictions none power on reset value x ? 00000001 ? register address reserved invalid capture 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-2 register address captured IBM3206K0424 register address. 1 reserved reserved. 0 invalid capture when this bit is reset to ? 0 ? , a valid capture has been made. length 32 bits type read/write address xxxx 0464 restrictions none power on reset value x ? 0000029b ?
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 146 of 676 pnr25.chapt04.01 august 14, 2000 2.14: intst general purpose timer compare this is the compare value for the general purpose timer. this register holds the value of the data that is com- pared to the count value in the intst general purpose timer counter, setting the intst general purpose timer status bits. see intst general purpose timer mode control on page 148 for details on the operation of this register. 2.15: intst general purpose timer counter this is the general purpose timer counter. this register holds the value of the counter. it always counts up. see intst general purpose timer mode control on page 148 for details on operation of this register. length 32 bits type read/write address xxxx 0468 restrictions none power on reset value x ? 0800 0000 ? length 32 bits type read/write address xxxx 046c restrictions none power on reset value x ? 0000 0000 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 147 of 676 2.16: intst general purpose timer status this is the status of the general purpose timer counter. see note on set/clear type registers on page 93 for more details on addressing. length 2 bits type clear/set address xxxx 0470 and 74 restrictions none power on reset value x ? 0 ? timer wrapped timer interrupt 10 bit(s) function description 1 timer wrapped this bit is set when the intst general purpose timer counter wraps around to a ? 0 ? count value. 0 timer interrupt see intst general purpose timer mode control on page 148 for details on how this bit is set. for mode 0: this bit is set when the intst general purpose timer counter matches the value in the intst general purpose timer compare register. the comparing condition must be changed (write intst general purpose timer counter or intst general pur- pose timer compare) before resetting this bit, or the bit will set again.
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 148 of 676 pnr25.chapt04.01 august 14, 2000 2.17: intst general purpose timer mode control this register controls the operating modes of the general purpose timer counter. see note on set/clear type registers on page 93 for more details on addressing. length 3 bits type clear/set address xxxx 0478 and 7c restrictions none power on reset value x ? 4 ? timer modes 210 bit(s) description 2-0 these bits are encoded to provide eight different timer operation modes. encoding is as follows: mode 0 the intst general purpose timer counter is a free-running up-counter and sets bit 0 of intst general purpose timer status when equal to intst general purpose timer compare. mode 1 the intst general purpose timer counter is a free-running up-counter and sets bit 0 of intst general purpose timer status when equal to intst general purpose timer compare. a write to intst general purpose timer compare will reset bit 0 of intst general purpose timer status. mode 2 the intst general purpose timer counter is a free-running up-counter and sets bit 0 of intst general purpose timer status when equal to or greater than intst general purpose timer compare. a write to intst general pur- pose timer compare will reset bit 0 of intst general purpose timer status. mode 3 the intst general purpose timer counter is a up-counter and sets bit 0 of intst general purpose timer status when equal to or greater than the intst general purpose timer compare. the intst general purpose timer counter is also reset when a comparison is made. a write to intst general purpose timer compare will reset bit 0 of intst general purpose timer status and intst general purpose timer counter. mode 4 the intst general purpose timer counter is disabled and no status bits will be set. modes 5-7 reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 149 of 676 2.18: intst enable for pcore normal interrupt this register serves as an enable for the pcore normal interrupt input. see intst interrupt source on page 139 for the bitwise description that the corresponding bit in this register will enable. see note on set/clear type registers on page 93 for more details on addressing. 2.19: intst enable for pcore critical interrupt this register serves as an enable for the pcore critical interrupt input. see intst interrupt source on page 139 for the bitwise description that the corresponding bit in this register will enable. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0480 and 84 restrictions none power on reset value x ? 00000000 ? length 32 bits type clear/set address xxxx 0488 and 8c restrictions none power on reset value x ? 00000000 ?
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 150 of 676 pnr25.chapt04.01 august 14, 2000 2.20: intst debug states control this register serves as the control for external debug states. length 32 bits type read/write address xxxx 0490 restrictions none power on reset value x ? 38030201 ? entity state mux control 4 (hardware debug) entity state mux control 3 (hardware debug) entity state mux control 2 (hardware debug) entity state mux control 1 (hardware debug) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-24 entity state mux control 4 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (63-48). selection encoding is the same as multiplexer 1 control. 23-16 entity state mux control 3 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (7 -32). selection encoding is the same as multiplexer 1 control. 15-8 entity state mux control 2 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (31-16).
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 151 of 676 7-0 entity state mux control 1 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (15-0) which are multiplexed over ad64 (15-0). x ? 00 ? disabled (no transition on outputs). x ? 20 ? select pools 95-80 states. x ? 01 ? select crset 15-0 states. x ? 21 ? select pools 111-96 states. x ? 02 ? select npbus 15-0 states. x ? 22 ? select pools 127-112 states. x ? 03 ? select pcint 15-0 states. x ? 23 ? select vimem 15-0 states. x ? 04 ? select pcint 31-16 states. x ? 24 ? select vimem 31-16 states. x ? 05 ? select comet 15-0 states. x ? 25 ? select vimem 47-32 states. x ? 06 ? select comet 31-16 states. x ? 26 ? select arbit 15-0 states. x ? 07 ? select pakit 15-0 states. x ? 27 ? select arbit 31-16 states. x ? 08 ? select pakit 31-16 states. x ? 28 ? select arbit 47-32 states. x ? 09 ? select rxque 15-0 states. x ? 29 ? select arbit 63-48 states. x ? 0a ? select rxque 31-16 states. x ? 2a ? select pcore 15-0 states. x ? 0b ? select raall 15-0 states. x ? 2b ? select pcore 31-16 states. x ? 0c ? select raall 31-16 states. x ? 2c ? select pcore 47-32 states. x ? 0d ? select raall 47-32 states. x ? 2d ? select pcore 63-48 states. x ? 0e ? select raall 63-48 states. x ? 2e ? select pcore 79-64 states. x ? 0f ? select reasm 15-0 states. x ? 2f ? select pcore 95-80 states. x ? 10 ? select linkc 15-0 states. x ? 30 ? select pcore 111-96 states. x ? 11 ? select segbf 15-0 states. x ? 31 ? select pcore 127-112 states. x ? 12 ? select segbf 31-16 states. x ? 32 ? select dmaqs 15-0 states. x ? 13 ? select segbf 47-32 states. x ? 33 ? select dmaqs 31-16 states. x ? 14 ? select segbf 63-48 states. x ? 34 ? select dmaqs 47-32 states. x ? 15 ? select csked 15-0 states. x ? 35 ? select dmaqs 63-48 states. x ? 16 ? select chksm 15-0 states. x ? 36 ? select sclck 15-0 states. x ? 17 ? select chksm 31-16 states. x ? 37 ? select sclck 31-16 states. x ? 18 ? select gpdma 15-0 states. x ? 38 ? select sclck 39-32 states. x ? 19 ? select bcach 15-0 states. x ? 39 ? -x ? ff ? reserved (do not toggle as well) x ? 1a ? select bcach 31-16 states. x ? 1b ? select pools 15-0 states. x ? 1c ? select pools 31-16 states. x ? 1d ? select pools 47-32 states. x ? 1e ? select pools 63-48 states. x ? 1f ? select pools 79-64 states. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary interrupt and status/control (intst) page 152 of 676 pnr25.chapt04.01 august 14, 2000 2.21: intst delayed interrupts dma system address 1 this register serves as the delayed interrupts dma system address. this register holds the value of the system dma address to which the delay interrupt status data will be moved. 2.22: intst delayed interrupts dma system address 2 this register serves as the delayed interrupts dma system address. this register holds the value of the system dma address to which the delay interrupt status data will be moved. 2.23: current pci master address counter for debug this register holds the current pci master address counter value. this register holds the value of the pci master dma address. the function of this register is primarily for debug when a severe error occurs that stops the dma engine from running. length 64 bits type read/write address xxxx 0498 and 9c restrictions none power on reset value x ? 00000000 ? length 64 bits type read/write address xxxx 04a0 and a4 restrictions none power on reset value x ? 00000000 ? length 64 bits type read only address xxxx 04a8 and ac restrictions none power on reset value x ? 00000000 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 interrupt and status/control (intst) page 153 of 676 2.24: external entity states read this register will get a snapshot value of the enstates pin i/o. this register will return whatever is on the out- put of the enstates mux output. it is strictly for debug and a convenient way to look at the current state of IBM3206K0424 internal logic. it is controlled by intst debug states control. length 64 bits type read only address xxxx 04b0 and b4 restrictions none power on reset value x ? xxxxxxxx ?
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 154 of 676 pnr25.chapt04.01 august 14, 2000 entity 3: dma queues (dmaqs) dmaqs provides the interface to the IBM3206K0424 ? s dma master capability (described in general purpose dma (gpdma) on page 175). it provides three dma queues that hold dma descriptor chains that are exe- cuted in a multiplexed fashion. together with gpdma, a very powerful interface is provided to software to complete complex tasks including tcp/ip checksumming for transmit and receive packets. the following sections describe the features of dmaqs, how to set up dmaqs, and some troubleshooting tips. dma descriptors dma descriptors can reside in either pci/system memory space or the IBM3206K0424 memory space. cer- tain types of descriptors, called cut-through dma descriptors, must be located in the IBM3206K0424 memory space. dma descriptors that are located in the IBM3206K0424 memory space are more efficient to process because they do not need to be moved across the pci bus. however, it is more costly for software to update across the bus. the best option is to mix descriptors in both locations. dma descriptors that are infrequently changed should reside in the IBM3206K0424 memory, while dynamic descriptors should be placed in system memory. descriptors located in the IBM3206K0424 memory space must fall in a definable address range. see dmaqs local descriptor range registers on page 173. dma descriptor layout flags/byte count source address destination address high order system address flags/byte count source address destination address 32 bits blocks of up to 63 descriptors one descriptor can be queued with one enqueue primitive. note: the high order system address field (word 4) is not present when the chip is in 32-bit addressing mode. high order system address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 155 of 676 dma types and options the dma descriptor is very versatile and can perform many actions. the following list shows some examples and possible flags to use. other combinations are possible: see gpdma transfer count and flag register on page 179. note: these are not the only options. some of the above can be ored together also. using the above, you can efficiently do tcp checksumming, place user events in receive queues, do register reads/writes, free buffers, and get buffers. dma types and flags hex flags dma operation 3000 clear the current tcp checksum and include this dma in the tcp checksum. 1000 include this dma in the tcp checksum and use previous checksum as seed. 0800 this dma transfer is done in little endian mode. 0400 upon completion of this dma descriptor, the destination address from this descriptor is used as a packet address to be enqueued to transmit. 0100 queue a dma complete event when dma is complete. 0080 status in the status register is inhibited for this descriptor. this can be useful if ints/polling are being used to track when a particular dma is complete. 0001 move system memory to the IBM3206K0424 memory. 0010 move the IBM3206K0424 memory to system memory. 0012 move a single IBM3206K0424 register to system memory. 0013 move IBM3206K0424 memory to system memory and free buffer. upon dma completion, the source address is used to free the IBM3206K0424 buffer. 0017 auto-increment source address and move IBM3206K0424 memory to system memory and free buffer. upon dma completion, the source address is used to free the IBM3206K0424 buffer. 0002 move single IBM3206K0424 register to IBM3206K0424 memory. 0020 move IBM3206K0424 memory to single IBM3206K0424 register. 0021 move system memory to single IBM3206K0424 register. 0031 move system memory to a new IBM3206K0424 buffer. a get buffer operation will be done to fill in the destination address using the low four bits of the destination address as a get pool id. 0050 move something to source address of next descriptor. allows indirection. 0062 move single IBM3206K0424 register to destination address of the next descriptor. allows a get buffer operation in descriptor chain. see the get buff flag for a better option. 0008 use source address as immediate data. allows up to four bytes of immediate data in the dma descriptor. 0004 auto-increment the source address. the source address picks up where it left off from the previous dma descriptor. 000c auto-increment the source address and use as immediate data. one use is to free a packet after dmaing data. see the free buff flags for better option. 0040 auto-increment the destination address. the destination address picks up where it left off from the previous dma descriptor. one use is transmit scatter into an IBM3206K0424 virtual buffer. 2200 hold the destination address. useful for freeing a scatter dma list, or doing a repetitive write to an IBM3206K0424 register. 1200 hold the source address. useful for doing a repetitive read from an IBM3206K0424 register.
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 156 of 676 pnr25.chapt04.01 august 14, 2000 descriptor based dmas this is the recommended approach to processing dmas. a single descriptor or a descriptor chain is built that describes the actions to take. the descriptor is then enqueued to the proper dma queue. the number of the descriptor in the dma chain is placed in the lower six bits of the descriptor address as it is enqueued. register based dmas while register based dmas can be enabled and used, they are not recommended because they are not as efficient and they do not leave a debug trail as the descriptors do in the dma queue. these should not be used concurrently with descriptor-based dmas for a particular queue, but register-based and descrip- tor-based dmas can be used on different queues. one possible use for register-based dmas is doing dmas from the core. polling, interrupts, or events there are several choices for handling dma completion. first, the status register can be polled. while not very efficient, it is the easiest option. second, you can use interrupts to tell when a dma is done. again, not very efficient. however, interrupts should be used to tell when a dma error has occurred. one way to deal with dma completes is to use the rxque event mechanism. by generating events, the user can dump in dma descriptor and clean up at a later time when it is convenient. the user can use the auto- matic dma events using the queue on dma complete flag, or the user can place a user event on an arbitrary queue by writing a dma descriptor that does an explicit rxque enqueue with user data. error detection and recovery ideally, there should not be any errors. errors are usually user errors in the dma descriptor which need to be fixed and are not recoverable. errors on the pci bus (that is, parity) should not occur in a normal working sys- tem, and typically you do not want to recover them. however, if recovery is desired, the current dma must be recovered in gpdma. upon successful completion of the recovered dma, dmaqs will resume operation. dma/queue scheduling options there are three dma queues. queue 0 is higher priority than the other two. this high priority queue is always scheduled to go if the current descriptor is ready. the other two queues (q1 and q2) are of equal priority and are scheduled in a round robin fashion when the descriptor is ready. this is meant to provide a transmit dma queue, receive dma queue, and a high priority dma queue. however, these queues can be used for any pur- pose by setting the routing registers properly. the queues can be arbitrated after each dma request length operation, after complete dma descriptor chains complete, or after a single dma descriptor in a chain completes. the queues can also be placed in true round robin mode, where all three queues have equal priority. address size dmaqs can be operated with either 32- or 64-bit system addresses. see pcint 64-bit control register. all dmaqs address registers are 64 bits wide. in 32-bit addressing mode, the high order portion of address reg- isters are initialized at reset to ? 0 ? , and cannot be modified. in 32 bit addressing mode, word four of the dma buffer descriptor is ignored.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 157 of 676 data width dmaqs recognizes 64 bit writes to 64 bit internal registers. dmaqs internal 64-bit registers may be written either as a 64-bit entity, or by two 32-bit writes. all dmaqs registers are memory mapped on a 64-bit bound- ary (address bits 2:0 = 0). when in 64-bit addressing mode, an address register is updated with 32 bit writes (atomicity of update cannot be guaranteed). the user should use semaphores to assure the integrity of the operation. initialization of dmaqs dmaqs is very simple to set up by following these steps: 1. set up each of the three dma queues. to do this, you need to know the size of each queue (see dmaqs upper bound registers on page 159 for choices). given this information, the dma queue is set up with two register writes in diagnostic mode (see dmaqs control register on page 164). dmaqs->lowerbound[q] = baseaddress // should be aligned with size of queue dmaqs->upperbound[q] = encodedsize; // et encoded size of dma queue or dmags->bounds[q] = baseaddress + encodedsize; // if 64 bit data is enabled the data structure for the dma queue is now set up. 2. set up the queue thresholds if they are being used: dmaqs->threshold[q]=threshold //setthresholdsizetobeinterrupted on //may also need to set int mask 3. set up the local dma descriptor range if local descriptors are being used: dmaqs->localdescriptorlowerbound = localdescriptorbase // set base addr of local desc in IBM3206K0424 memory dmaqs->localdescriptorupperbound = localdescriptorend; // set ending addr of local desc in IBM3206K0424 memory 4. set up any options that are being used in the dmaqs control register: dmaqs->control[set] = enable_dma_queues | clr_checksum_to_foxes; // set options/modes 5. finally, clear the diagnostic bit: dmaqs->control[clr] = diag_mode // clear the diag mode bit 6. need to set up memory bank selection if necessary, but normally control memory is used.
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 158 of 676 pnr25.chapt04.01 august 14, 2000 3.1: dmaqs lower bound registers these registers specify the lower bound of the corresponding dma queue data structure. these registers specify the lower bound of the corresponding dma queue data structure. the head, tail, and length of the dma queue are initialized when this register is written. when the dma queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the dma queue as a circular buffer. when this register is written, the corresponding dma queue is essentially reset. this is because the head, tail, and length of the queue are all reset. . length 32 bits type read/write address queue 0 604 queue 1 684 queue 2 704 power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the dmaqs control register. the alignment should correspond to the size specified in the upper bound register. for example, it should be 4k aligned if the upper bound specifies 4k size. the low order nine bits are not writable and read back ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 159 of 676 3.2: dmaqs upper bound registers these registers specify the encoded size/upper bound of the corresponding dma queue data structure. the actual upper bound is calculated by adding the decoded queue size to the lower bound. when the dma queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the dma queue as a circular buffer. length 3 bits type read/write address queue 0 xxxx 0604 queue 1 xxxx 0644 queue 2 xxxx 0684 power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the dmaqs control register. bit(s) description 2-0 encoding is as follows: 000 59512 bytes of memory 001 611k bytes of memory 010 632k bytes of memory 011 654k bytes of memory 100 678k bytes of memory 101 6916k bytes of memory 110 7132k bytes of memory 111 7364k bytes of memory
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 160 of 676 pnr25.chapt04.01 august 14, 2000 3.3: dmaqs head pointer registers these registers point to the head element of the corresponding dma queue. during normal operations, these registers do not need to be read or written; they are used by the IBM3206K0424 to implement the dma queues. these registers are initialized when the dmaqs lower bound registers for the corresponding dma queue is written. 3.4: dmaqs tail pointer registers these registers point to the next free element of the corresponding dma queue. length 32 bits type read/write address queue 0 608 queue 1 688 queue 2 708 power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. they can only be written when the diagnostic bit has been set in the dmaqs control register. the head pointer registers are 4-byte aligned (low order two bits are always ? 0 ? ). bits 31-17 are calculated internally and are not writable. length 32 bits type read/write address queue 0 60c queue 1 68c queue 2 70c power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. they can only be written when the diagnostic bit has been set in the dmaqs control register. the head pointer registers are four-byte aligned (low order two bits are always ? 0 ? ). bits 31-17 are calculated internally and are not writable.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 161 of 676 3.5: dmaqs length registers these registers specify the length in bytes of the corresponding dma queue. this register is cleared when the corresponding dmaqs lower bound registers is written. 3.6: dmaqs threshold registers these registers specify a queue length threshold at which the corresponding status bit is generated. these registers should be set equal to the queue length that should cause status to be generated. for exam- ple, if the value was set to five, then no interrupt would be generated until the queue was length five or more for the corresponding dma queue. the threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. when this register is set to ? 0 ? , no thresholding occurs. length 17 bits type read address queue 0 614 queue 1 694 queue 2 714 power on value x ? 00000000 ? restrictions the lengths are calculated and cannot be written. length 17 bits type read/write address queue 0 61c queue 1 69c queue 2 71c power on value x ? 0000 ? restrictions must be a multiple of four.
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 162 of 676 pnr25.chapt04.01 august 14, 2000 3.7: dmaqs interrupt status this register indicates the source(s) of the interrupt(s) pending. see note on set/clear type registers on page 93 for more details on addressing. length 26 bits type read/write address xxxx 6f0 and 6f4 restrictions none power on value x ? 00009200 ? zero address in source/destination zero address in src/dst enq fifo thresh exceeded error during delayed int transfer enq fifo full zero length dma loaded error enqueuing csked descriptor error enqueuing raall descriptor error enqueuing descriptor dma descriptor error dma descriptor queue 2 not full dma descriptor queue 2 threshold exceeded dma descriptor queue 2 full dma descriptor queue 1 not full dma descriptor queue 1 threshold exceeded dma descriptor queue 1 full dma descriptor queue 0 not full dma descriptor queue 0 threshold exceeded dma descriptor queue 0 full error occurred during descriptor transfer error occurred during dma transfer q2 error occurred during dma transfer q1 error occurred during dma transfer q0 dma transfer complete q2 dma transfer complete q1 dma transfer complete q0 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 25 zero address in source/desti- nation when set, a zero address was detected in the source or destination field of a dma descrip- tor. the remainder of the descriptor chain was skipped and an event was enqueued to the dma complete queue. this may or may not be an error condition. it is not an error if the get buffer mode is being used and no buffer was available. in this case, the descriptor can be retried or discarded by software. 24 enq fifo thresh exceeded when set, the dma enqueue fifo length threshold has been exceeded. 23 enq fifo full when set, the dma enqueue fifo is full and further enqueues will be held off. this bit is hot and cannot be reset. 22 enqueue primitive sequence error this bit is set when an improper sequence is detected for loading the dmaqs enqueue dma descriptor primitive in 64 bit addressing mode. 21 zero length dma loaded a descriptor was loaded that had a dma length equal to zero. this will not stop the dma engine, but it is technically a user error. 20 error enqueuing pcore descriptor a descriptor was enqueued from pcore with a chain length of zero. 19 error enqueuing csked descriptor a descriptor was enqueued from csked with a chain length of zero. 18 error enqueuing reall descriptor a descriptor was enqueued from reaall with a chain length of zero.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 163 of 676 17 error enqueuing descriptor a descriptor was enqueued with a chain length of zero. 16 dma descriptor error an invalid transfer was described by the value loaded into the transfer count and flag reg- ister. 15 dma descriptor queue 2 not full the dma descriptor queue 2 is not full. this bit always contains the status of the queue and is therefore is not writable. 14 dma descriptor queue 2 threshold exceeded the threshold for dma descriptor queue 2 has been exceeded. 13 dma descriptor queue 2 full the dma descriptor queue 2 is full. this bit always contains the status of the queue and is therefore is not writable. 12 dma descriptor queue 1 not full the dma descriptor queue 1 is not full. this bit always contains the status of the queue and is therefore is not writable. 11 dma descriptor queue 1 threshold exceeded the threshold for dma descriptor queue 1 has been exceeded. 10 dma descriptor queue 1 full the dma descriptor queue 1 is full. this bit always contains the status of the queue and is therefore is not writable. 9 dma descriptor queue 0 not full the dma descriptor queue 0 is not full. this bit always contains the status of the queue and is therefore is not writable. 8 dma descriptor queue 0 threshold exceeded the threshold for dma descriptor queue 0 has been exceeded. 7 dma descriptor queue 0 full the dma descriptor queue 0 is full. this bit always contains the status of the queue and is therefore is not writable. 6 error occurred during descrip- tor transfer hardware errors occurred transferring the dma descriptor. the transfer stopped after detecting the error. if the descriptor transfer is finished or is to be terminated, the byte count register must be written to clean up the failed descriptor transfer. before this bit is reset, the dma descriptor queue must contain the valid descriptor data or the ®dmt- dqcn. must be written to the value it contained prior to the descriptor enqueue. 5 error occurred during dma transfer q2 hardware errors occurred during the last transfer on queue 2. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 4 error occurred during dma transfer q1 hardware errors occurred during the last transfer on queue 1. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 3 error occurred during dma transfer q0 hardware errors occurred during the last transfer on queue 0. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 2 dma transfer complete q2 the dma transfer has completed for queue 2. 1 dma transfer complete q1 the dma transfer has completed for queue 1. 0 dma transfer complete q0 the dma transfer has completed for queue 0. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 164 of 676 pnr25.chapt04.01 august 14, 2000 3.8: dmaqs interrupt enable this register serves as a mask for dmaqs interrupt status. see dmaqs interrupt status on page 162 for the bitwise description that the corresponding bit in this register will mask. see note on set/clear type registers on page 93 for more details on addressing. 3.9: dmaqs control register used to set options for dmaqs. see note on set/clear type registers on page 93 for more details on addressing. length 26 bits type read/write address xxxx 670 and 674 restrictions none power on value x ? 00260078 ? length 32 bits type read/write address xxxx 0770 and 774 restrictions see bit descriptions. power on value x ? 000c0001 ? reset fifo restart dma reserved disable descriptor snooping disable descriptor prefetch enable cache flushes of local descriptor fifo length threshold enable full round robin scheduling rearbitrate on descriptor completion rearbitrate on descriptor chain completion delayed int endian bit route int 2 to int 1 enable delayed int 1 enable delayed int 2 memory select for IBM3206K0424 dma descriptor memory select for dma queues enable register based dmas clear checksum to all ones queue on error endian of dma descriptors enable queue 2 dmas enable queue 1 dmas enable queue 0 dmas diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s0 function description 31 reset fifo when this bit is set, the internal dma enqueue fifo is flushed, and this bit is reset. the result is this bit will always be read as a ? 0 ? . this bit can only be set in diagnostic mode.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 165 of 676 30 restart dma when this bit is set, the internal dma state machine restarts the current dma that is stopped, and this bit is reset. the result is this bit will always be read as a ? 0 ? . this bit should only be used at the specific recommendation of an IBM3206K0424 developer. 29-23 reserved reserved. 22 disable descriptor snooping when set, this bit is the dma descriptor snooping logic is disabled. when this bit is enabled, IBM3206K0424 performance may be enhanced. 21 disable descriptor prefetch when set, this bit is the next descriptor prefetch logic is disabled. otherwise performance may be enhanced by enabling this function. 20 enable cache flushes of local descriptor when set, this bit is all local dma descriptors are flushed out of bcach before being used. this only needs to be used if local dma descriptors are in packet memory and are updated via the slave interface. cut-through descriptors do not fall in this category. 19-17 fifo length threshold this value is used to set the fifo length threshold. when this threshold is exceeded, bit 23 of the interrupt status register is set. 16 enable full round robin scheduling when set, this bit is all three dma queues are of equal priority. when cleared, queue 0 is higher priority than queues 1 and 2. 15 rearbitrate on descriptor com- pletion when set, this bit is the dma queues are rearbitrated after each individual dma descriptor completes. 14 rearbitrate on descriptor chain completion when set, this bit is the dma queues are rearbitrated after full dma descriptor chains com- plete. this bit takes precedence over bit 15. when both bits 14 and 15 are cleared, the queues are rearbitrated after each dma request length operation. 13 true queue zero preference scheduling mode bit 13 is provided to ensure compatibility with previous chips. in version 2.1 and before, queue 0 would not be scheduled immediately after itself if queue 1 or queue 2 were ready when a queue 0 dma completed. this was because it took at least one cycle to reload the queue registers. in IBM3206K0424, the queue registers are loaded while the arbitration for the next dma is being done, if preloading or snooping is enabled. in this case, with bit 17 set, a queue 0 dma may be immediately followed by another queue 0 dma. with bit 17 reset, the scheduling (with all queues ready) is q0q1q0q2q0q1.... this mode is provided to give queue 0 scheduling preference without permitting it to lock out the other two queues. 12 queue 2 uses on chip sram this bit directs queue 2 to fetch all dma descriptors from the on-chip sram. bits 63-18 of the system descriptor address will be ignored. 11 queue 1 uses on chip sram this bit directs queue 1 to fetch all dma descriptors from the on-chip sram. bits 63-18 of the system descriptor address will be ignored. 10 queue 0 uses on chip sram this bit directs queue 0 to fetch all dma descriptors from the on-chip sram. bits 63-18 of the system descriptor address will be ignored. 9 memory select for IBM3206K0424 dma descriptor when this bit is set, the dma descriptors that are located in the IBM3206K0424 are located in packet memory. otherwise they are located in control memory. 8 memory select for dma queues when this bit is set, the dma queues are located in packet memory. otherwise they are located in control memory. 7 enable register based dmas when set, this bit is source, destination, count, and system descriptor address (sda) regis- ters can be written to start a dma. 6 clear checksum to all ones when this bit is set and the dmaqs checksum register is cleared, the dmaqs check- sum register is set to 0xffff. when this bit is cleared and the dmaqs checksum register is cleared, the dmaqs checksum register is set to ? 0 ? . this option should be used if the tcp/ip checksum should never be set to ? 0 ? (0xffff is ? 0 ? also). 5 queue on error when set, this bit causes any dma error to log an error event. 4 endian of dma descriptors when set, this bit indicates that dma descriptors in system memory are in little endian for- mat. the default is big endian. 3 enable queue 2 dmas this bit enables dma queue 2. 2 enable queue 1 dmas this bit enables dma queue 1. 1 enable queue 0 dmas this bit enables dma queue 0. 0 diagnostic mode when this bit is set, dmaqs is in diagnostic mode. bit(s0 function description
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 166 of 676 pnr25.chapt04.01 august 14, 2000 3.10: dmaqs enqueue dma descriptor primitive this register enqueues a dma descriptor chain to the corresponding dma queue. the write data is the address of the descriptor chain that describes the dma transfers. the low six bits contain a count of the num- ber of dma descriptors in this chain. after the dma descriptors are enqueued by writing to this register, the chain of descriptors is fetched from system memory and the dma transfers described by the chain of descrip- tors are performed. in 32 bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. 3.11: dmaqs source address register this register is used to set and keep track of the source address during a dma transfer. this is the source for the current dma transfer. a bit in the transfer count and flag register determines whether the source address is internal to the IBM3206K0424 or is a system address. in 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. length 64 bits type write address queue 0 xxxx 0620 queue 1 xxxx 06a0 queue 2 xxxx 0720 power on value queue 0 x ? 00000000000000000 ? queue 1 x ? 00000000 ? queue 2 x ? 00000000 ? restrictions none length 64 bits type read/write address queue 0 xxxx 0638 queue 1 xxxx 06b8 queue 2 xxxx 0738 power on value x ? 0000000000000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 167 of 676 3.12: dmaqs destination address register this register is used to set and keep track of the destination address during a dma transfer. this is the des- tination address for the current dma transfer. in 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. a bit in the transfer count and flag register determines whether the destination address is internal to the IBM3206K0424 or is a system address. 3.13: dmaqs buffer address register this register is used to set and keep track of the pools buffer address during a dma transfer. when the dma descriptor directs that a new buffer address be obtained from pools, this is buffer address for the cur- rent dma transfer. a bit in the transfer count and flag register determines whether a buffer address has been obtained for this descriptor. this register can be written to an rxque queue. the low-order seven bits should be set to 0x2a, the event code for assign pool buffer events. this is the destination address for the current dma transfer. in 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. a bit in the trans- fer count and flag register determines whether the destination address is internal to the IBM3206K0424 or is a system address. . length 32 bits type read/write address queue 0 xxxx 0628 queue 1 xxxx 06a8 queue 2 xxxx 0728 power on value x ? 0000000000000000 ? restrictions none length 32 bits type read/write address queue 0 xxxx 0630 queue 1 xxxx 06b0 queue 2 xxxx 0730 power on value x'0000002a' restrictions these registers should not be written during normal system operation. the low-order 7 bits are set to 0x2a and should not be modified. this is the event code for bfa events in rxque.
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 168 of 676 pnr25.chapt04.01 august 14, 2000 3.14: dmaqs transfer count and flag register this register specifies the type and number of bytes transferred during a dma transfer. the lower 16 bits are a counter of the number of bytes transferred during a dma transfer. the upper 16 bits specify the type of transfer. length 32 bits type read/write address queue 0 x xxx 644 queue 1 x xxx 06c4 queue 2 x xxx 0744 power on value x ? 00000000 ? restrictions none register destination is 64 bits wide register source is 64 bits wide clear checksum/hold dest compute checksum/hold src little endian mode tx on dma complete hold mode queue on dma complete inhibit status update when dma complete destination address specifier source address specifier byte transfer count 313029282726252423222120191817161514131211109876543210 bit(s) function description 31 register destination is 64 bits wide these bits must be used with bits 25 and 29 (see below). 30 register source is 64 bits wide 29 clear checksum/hold dest when this bit is set, the checksum and the alignment state are cleared. 28 compute checksum/hold src when this bit is set, a checksum will be computed over this dma segment. 27 little endian mode when this bit is written to ? 0 ? , this dma channel operates in big endian mode. when set to ? 1 ? , the channels operate in little endian mode. in little endian mode, both the source and destination must be aligned on four-byte boundaries. 26 tx on dma complete when set, the destination address is used as the packet address that is to be enqueued to csked to be transmitted. the lower bits are set to ? 0 ? so the buffer base is used for the csked enqueue operation.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 169 of 676 25 hold mode when set, bits 31-28 are redefined to allow the source or destination address to be held instead of incremented. bit 29 becomes hold destination address and bit 28 becomes hold source address. this allows a single dma descriptor to do an n-to-1 or 1-to-n transfer. for example, an entire scatter dma list can be freed to a receive queue enqueue register. the address being held must be a register address. when holding, the maximum length is 252 bytes. when holding, the source or destination is incremented by four when the dma completes (for auto-increment mode). bit 31 becomes destination address 64 bits wide. bit 30 becomes source address 64 bits wide. this destination is required to properly update 64 bit wide registers when hold mode is asserted. 24 queue on dma complete when this bit is set, the upper 26 bits of the dmaqs system descriptor address regis- ter will be queued to the dma event queue when the dma completes. if descriptors are not being used to set up the dma, then before starting the dma, the dmaqs system descriptor address register should be loaded before starting the dma with a value to identify this transfer. if descriptors are being used, the dmaqs system descriptor address register will be loaded automatically with the system address of the descriptor block at the time it is processed. 23 inhibit status update when dma complete normally a bit will be set in the status register when the dma completes without error. if this bit is set, this update will not be done. this bit is useful when multiple dmas are to be done and an interrupt is only desired on the last transfer. the dma error status bits are not affected by this bit. 22-20 destination address specifier these bits specify how the destination address should be used for this dma descriptor. the following are the valid patterns: 000 IBM3206K0424 memory address: the destination address specifies an IBM3206K0424 internal memory address. 001 pci bus address: the destination address specifies a pci bus address. 010 IBM3206K0424 register address: the destination address specifies an IBM3206K0424 register address. only the low 16 bits must be specified. 011 get IBM3206K0424 buffer: the low four bits of the destination address specify a pool id from which to get a buffer. if a buffer is not available, a zero destina- tion address event or appropriate status is raised. otherwise the buffer address is used as an IBM3206K0424 memory address. 100 auto increment destination address: the destination address is sourced from the previous dma instead of the destination address specified in the descriptor. 101 next source address: the destination address is the address of the source address field of the next descriptor in the current dma chain. using this feature allows indirection. 110 next destination address: the destination address is the address of the desti- nation address field of the next descriptor in the current dma chain. using this feature allows operations like doing a get buffer in the dma descriptor chain. 111 offset destination address: the destination address is a positive offset from the dmaqs buffer address register. using this feature allows, for example, storing the checksum value in the header of the packet. others reserved: reserved and flagged as errors. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 170 of 676 pnr25.chapt04.01 august 14, 2000 19-16 source address specifier these bits specify how the source address should be used for this dma descriptor. the following are the valid patterns: 0000 IBM3206K0424 memory address: the source address specifies an IBM3206K0424 internal memory address. 0001 pci bus address: the source address specifies a pci bus address. 0010 IBM3206K0424 register address: the source address specifies an IBM3206K0424 register address. only the low 16 bits must be specified. 0011 IBM3206K0424 memory address and free buffer when dma complete: the source address specifies an IBM3206K0424 internal memory address, and this address will be freed to pools when the dma is complete. -100 auto increment source address: the source address is sourced from the pre- vious dma instead of the source address specified in the descriptor. -111 auto increment source address and free buffer when dma complete: the source address is sourced from the previous dma instead of the source address specified in the descriptor. the source address specifies an IBM3206K0424 internal memory address, and this address will be freed to pools when the dma is complete. 1000 immediate data: use the source address field as immediate data. the data is 4 bytes in 32-bit addressing mode or eight bytes when in 64 bit addressing mode. if the count is greater than the data size, the data is repeated. 1-11 immediate data and free buffer when dma complete: use the source address field as immediate data. the data is 4 bytes in 32 bit addressing mode or eight bytes when in 64-bit addressing mode. if the count is greater than the data size, the data is repeated. the source address will be freed to pools when the dma is complete. others reserved: reserved and flagged as errors. 15-0 byte transfer count these bits indicate the number of bytes to transfer. a non-zero value in this field will start the dma transfer. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 171 of 676 3.15: dmaqs system descriptor address the upper 57 bits contain the address of the current descriptor block and the lower seven bits contain the number of descriptors in the chain that remain to be processed. when doing register-based dmas, the low six bits are set to "000001" when the dmaqs transfer count and flag register is written. if dma descriptors are used for dma transfers, this register will contain the system address of the current descriptor block and the number of descriptors that remain to be processed. this address may be queued on dma completion to correlate dma transfers with system control blocks. in 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. 3.16: dmaqs checksum register this register contains the accumulated checksum. this register contains the accumulated checksum value. it can also be used to initialize the checksum with a seed value. the most significant bit contains the alignment state (1 = odd, 0 = even alignment). the alignment state is significant between subsequent checksummed dmas. this register can be read at four different addresses. the base address returns the unmodified accumulated checksum. the base address +4 returns the inverted accumulated checksum. the base address + 8 returns the byte-swapped accumulated checksum. the base address + 12 returns the inverted byte-swapped accu- mulated checksum. length 64 bits type read/write address queue 0 xxxx 0648 queue 1 xxxx 06c8 queue 2 xxxx 0748 power on value x ? 0000000000000000 ? restrictions this register should not be written if descriptors are going to be used to set up dma transfers. if it is used, it must be written to 0 before descriptors are enqueued. length 17 bits type read/write address q0 sum xxxx 0654 q0 inv sum xxxx 065c q0 swapped sum xxxx 0664 q0 inv swapped xxxx 066c q1 sum xxxx 06d4 q1 inv sum xxxx 06dc q1 swapped sum xxxx 06e4 q1 inv swapped xxxx 06ec q2 sum xxxx 0754 q2 inv sum xxxx 075c
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 172 of 676 pnr25.chapt04.01 august 14, 2000 q2 swapped sum xxxx 0764 q2 inv swapped xxxx 076c power on value q0 sum x ? 00000000 ? q0 inv sum x ? 0000ffff ? q0 swapped sum x ? 00000000 ? q0 inv swapped x ? ffff0000 ? q1 sum x ? 00000000 q1 inv sum x ? 0000ffff ? q1 swapped sum x ? 00000000 ? q1 inv swapped x ? ffff0000 ? q2 sum x ? 00000000 ? q2 inv sum x ? 0000ffff ? q2 swapped sum x ? 00000000 ? q2 inv swapped x ? ffff0000 ? restrictions only the base address accepts write data. all four addresses return read data.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 dma queues (dmaqs) page 173 of 676 3.17: dmaqs local descriptor range registers these registers specify the lower and upper bounds respectively of the memory range for local dma descrip- tors. these registers contain the address of the lower and upper bound of the memory range of descriptors that are in the IBM3206K0424. if a descriptor block is enqueued, it is compared to these registers. if it falls within this range, only the descriptor address is placed on the queue. when the descriptor is to be loaded into the dma registers, and it falls within this range, it will not be taken from the queue but loaded directly from the descriptor address. these registers are 4k aligned. the upper bound register contains the address of the last 4k block in the local descriptor address range. 3.18: dmaqs event queue number register this register specifies which dmaqs queue should be used when dma descriptors are enqueued from csked (dma on transmit comp). this register also indicates the rxque event queue to which events should be enqueued for each dmaqs queue register. length lower bound upper bound 64 bits 32 bits type read/write address lower bound x xxx 0798 upper bound x xxx 07a4 power on value lower bound x ? 0000000000000000 ? upper bound x ? 00000000 ? restrictions can be written in diagnostic mode only. upper bound is 32 bits. the upper 32 bits are internally generated, and are not different from the upper 32 bits of the lower bound reg- ister. the last four addresses in this range are reserved, and should not be used to hold descriptors. length 20 bits type read/write address xxxx 07cc power on value x ? 00002210 ? restrictions can be written in diagnostic mode only. invalid values (that is, 3), force queue number 2.
IBM3206K0424 ibm processor for network resources preliminary dma queues (dmaqs) page 174 of 676 pnr25.chapt04.01 august 14, 2000 3.19: dmaqs dma request size register this register specifies the maximum request size for dma descriptor scheduling. this is the amount of data that dmaqs will request gpdma to move in a single request. for example, if a descriptor wants to move 2k of data and the request size is set to 512 bytes, then dmaqs will request 512 bytes to be moved and then rearbitrate the dma queues. a value of ? 0 ? is the same as 0xffff. 3.20: dmaqs enq fifo register this register is for diagnostic use only. it holds dma descriptor waiting to be placed on a dma queue. read- ing this register is destructive. the oldest entry is read on each read. if it is desired to re-dispatch the dequeued entries, they will have to be re-enqueued. dma descriptors which reside in system storage are not immediately copied into the queue, but space is reserved in the queue for the descriptors, and a descriptor is built which will copy the descriptor into the queue when needed. length 16 bits type read/write address xxxx 07c0 power on value x ? 00000000 ? restrictions none length 64 bits type read only address xxxx 07f8 power on value x ? 0000000000000000 ? restrictions can not be written.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 general purpose dma (gpdma) page 175 of 676 entity 4: general purpose dma (gpdma) this entity provides dma control between system memory and IBM3206K0424 packet memory. dma transfers must be enabled in the gpdma control registers for transmit and/or receive. there are two ways to initiate dma transfers. the first is by directly writing the source address, destination address, and transfer count and flag registers. the second is by using dma descriptors and enqueueing them using dmaqs. these two methods should not be used simultaneously. if using descriptors, refer to the dmaqs section beginning on dma queues (dmaqs) on page 154 for more information. dma transfers to system i/o space are not allowed. 4.1: gpdma interrupt status this register indicates the source(s) of the interrupt(s) pending, or is used as a status register when the bits are enabled. see note on set/clear type registers on page 93 for more details on addressing. length 9 bits type read/write address xxxx 0108 and 0c power on reset value x ? 000 ? restrictions none dma transaction timeout dma command error reserved reserved zero length dma request from dmaqs error occurred during receive transfer error occurred during transmit transfer receive transfer complete transmit transfer complete 876543210 bit(s) function description 8 dma transaction timeout the dma transaction timeout specified in the gpdma interrupt enable timed out. 7 dma command error an invalid transfer was described by the value loaded into the transfer count and flag regis- ter. 6 reserved reserved 5 reserved reserved 4 zero length dma request from dmaqs dmaqs has requested a dma with a length of zero. this bit is for information use only. this bit is not an error that will prevent gpdma from processing additional dma requests.
IBM3206K0424 ibm processor for network resources preliminary general purpose dma (gpdma) page 176 of 676 pnr25.chapt04.01 august 14, 2000 4.2: gpdma interrupt enable this register serves as a mask for gpdma interrupt status. see gpdma interrupt status on page 175 for the bitwise description that the corresponding bit in this register will mask. see note on set/clear type registers on page 93 for more details on addressing. 3 error occurred during receive transfer hardware errors occurred during the last transfer. the transfer stopped after detecting the error. 2 error occurred during transmit transfer hardware errors occurred during the last transfer. the transfer stopped after detecting the error. 1 receive transfer complete the receive transfer is complete. 0 transmit transfer complete the transmit transfer is complete. length 9 bits type read/write address xxxx 0110 and 14 power on reset value x ? 9c ? restrictions none bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 general purpose dma (gpdma) page 177 of 676 4.3: gpdma control register used to set options for dma operations. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write address xxxx 0118 and 1c power on value x ? 008800c7 ? restrictions none assume 64 assume 32 assume 64 assume 32 assume 64 assume 32 assume 64 assume 32 pci transfer threshold memory transfer threshold dma transaction timeout word swap mode disable access to internal array enable limiting dma burst to cache line size pci target cache line size data transfer break type enable receive dmas enable transmit dmas 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 assume 64 assume 64-bit pci interface for descriptor transfers 30 assume 32 assume 32-bit pci interface for descriptor transfers 29 assume 64 assume 64-bit pci interface for queue 2 transfers 28 assume 32 assume 32-bit pci interface for queue 2 transfers 27 assume 64 assume 64-bit pci interface for queue 1 transfers 26 assume 32 assume 32-bit pci interface for queue 1 transfers 25 assume 64 assume 64-bit pci interface for queue 0 transfers 24 assume 32 assume 32-bit pci interface for queue 0 transfers 2 23-20 pci transfer threshold the value of these bits multiplied by eight determines the number of bytes that must be ready to transfer before a dma transfer is initiated on the pci bus. this can be used to tune the performance of the pci bus. if the number of bytes left to transfer is less than the threshold, the transfer will start when all remaining bytes are ready to be transferred. 19-16 memory transfer threshold the value of these bits multiplied by eight determine the number of bytes that must be ready to transfer before a transfer is initiated on the internal memory bus. this can be used to tune the performance of the memory subsystem. 15-9 dma transaction timeout these bits hold a value that is used to count the number of cycles that an unacknowl- edged dma cycle is in progress. if the count is reached, due to an internal chip hang condition, the dma is terminated. a value of ? 0 ? disables this function.
IBM3206K0424 ibm processor for network resources preliminary general purpose dma (gpdma) page 178 of 676 pnr25.chapt04.01 august 14, 2000 4.4: gpdma source address register used to set and keep track of the source address during a dma transfer. this is the system address that increments during a dma transfer. a bit in the transfer count and flag register determines if the source address is internal to the IBM3206K0424 or is a system address. 8-7 word swap mode this field controls word swapping for data being transferred to pcint. the word swap- ping is done as part of endian alignment. the bits are defined as follows: 00 no swap: the 32-bit words being transferred will not be swapped by pcint 01 swap: the 32-bit words being transferred will always be swapped by pcint 10 endian swap: the words will be swapped if byte swapping is being done. 11 anti-endian swap: the words will be swapped if byte swapping is not being done. 6 disable access to internal array when this bit is set, the internal array cannot be read or written. this can be used to ensure that the array is not inadvertently read or written while dmas are in progress, causing unpredictable results. 5 enable limiting dma burst to cache line size this bit on causes a dma burst to terminate upon crossing a cache line boundary of the pci target. 4-3 pci target cache line size this field indicates the cache line size if aligning dmas to the cache line size of the pci target (see bit 5). 00 32 bytes 01 64 bytes 10 128 bytes 11 256 bytes 2 data transfer break type this bit on causes a re-arbitrate request from pci to "immediately" stop moving data and resurface a new request to move the remainder of the data. when reset, gpdma stops data movement at the next cache line boundary. 1 enable receive dmas this bit on enables dma transfers out of the IBM3206K0424. 0 enable transmit dmas this bit on enables dma transfers into the IBM3206K0424. length 64 bits type read/write address xxxx 0128 power on value x ? 0000000000000000 ? restrictions none bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 general purpose dma (gpdma) page 179 of 676 4.5: gpdma destination address register used to set and keep track of the destination address during a dma transfer. this is the destination address that increments during a dma transfer. a bit in the transfer count and flag register determines if the desti- nation address is internal to the IBM3206K0424 or is a system address. 4.6: gpdma transfer count and flag register specifies the type and number of bytes transferred during a dma transfer. the lower 16 bits are a counter of the number of bytes transferred during a dma transfer. it is a count down counter; when zero is reached, the transfer ends. writing a non-zero value to the lower 16 bits starts the dma transfer. the upper 16 bits specify the type of transfer as follows. length 64 bits type read/write address xxxx 0130 power on value x ? 0000000000000000 ? restrictions none length 32 bits type read/write address xxxx 0138 power on value x ? 000000 ? restrictions none reserved reserved reserved little endian mode reserved hold mode reserved assume 64 assume 32 register/memory destination address system/IBM3206K0424 destination address data/address source address reserved register/memory source address system/IBM3206K0424 source address byte transfer count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-30 reserved these bits must be ? 0 ? . 29 reserved 28 reserved
IBM3206K0424 ibm processor for network resources preliminary general purpose dma (gpdma) page 180 of 676 pnr25.chapt04.01 august 14, 2000 27 little endian mode when this bit is written to ? 0 ? , this dma channel operates in big endian mode. when ? 1 ? , it operates in little endian mode. when in little endian mode, both the source and destina- tion must be aligned on four-byte boundaries. 26 reserved reserved. 25 hold mode when set, bits 28-29 are redefined to allow the source or destination address to be held instead of incremented. bit 29 becomes the hold destination address and bit 28 becomes the hold source address. the address being held must be a register address. when hold- ing, the maximum length is 240 bytes. 24 reserved reserved. 23 assume 64 assume the pci interface is 64-bits wide. 22 assume 32 assume the pci interface is 32-bits wide. 21 register/memory destination address if this bit is set, the destination address is a register address. if this bit is not set, the des- tination address is a memory address. if the destination address is a system address, this bit should cleared. i/o dma cycles on the pci bus are not implemented. 20 system/IBM3206K0424 destination address if this bit is set, the destination address is a pci bus address. if this bit is not set, the des- tination address is internal to the chip. 19 data/address source address if this bit is set, the source address register contains the source data. if this bit is not set, the source address register contains the source address. 18 reserved reserved. 17 register/memory source address if this bit is set, the source address is a register address. if this bit is not set, the source address is a memory address. if the source address is a system address, this bit should cleared. i/o dma cycles on the pci bus are not implemented. 16 system/IBM3206K0424 source address if this bit is set, the source address is a pci bus address. if this bit is not set, the source address is internal to the chip. 15-0 byte transfer count these bits indicate the number of bytes to transfer. a non-zero value in this field starts the dma transfer. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 general purpose dma (gpdma) page 181 of 676 4.7: gpdma dma max burst time used to limit the number of cycles a master can burst on the pci bus. when a dma burst is started, a counter is loaded with the value in this register. when the counter expires and the current access completes, the pci bus is released for use by another bus master. writing a non-zero value to this register enables this function. 4.8: gpdma maximum memory transfer count used to limit the size of data requests to the control/packet memories. this register defines the maximum number of bytes to be transferred in a single storage request to IBM3206K0424 storage. 4.9: gpdma checksum register this register contains the accumulated checksum value. it can also be used to initialize the checksum with a seed value. the most significant bit contains the alignment state (1 = odd, 0 = even alignment). this register can be read at four different addresses. the base address returns the unmodified accumulated checksum. the base address +4 returns the inverted accumulated checksum. the base address + 8 returns the byte-swapped accumulated checksum. the base address + 12 returns the inverted byte-swapped accumu- lated checksum. length 24 bits type read/write address xxxx 0158 power on value x ? 000 ? restrictions none length 7 bits type read/write address xxxx 0150 power on value x ? 40 ? restrictions none length 17 bits type read/write address xxxx 0160 power on value x ? 00000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary general purpose dma (gpdma) page 182 of 676 pnr25.chapt04.01 august 14, 2000 4.10: gpdma read dma byte count this register counts the bytes transferred into the IBM3206K0424 by the dma controller. descriptor bytes can optionally be included. (see the gpdma control register on page 177 for details.) 4.11: gpdma write dma byte count this register counts the bytes transferred out of the IBM3206K0424 by the dma controller. 4.12: gpdma array read address this register is used to read the gpdma internal array. the internal array is used to hold data for the dma. the array is organized as 64 32-bit words. the gpdma array read address is written with the address of the word that is to be read. the gpdma array data register is read to obtain the contents of the addressed word. the gpdma array read address is incremented each time the gpdma array data register is read, causing repeated reads of the gpdma array data register to obtain sequential words from the array. length 32 bits type read/write address xxxx 0178 power on value x ? 00000000 ? restrictions none length 32 bits type read/write address xxxx 017c power on value x ? 00000000 ? restrictions none length 8 bits type read/write address xxxx 0140 power on value x ? 00 ? restrictions this address space is for diagnostic use only. it should not be read or written during normal operation. the low order two bits of gpdma array read address are place holders and are ignored. they should be set to ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 general purpose dma (gpdma) page 183 of 676 4.13: gpdma array write address this register is used to write the gpdma internal array. the internal array is used to hold data for the dma. the array is organized as 64 32-bit words. the gpdma array write address is written with the address of the word that is to be written. the gpdma array data register is written to write the addressed word. the gpdma array write address is incremented each time the gpdma array data register is written, causing repeated writes of the gpdma array data register to write sequential words in the array. 4.14: gpdma array reads the contents of the internal array. the internal array is used to hold data for the dma. length 8 bits type read/write address xxxx 0144 power on value x ? 00 ? restrictions this address space is for diagnostic use only. it should not be read or written during normal operation. the low order two bits of gpdma array read address are place holders and are ignored. they should be set to ? 0 ? . length 64 words x 32 bits type read/write address xxxx 0148 power on value x ? 00000000 ? restrictions this address space is for diagnostic use only. it should not be read or written during normal operation. the array is read/written at the location indicated by the gpdma array read address or gpdma array write address.
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 184 of 676 pnr25.chapt04.01 august 14, 2000 memory controlling entities entity 5: the dram controllers (comet/pakit) this section describes the function of the comet/pakit entities. comet is the memory controller for con- trol memory, and pakit is the memory controller for packet memory. each controller can support the following types of memory: synchronous drams running at 133mhz (7.5 ns cycle time) with a cas latency of two or three and a burst length of one or two. memory sizes of 4mb, 8mb, 16mb, and 32mb are supported. please note that the cycle time of the sdram clock is a constant on the IBM3206K0424. any sdram part selected must be capable of running at 133mhz or faster at cas latency 2 or 3. synchronous sram running at 133mhz (7.5 ns cycle time) with a read latency of two and a write latency of zero or two. memory sizes of 1mb, 2mb, 4mb, and 8mb are supported. note: for any memory configuration, modules must be selected such that the loading on any memory net (including card wiring) does not exceed 120pf. the number of column address lines is programmable, allowing both drams with symmetric address (same number of row and column address lines) and asymmetric address (typically having more row than column address lines). if using sdram, the memory may be operated as having one or two arrays. the arrays are differentiated by their chip selects. if the memory is configured to have two arrays, the memory's address range is split equally between the two arrays. memory checking can be enabled/disabled, and the method of checking selected can be either ecc or parity. if ecc is selected, seven data bits are used for ecc over the 32 data bits. if parity is selected, four data bits are used to provide parity over the 32 data bits. comet/pakit are designed so that memory contents are preserved over a reset. if the IBM3206K0424 is reset while a memory write cycle is in progress, the cycle is completed in an orderly fashion to ensure that valid ecc/parity is written. memory timings are not violated when reset goes active. refresh is maintained during the reset.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 185 of 676 memory reset sequence after a reset, onboard rom or external firmware must properly configure the control registers for comet/pakit. if using sram, the reset sequence is complete. if using sdram, bit 3 of the memory controller ? s sdram command and status register must be written to a ? 1 ? to initiate forcing the sdrams out of the self refresh state and performing the por sequence. when bits five and four of this register are '00', the sdrams are ready for use. note: memory configuration errors occur if an attempt is made to use memory that is configured incorrectly or, if an attempt is made to use sdram before the por sequence is completed. accesses to the first 0x20 bytes of memory (control or packet) are not allowed unless bit 26 of the corre- sponding memory control register is set. with this restriction in place, accesses with zero-valued pointers will cause the zero address error bit in the memory controller's status register to be set.
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 186 of 676 pnr25.chapt04.01 august 14, 2000 5.1: comet/pakit control register this register contains the information that controls the functions of the entity. see note on set/clear type registers on page 93 for more details on addressing. before this register can be altered, writing it must be enabled in comet/pakit memory controller write e nable register (described on page 197). length 32 bits type read/write comet address xxxx 0900 and 04 pakit address xxxx 0980 and 84 power on value x ? 00000000 ? restrictions none disable controller waiting for t ras being met on auto precharge reserved 4/2 bank sdram device reserved encode sram chip selects disable zero address error detection state information selection disable driving memory data nets when idle sdram split ecc sdram burst length of 2 drive sram output enables freeze dram error registers latch error registers on single bit errors enable ecc or parity sram byte enables for writes only disable sdram overlapped parity or ecc reserved sram or sdram latency memory type memory unpopulated sdram column address size/sram module width memory size number of dram arrays 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 disable controller waiting for t ras being met on auto pre- charge some sdram modules don ? t allow sending a read or write with auto precharge to them unless t ras has been met. if using esdram (any sdram at burst length of two, or a part that allows sending an auto precharge before t ras has been met), this bit should be set. this bit has no meaning for sram. 30 reserved reserved 29 4/2 bank sdram device when this bit is ? 1 ? , the sdrams attached are four-bank devices. when a ? 0 ? , the sdrams are two-bank devices. a ? 0 ? setting works for either type device, but four-bank devices provide slightly better performance if this bit is set to ? 1 ? . 28 reserved reserved 27 encode sram chip selects when using sram, this bit set to a ? 0 ? causes the chip select outputs to be direct chip selects. set to ? 1 ? , chip selects 2-0 carry an encoded value for one of eight chip selects. chip select three indicates when chip selects 2-0 are valid.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 187 of 676 26 disable zero address error detection. when set to ? 1 ? , this bit disables the detection of zero address errors to memory. 25-24 state information selection. these bits control what will be visible on the enstate outputs if comet/pakit are selected for observation on the enstate pins. 23 disable driving memory data nets when idle when set to ? 1 ? , this bit disables the memory controller from driving the memory data nets to ? 0 ? when the controller is idle. 22 sdram split ecc when set to ? 1 ? , this bit indicates that the ecc/parity for multiple arrays of memory are in separate modules and a slight increase in performance is possible. if this bit is ? 0 ? , the ecc/parity is in a shared module. if using neither ecc or parity, this bit should be set to ? 1 ? for a slight performance increase. this bit applies only when sdram is being used. 21 sdram burst length of 2 when set to ? 1 ? , this bit indicates that the sdram should be driven assuming a burst length of two. this bit set to ? 0 ? indicates a burst length of one. 20 drive sram output enables when set to ? 1 ? , this bit allows functional output enables to be driven for srams. when set to ? 0 ? , the output enables are driven active continuously. 19 freeze error registers when set to ? 1 ? , this bit freezes the memory address register and the syndrome regis- ter when a memory error occurs. when this bit is set to ? 0 ? , the error registers are updated whenever an error is encountered. for this bit to have any meaning with single bit errors, bit 18 must also be a ? 1 ? . 18 latch error registers on single bit errors when set to ? 1 ? , this bit allows error data to be latched into the memory error address register and the syndrome register when a single bit errors occurs. when this bit is set to ? 0 ? , single bits errors do not latch data into the error registers. 17 enable ecc or parity this bit set to ? 1 ? enables ecc detection/correction or parity error detection. 16 sram byte enables for writes only when set to ? 1 ? , this bit' causes byte enables to only be driven on writes to sram. the enables are driven inactive for reads. if the bit is set to ? 0 ? , the byte enables are valid on both reads and writes. 15 disable sdram overlapped bank accesses/shorten sram write duration when the memory controller is configured for sdram, setting this bit to ? 1 ? disables the overlapping of bank accesses. when configured for sram, setting this bit to ? 1 ? short- ens the time the IBM3206K0424 drives data on writes. 14 parity or ecc when set to ? 1 ? , this bit causes parity to be generated. this bit set to ? 0 ? causes ecc to be generated. ecc is supported for dram only. 13-12 reserved reserved 11-10 sram or sdram latency these bits indicate the delay between performing a read and the memory returning data. the bits are encoded as follows: 00 1 cycle (sram only) 01 2 cycles 10 3 cycles (sdram only) 11 reserved 9-8 memory type these bits indicate the type of memory being used for memory. the bits are encoded as follows: 00 sram 01 zbt sram 10 synchronous dram (sdram) 11 enhanced synchronous dram (esdram) 7 memory unpopulated. if this bit is ? 1 ? , there is no physical memory connected to this controller. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 188 of 676 pnr25.chapt04.01 august 14, 2000 6-4 sdram column address size/sram module width these bits indicate the number of column address lines. the bits are encoded for sdram as follows: ? 000 ? 8 column address lines (256 words/row) ? 001 ? 9 column address lines (512 words/row) ? 010 ? 10 column address lines (1k words/row) ? 011 ? reserved ? 1xx ? reserved the bits are encoded for sram as follows: ? 000 ? 18-bit wide 4 mb sram ? 001 ? 18-bit wide 8 mb sram ? 010 ? 18-bit wide 16 mb sram ? 011 ? 18-bit wide 32 mb sram ? 100 ? 36-bit wide 4 mb sram ? 101 ? 36-bit wide 8 mb sram ? 110 ? 36-bit wide 16 mb sram ? 111 ? 36-bit wide 32 mb sram 3-1 memory size these bits indicate the total amount of memory present, that is, two 64mb sdram arrays would result in a value of 128mb in these bits. the bits are encoded as follows: ? 000 ? 1 mb ? 001 ? 2 mb ? 010 ? 4 mb ? 011 ? 8 mb ? 100 ? 16 mb ? 101 ? 32 mb ? 110 ? 64 mb ? 111 ? 128 mb - sdram only 0 number of dram arrays. this two bit indicates the number of arrays of dram present. this bit set to ? 0 ? indicates one array; the bit set to ? 1 ? indicates two arrays. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 189 of 676 5.2: comet/pakit status register this register contains status information for comet/pakit. see note on set/clear type registers on page 93 for more details on addressing. length 6 bits type read/write comet address xxxx 0908 and 0c pakit address xxxx 0988 and 8c power on value x ? 00000000 ? restrictions reserved zero address error memory configuration error uncorrectable error detected single bit error memory address out of range error reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-6 reserved reserved 5 zero address error this bit is set if comet/pakit is presented an address of zero. 4 memory configuration error this bit is set if comet/pakit is configured in an invalid combination. 3 uncorrectable error detected this bit is set if an uncorrectable error is detected. 2 single bit error this bit is set if a single bit ecc error is detected. 1 memory address out of range error this bit is set if the address presented to the memory controller is out of the defined range. 0 reserved reserved
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 190 of 676 pnr25.chapt04.01 august 14, 2000 5.3: comet/pakit interrupt enable register this register contains bits corresponding to the bits in the comet/pakit status register. if a bit in this reg- ister is set and the corresponding bit is set in the comet/ pakit status register, an interrupt is generated. see note on set/clear type registers on page 93 for more details on addressing. 5.4: comet/pakit lock enable register this register contains bits corresponding to the bits in the comet/pakit status register. if a bit in this reg- ister is set and the corresponding bit is set in the comet/ pakit status register, a signal is sent to vimem indicating that memory should be locked. see note on set/clear type registers on page 93 for more details on addressing. length 6 bits type read/write comet address xxxx 0910 and 14 pakit address xxxx 0990 and 94 power on value x ? 0000003a ? restrictions length 6 bits type read/write comet address xxxx 0918 and 1c pakit address xxxx 0998 and 9c power on value x ? 0000003a ? restrictions
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 191 of 676 5.5: comet/pakit memory error address register this register holds the address at which the last memory error occurred. length 32 bits type read only comet address xxxx 0920 pakit address xxxx 09a0 power on value x ? 00000000 ? restrictions reserved error address 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-27 reserved reserved. 26-0 error address. the read address of the last memory error.
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 192 of 676 pnr25.chapt04.01 august 14, 2000 5.6: comet/pakit sdram command and status register this register is used to issue various commands to and control the timing operation of synchronous drams when they are attached to the IBM3206K0424. if the IBM3206K0424 is not configured for sdrams, any writes to bits 3-0 of this register are ignored. this register is also used to reflect the status of the synchronous drams. when a command bit in this register is set (bits 3-0 only), the command executes and resets the bit upon completion. only one bit (3-0 only) may be set during any write. software should poll this register to make sure the previous command has completed before issuing another write to this register. if more than one bit at a time is written to this register (3-0 only), the results may be unpredictable. length 32 bits type read/write comet address xxxx 0924 pakit address xxxx 09a4 restrictions power on value: x ? 00003030 ? reserved t dpl delay t ras delay t rp delay t rc delay reserved por self refresh initialize sdrams start power on reset sequence enter the self refresh state exit the self refresh state 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-24 reserved reserved. 23-20 t dpl delay the value of these four bits determine the number of cycles after writing data before a precharge command may be issued. to determine the value needed in these bits, take the t dpl3 (for cas latency 3) or t dpl2 (for cas latency 2) parameter from the specification of the sdram of the part to be used, divide by 7.5 ns, and round up if necessary. suggested values are: x ? 2 ? 6.8 ns sdram x ? 1 ? 6 ns esdram x ? 1 ? 7.5 ns esdram 19-16 t ras delay the value of these four bits determine the number of cycles a bank must be active. to determine the value needed in these bits, take the t ras parameter from the specifica- tion of the sdram of the part to be used, divide by 7.5 ns, and round up if necessary. suggested values are: x ? 7 ? 6.8 ns sdram x ? 3 ? 6 ns esdram x ? 3 ? 7.5 ns esdram
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 193 of 676 15-12 t rp delay the value of these four bits determines the number of cycles after a bank precharge starts before the bank may be accessed again. to determine the value needed in these bits, take the t rp parameter from the specification of the sdram of the part to be used, divide by 7.5 ns, and round up if necessary. if tdpl is 2, trp may need to be increased by one to insure correct operation. suggested values are: x ? 4 ? 6.8 ns sdram x ? 2 ? 6 ns esdram x ? 2 ? 7.5 ns esdram 11-8 t rc delay the value of these four bits determine the bank cycle time. to determine the value needed in these bits, take the t rc parameter from the specification of the sdram of the part to be used, divide by 7.5 ns, and round up if necessary. suggested values are: x ? a ? 6.8 ns sdram x ? 5 ? 6 ns esdram x ? 5 ? 7.5 ns esdram 7-6 reserved reserved 5por when set to ? 1 ? , this bit indicates the por sequence has not been performed on the sdrams. this bit automatically resets to ? 0 ? when the por sequence has been per- formed. 4self refresh this bit reads ? 1 ? when the sdrams are in the self refresh state. this bit reads ? 0 ? when the sdrams are not in the self refresh state. this bit is ? 1 ? after a por or reset. the exit self refresh operation must be performed before the por sequence is initi- ated. 3 initialize sdrams this bit effectively encapsulates the functions provided by bits 2 and 0. setting this bit to ? 1 ? causes the memory controller to take the sdrams out of self refresh and per- form the por sequence on them. this bit clears itself. when the initialization is com- plete, bits 4 and 5 should be a ? 0 ? . 2 start power on reset sequence when set to ? 1 ? , this bit causes the dram controller to initiate the sdram power on sequence. this includes an all-banks precharge, following by a command register write that sets the cas latency to 3, the wrap type to sequential, and the burst length to 1, followed by two refresh cycles. after this sequence is initiated and completed, bit 5 resets and the sdrams are ready for normal use. 1 enter the self refresh state when set to ? 1 ? , this bit causes the sdram controller to signal the sdrams to go into the self refresh state. all memory activity is suspended. once the sdrams have entered the self refresh state, bit 4 will set. this bit will clear itself. 0 exit the self refresh state when set to ? 1 ? , this bit causes the sdram controller to signal the sdrams to exit the self refresh state. once the sdrams have exited the self refresh state, bit 4 will clear. this bit will clear itself. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 194 of 676 pnr25.chapt04.01 august 14, 2000 5.7: comet/pakit dram refresh rate register this register holds the value of a counter used to control the rate of refresh for the dram. length 32 bits type read/write comet address xxxx 0928 pakit address xxxx 09a8 power on value x ? 00000820 ? restrictions none reserved refresh rate 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-12 reserved reserved 11-0 refresh rate the value of these bits multiplied by 7.5 ns gives the refresh rate. the por value of x ? 820 ? yields a refresh rate of 15.6 ms.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 195 of 676 5.8: comet/pakit syndrome register this register holds the syndrome bits that can be used to isolate the data or check bit in error when ecc is used. when parity is used, this register indicates which of the four bytes of the memory bus had a parity error. length 32 bits type read/write comet address xxxx 092c pakit address xxxx 09ac power on value x ? 00000000 ? restrictions none reserved syndrome bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-7 reserved reserved 6-0 syndrome bits when using ecc, a single bit error can be identified by matching the contents of this regis- ter to the corresponding bit in the table below. when using parity, only bits 3-0 are valid and are interpreted as follows: 0000 no parity error 0001 parity error on bits 7-0 0010 parity error on bits 15-8 0100 parity error on bits 23-16 1000 parity error on bits 31-24 other reserved
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 196 of 676 pnr25.chapt04.01 august 14, 2000 ecc syndrome bits bit in error syndromes bit in error syndromes ecc(6) ? 1000000 ? ecc(5) ? 0100000 ? ecc(4) ? 0010000 ? ecc(3) ? 0001000 ? ecc(2) ? 0000100 ? ecc(1) ? 0000010 ? ecc(0) ? 0000001 ? n/a n/a data(31) ? 0111000 ? data(30) ? 0110100 ? data(29) ? 0110010 ? data(28) ? 0101100 ? data(27) ? 1110000 ? data(26) ? 1101000 ? data(25) ? 1100100 ? data(24) ? 1100010 ? data(23) ? 0100101 ? data(22) ? 0010101 ? data(21) ? 0001101 ? data(20) ? 1100001 ? data(19) ? 0110001 ? data(18) ? 0101001 ? data(17) ? 0011001 ? data(16) ? 1000101 ? data(15) ? 1010001 ? data(14) ? 1001100 ? data(13) ? 1001010 ? data(12) ? 1000110 ? data(11) ? 1000011 ? data(10) ? 1011000 ? data(09) ? 1010100 ? data(08) ? 1010010 ? data(07) ? 0100011 ? data(06) ? 0010011 ? data(05) ? 0001011 ? data(04) ? 0000111 ? data(03) ? 0011010 ? data(02) ? 0100110 ? data(01) ? 0010110 ? data(00) ? 0001110 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 197 of 676 5.9: comet/pakit checkbit inversion register this register can be used for diagnostic purposes to invert the ecc/parity check bits that are written to mem- ory. 5.10: comet/pakit memory controller write enable register this register must be written to a specific pattern before the memory control register can be written. length 32 bits type read/write comet address xxxx 0930 pakit address xxxx 09b0 power on value x ? 00000000 ? restrictions none reserved invert check bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-7 reserved reserved 6-0 invert check bits setting any of these bits inverts the corresponding check bit that is written to memory. only bits 3-0 are valid when parity is used as a checking mechanism. length 32 bits type read/write comet address xxxx 0934 pakit address xxxx 09b4 power on value x ? 000000b4 ? restrictions none reserved lock bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-8 reserved reserved 7-0 lock bits this register must be written to a x ? 4 ? before the memory control register can be written. this register will por to x ? 4 ? , but crisco code sets up the memory controller and clears this register back to x ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary the dram controllers (comet/pakit) page 198 of 676 pnr25.chapt04.01 august 14, 2000 5.11: comet/pakit memory configuration error sense register this register can be read to help determine the source of a memory configuration error. the bits in this regis- ter reset automatically once the configuration error is resolved. length 32 bits type read only comet address xxxx 0938 pakit address xxxx 09b8 power on value x ? 00000000 ? restrictions none reserved sdram not properly initialized sdram not properly initialized sdram not properly initialized sdram bad latency sram invalid amount of sram with ecc enabled sram bad latency 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-7 reserved reserved 6 sdram not properly initialized an sdram access has been attempted without the sdrams being taken out of self refresh and/or the por sequence being performed. 5 sdram not properly initialized bits 6-4 of the control register have an invalid value. 4 sdram not properly initialized bits 3-2 of the control register indicate less than 4m of memory. 3 sdram bad latency bits 11-10 of the control register indicate a latency of one or a reserved value.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the dram controllers (comet/pakit) page 199 of 676 2 sram invalid amount of memory bits 27, 13-12 and 3-1 of the control register indicate an invalid sram memory size. acceptable sizes are: 4mbit x18 unmuxed chip selects of sizes 1m, 2m, 4m. 8mbit x18 unmuxed chip selects of sizes 2m, 4m, 8m. 16mbit x18 unmuxed chip selects of sizes 4m, 8m, 16m. 32mbit x18 unmuxed chip selects of sizes 8m, 16m, 32m. 4mbit x18 muxed chip selects of sizes 2m, 4m, 8m. 8mbit x18 muxed chip selects of sizes 4m, 8m, 16m. 16mbit x18 muxed chip selects of sizes 4m, 16m, 32m. 32mbit x18 muxed chip selects of sizes 8m, 32m, 64m. 4mbit x36 unmuxed chip selects of sizes 1m, 2m. 8mbit x36 unmuxed chip selects of sizes 1m, 2m, 4m. 16mbit x36 unmuxed chip selects of sizes 2m, 4m, 8m. 32mbit x36 unmuxed chip selects of sizes 4m, 8m, 16m. 4mbit x36 muxed chip selects of sizes 1m, 2m, 4m. 8mbit x36 muxed chip selects of sizes 2m, 4m, 8m. 4mbit x36 muxed chip selects of sizes 4m, 8m, 16m. 8mbit x36 muxed chip selects of sizes 8m, 16m, 32m. 1 sram with ecc enabled bits 17, 14, and 9-8 of the control register indicate ecc is enabled with an sram configu- ration. this is invalid. 0 sram bad latency bits 11-10 of the control register indicate a latency of three or a reserved value. bit(s) function description
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 200 of 676 pnr25.chapt04.01 august 14, 2000 entity 6: atm virtual memory logic (vimem) this entity is responsible for adjustment of all addresses provided to the memory control entities. all addresses can be categorized into three distinct types, based entirely upon the location of the requested address with respect to the three base registers defined in this entity. the three types of addresses are referred to as control, real packet, and virtual packet addresses. all memory requests arriving on the control memory bus are handled as control memory accesses, and sim- ply have the contents of the control memory base register subtracted from them before being passed on to the control memory entity. when the processor accesses memory, the cache controller compares the requested address to the real packet memory base register and if the address is less than the base regis- ter, the request is routed to the control memory bus; otherwise it is routed to the packet memory bus. all requests arriving on the packet memory bus are compared to the virtual memory base address register. if the address of the request is less than the base register, the contents of the real packet memory base reg- ister are subtracted from the address and this address is passed on to the packet memory control entity. if the requested address is greater than or equal to the base register, a more complex, but flexible scheme is used to determine the real address to provide to the packet memory control entity. for a detailed explanation of the virtual address generation scheme refer to virtual memory overview on page 248 and the accompany- ing figures. 6.1: vimem virtual memory base address this register defines the starting address of the virtual address space used to manage incoming and outgoing frames. any time an access is made to virtual memory that falls within the defined bounds of virtual memory, the contents of this register are subtracted from the virtual address to derive the true offset into virtual mem- ory. this true offset, along with the known length of all virtual buffers, allows the index of the specific virtual buffer to be derived by the virtual memory access hardware. this index can then be used to access the real buffer map associated with this virtual buffer. length 32 bits type read/write address xxxx 0d10 power on value x ? 0040 0000 ? restrictions the start of virtual address space must begin on a 128kb boundary. for this rea- son, the lowest 17 bits of this register are forced to ? 0 ? and are not implemented. writes of any value to the low 17 bits of this register are ignored, and a read always returns ? 0 ? for the low 17 bits. base address of virtual memory 128kb boundary restriction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 these bits contain the upper 15 bits of the base address of virtual memory. 16-0 these bits are forced to ? 0 ? because the virtual memory base address must start on a 128k byte boundary.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 201 of 676 6.2: on-chip memory base address this register is used by various entities to generate the base address of the on-chip memory (ocm). 6.3: vimem control memory base address this register defines the starting address of the control memory address space. any time an access is made to control memory, the contents of this register are subtracted from the address before an access to memory occurs. length 17 bits type read/write address xxxx 0d9c power on value x ? 0010 0000 ? restrictions the start of virtual address space must begin on a 128kb boundary. for this rea- son, the lowest 17 bits of this register are forced to ? 0 ? and are not implemented. writes of any value to the low 17 bits of this register are ignored, and a read always returns ? 0 ? for the low 17 bits. length 32 bits type read/write address xxxx 0d14 power on value x ? 0000 0000 ? restrictions the start of real control address space must begin on a 128kb boundary. for this reason, the lowest 17 bits of this register are forced to ? 0 ? and are not implemented. writes of any value to the low 17 bits of this register are ignored, and a read always returns ? 0 ? for the low 17 bits. base address of real control memory 128kb boundary restriction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 these bits contain the upper 15 bits of the base address of real control memory. 16-0 these bits are forced to ? 0 ? because the real control memory base address must start on a 128kb boundary.
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 202 of 676 pnr25.chapt04.01 august 14, 2000 6.4: vimem packet memory base address this register defines the starting address of the packet memory address space. any time an access is made to packet memory, the contents of this register are subtracted from the address before an access to memory occurs. length 32 bits type read/write address xxxx 0d18 power on value x ? 0020 0000 ? restrictions the start of real packet address space must begin on a 128kb boundary. for this reason, the lowest 17 bits of this register are forced to ? 0 ? and are not implemented. writes of any value to the low 17 bits of this register are ignored, and a read always returns ? 0 ? for the low 17 bits. this register must also be set up before any of the real buffer base registers, or the virtual buffer map registers are written. base address of real packet memory 128kb boundary restriction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s0 description 31-17 these bits contain the upper 15 bits of the base address of real packet memory. 16-0 these bits will be forced to ? 0 ? because the real packet memory base address must start on a 128kb boundary.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 203 of 676 6.5: vimem virtual memory total bytes this register defines the total number of bytes in the address space being allocated for virtual memory. the contents of this register, divided by the configured size of virtual buffers, yields the total number of virtual buffer indices that should be used to initialize pools. the value of the indices should range from this calcu- lated value minus one, down to zero. if an address is determined to be above or equal to the virtual memory base register it is assumed to be a virtual access. if the virtual buffer index derived from the requested address indicates that the virtual buffer space being accessed is above the limit defined by this register, an error is generated. length 32 bits type read/write address xxxx 0d0c power on value x ? 0001 0000 ? restrictions the maximum value that should be set in this register is (65535 * virtual buffer size). for example, if 64-byte virtual buffers are configured, the maximum value that should be loaded into this register is x ? 3fffc0 ? . virtual memory address space not implemented 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 these bits contain the upper 26 bits of the total number of bytes of address space being reserved for virtual memory. 5-0 these bits are not implemented and are forced to ? 0 ? because the virtual memory block can only be allocated in incre- ments of the current virtual buffer size (minimum size is 64 bytes).
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 204 of 676 pnr25.chapt04.01 august 14, 2000 6.6: vimem virtual/real memory buffer size this register defines the total number of bytes to be occupied by each of the virtual or real buffers as well as the spacing from one buffer to the next. length 4 bits type read/write address xxxx 0d04 power on value x ? 2 ? restrictions care must be taken to set this register to a large enough value to contain the entire frame being sent as well as certain control information that the hardware stores in the buffer header. for example, if the maximum frame being sent or received is 1024 bytes long, then this register should be set to indicate 2048-byte frames to allow sufficient room for the buffer header information added by the hardware. virtual/real buffer size 3210 bit(s) description 3-0 these bits contain the encoded four-bit value that defines the virtual/real buffer size. the encoding is as follows: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 205 of 676 6.7: vimem packet memory offset this register contains the number that will be added by the vimem access logic to all accesses of real packet memory that occur. in a high performance configuration (separate control and packet store), this register should be written to all zeros to indicate that all accesses of real packet memory do not require any additional offset to be added. in a medium performance configuration (combined control and packet store), this register should be loaded with a value that indicates the logical partitioning between control and packet storage. if for instance, a single bank of 2 meg was configured and this register was loaded with x ? 00100000 ? (1 meg), then all accesses to real packet memory would be forced into the 1-meg to 2-meg range. 6.8: vimem maximum buffer size this register is used by the virtual memory logic to determine if an access to a virtual buffer falls into the region of the buffer that can be accessed. if a virtual buffer read or write accesses an offset in a virtual buffer that is greater than the contents of this register, the virtual memory logic can be configured to halt and gener- ate an interrupt. the power up value of all ones causes this check to be disabled. this register is intended to provide the user with a means of providing additional protection to accesses of the virtual buffers. for exam- ple, if this register is loaded with x ? ff8 ? , all memory access up to and including the byte at address x ? fff ? are allowed. any access of offset x ? 1000 ? or above will cause an exception. length 32 bits type read/write address xxxx 0d3c power on value: x ? 0000 0000 ? restrictions this register should only be loaded with a non-zero value if a medium performance configuration (combined control and packet store) exists. the value loaded must be between zero and the maximum of the total amount of memory in the single bank, and it must be on a 128kb boundary. any time the value in this register is changed, the related base registers must be reloaded because the value loaded into them is affected by the contents of this register during the load operation. the related regis- ters are the virtual buffer map base address register and all five real buffer base registers. length 17 bits type read/write address xxxx 0d34 power on value x ? 1 fff8 ? restrictions all address logic based on this register only recognizes eight-byte words in mem- ory. for this reason, the low three bits of this register are not implemented and are always forced to ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 206 of 676 pnr25.chapt04.01 august 14, 2000 6.9: vimem access control register the bits in this register control the configurable features of the virtual memory logic. see note on set/clear type registers on page 93 for more details on addressing. length 16 bits type read/write address xxxx 0d80 and 84 power on value x ? 0 ? restrictions none ignore virtual buffer map fetch required map serialize packet memory control access priority reserved 1514131211109876543210 bit(s) description 15 when set, this bit forces the virtual memory logic to ignore the virtual buffer map validity indication, and force all maps to appear valid. 14 when set, this bit forces the virtual memory logic to fetch the required map entry from storage on every new virtual access. if a virtual memory map is updated by the software for any reason, this bit should be toggled on and off after the map is updated and before any virtual access happens to ensure that the virtual memory logic is not using stale cached map seg- ments. there is no hardware provided to make sure that the map entry required by the virtual memory logic is not con- tained in one of the bcach lines. if is the responsibility of the software to ensure that all modified lines are flushed from the cache before the virtual memory logic needs them. 13 when set, this bit forces all accesses to packet memory to be serialized. 12 when set, this bit causes control accesses to always have priority over packet accesses in a single memory bank configu- ration. when reset, priority will toggle every time an access is initiated. 11-0 reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 207 of 676 6.10: vimem access status register this register contains information regarding the current status of the virtual memory logic mainly with respect to detected error access conditions. see note on set/clear type registers on page 93 for more details on addressing. length 17 bits type read/write address xxxx 0d60 and 64 power on value x ? 0000 ? restrictions none required conditions not met page fault error during read control memory access too high packed memory address invalid invalid map non-recoverable page fault error during write recoverable page fault error during write read caused a page fault access above current virtual buffer access off current virtual buffer map invalid buffer size in base register incorrect memory boundary in base register ? 0 ? detected in base register reserved generated buffer index too large invalid configured buffer size invalid value in map base register 161514131211109876543210 bit(s) description 16 when set, this bit indicates that the required conditions for the control, packet, and virtual base registers has not been sati s- fied. the required conditions are: control base < packet base < virtual base 15 when set, this bit indicates that the virtual memory logic has detected a page fault error when attempting to read memory. this indicates that no real buffer was available to map into the virtual address space when required. all virtual reads that fa il during a page fault regardless of the requesting entity will cause this bit to be set. if the corresponding bit is reset in the lock register, the read operation will complete, but with invalid data. 14 when set, this bit indicates that a control memory access was detected that was above the value contained in the packet memory offset register for single bank configurations, or in a multiple bank configuration in which the high address bits 31 - 27 were not ? 0 ? . 13 when set, this bit indicates that a packet memory access of address zero was detected in single bank mode, or that a packet address was detected that contained an address out of range (high five bits non-zero). 12 when set, this bit indicates that the virtual memory logic has detected a virtual memory operation that attempted to access a map that was not marked as valid. a virtual buffer map is marked valid by the pools entity when the buffer is originally acquired, and is marked as invalid when the buffer is freed back to pools. receiving this error indication typically means that the software is trying to use a buffer that has not been acquired through the normal means, or is trying to use a buffer that has already been freed, or that memory has been corrupted. the valid indication that is checked by the hardware is the value x ? ?656 ? in the first 16 bits of the eight-byte map entry being accessed. to determine the failing address, the memory control entity can be locked on this type of failure, and the information saved by the memory controller, along with the base registers in this entity can be used to determine which map was being accessed at the time of failure.
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 208 of 676 pnr25.chapt04.01 august 14, 2000 11 when set, this bit indicates that the virtual memory logic has detected a non-recoverable page fault error when attempting to write memory. this indicates that no real buffer was available to map into the virtual address space when required. all virtual writes that fail during a page fault, with the exception of bcach and raall operations, cause this bit to be set. 10 when set, this bit indicates that the virtual memory logic has detected a recoverable page fault error when attempting to write memory. this indicates that no real buffer was available to map into the virtual address space when required. opera- tions from bcach and raall cause this bit to be set instead of the non-recoverable bit because the software can recover from these failures. if a bcach write to virtual memory fails in this manner, the packet header of the frame being updated is updated to indicate the failure. software can check the field in the packet header to ensure that the dma operation com- pleted successfully. if such a packet is enqueued to csked, the packet header is checked and will prevent the frame from being passed on to the segmentation logic. when csked encounters a frame that has had this type of failure, there are sev- eral possible ways in which it can be configured (via the csked control register) to handle the situation. it can be configured to ignore the error and attempt to transmit the frame anyway (probably not a good way), or the buffer can be freed back to pools, or an event can be generated to allow the software to deal with the situation. if a raall write to virtual memory fails in this manner, the packet currently being received is dropped; it is up to the software to perform any recovery operations tha t are required. 9 when set, this bit indicates that the virtual memory logic has detected a read operation that caused a page fault. this is an invalid condition because the data required for a read operation should have been previously initialized by a write operation, so no page fault should ever occur on a read operation. if the corresponding bit in the lock register is reset, a page is mappe d into the current virtual buffer segment and the data that previously was written in that page is returned. this bit can come on in several situations that are not really errors. in these cases, the associated interrupt and lock bits can be reset so that t his error does not cause the adapter to halt normal operation. several of these conditions are: when predictive fill is enabled, a read from the end of a buffer may cause a predictive read that crosses a virtual segment boundary and causes this bit to be set. if a small buffer (fits entirely in the cache) is copied from one IBM3206K0424 buffer to another IBM3206K0424 buffer, a subsequent read of the last bytes written causes this bit to be set if the cache hasn ? t been flushed between the write and the read, and the last write cycle did not write all four bytes, and the address that is being written/read is within the first 0x2 0 bytes of a virtual segment. 8 when set, this bit indicates that the virtual memory logic has detected an access of a virtual buffer that falls above the limi t set by the buffer maximum size register. 7 when set, this bit indicates that the virtual memory logic has detected an access that does not fall in one of the currently mapped buffer segments based upon the currently-configured virtual buffer map size. 6 when set, this bit indicates that a virtual access has been detected that used a base register that had an invalid associated buffer size configured in the low order bits. 5 when set, this bit indicates that a virtual access has been detected that used a base register that was not on the correct memory boundary. for example, if a base register is set up to use 2k buffers, then the base register must be set up on a 2k boundary. 4 when set, this bit indicates that a virtual access has been detected that used a base register that contained a value of ? 0 ? . 3 reserved. 2 when set, this bit indicates that the virtual memory logic has detected a memory access that resulted in the generation of a buffer index that was greater than the currently configured maximum derived from the vimem virtual memory total bytes reg- ister. 1 when set, this bit indicates that the currently configured size of buffers is invalid. 0 when set, this bit indicates that the map base register contains an invalid value. two possible causes are that bits 5-2 are not ? 0 ? or bits 31-6 are ? 0 ? . bit(s) description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 209 of 676 6.11: vimem access status interrupt enable register this register allows the user to enable interrupts for each of the conditions reported in the vimem access status register. each bit corresponds to the same bit in the status register and when set to ? 1 ? generates an interrupt to the processor if the condition is detected. see note on set/clear type registers on page 93 for more details on addressing. 6.12: vimem memory lock enable register this register allows the user to selectively allow each of the conditions reported in the vimem access status register to force a memory lock condition in the memory controller. each bit corresponds to the same bit in the status register and when set to ? 1 ? causes a memory lock if the condition is detected. see note on set/clear type registers on page 93 for more details on addressing. length 17 bits type read/write address xxxx 0d68 and 6c power on value x ? 1ffff ? restrictions none length 17 bits type read/write address xxxx 0d70 and 74 power on value x ? 1ffff ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 210 of 676 pnr25.chapt04.01 august 14, 2000 6.13: vimem state machine current state this register provides feedback to the user regarding the current status of the state machines in vimem. one use of this register is to make sure that the required initialization time has expired after loading the segment size register. this is accomplished by reading this register repeatedly until the initialization state machine is in the idle state. length 32 bits type read only address xxxx 0d78 power on value x ? 1?0 ? restrictions none reserved current state of the initialization state machine reserved current state of the vimem main1 state machine reserved current state of the vimem main0 state machine 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-21 reserved 20-16 these bits contain the current state of the initialization state machine. a value of "1----" indicates that the state machine i s in the idle state. 15-13 reserved 12-8 these bits contain the current state of the vimem main1 state machine. a value of "00000" indicates that the state machine is in the idle state. 7-5 reserved 4-0 these bits contain the current state of the vimem main0 state machine. a value of "00000" indicates that the state machine is in the idle state.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 211 of 676 6.14: vimem last processor read real address this register provides information to the user about the last read access of virtual packet memory by the pro- cessor. if a virtual address was accessed, this register contains the real address generated by the virtual memory logic that can be used to access the same location. this register is intended mainly as an aid in debugging to make virtual address translation easier. to perform the translation, the processor must read from the desired virtual address: after the read is complete, this register contains the real address that was accessed. the address contained in this register is an offset from the beginning of physical packet memory. length 32 bits type read only address xxxx 0d7c power on value x ? 0000 0000 ? restrictions none zero bits real address accessed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-27 these bits always read as ? 0 ? . 26-0 after any read operation from the processor to packet memory, these bits will contain the real address that was accessed.
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 212 of 676 pnr25.chapt04.01 august 14, 2000 6.15: vimem virtual buffer segment size register this register, along with the lower four bits of the real buffer base registers, defines the size of the second through 16th real buffers that are concatenated to make up a virtual buffer. two bits of this register are asso- ciated with each real buffer segment and indicate one out of four possible associations. the associative pos- sibilities are shown in the bit table below. every two bits defines the connection between a particular buffer segment and the real buffer base registers. length 32 bits type read/write address xxxx 0d00 power on value x ? 0000 0000 ? restrictions care must be used when setting up this register to ensure that only values that cor- respond to real buffer sizes that pools has also been set up to provide are loaded. a write to this register causes the virtual memory logic to calculate the different real buffer boundaries within a virtual buffer. this calculation requires information from the real buffer base registers to determine the size of the different segments mak- ing up the virtual buffer. for this reason, it is required that this register be written after the real buffer base registers have been initialized. after writing this register, the software must wait at least 2 ms before accessing virtual memory. 16th buffer segment 15th buffer segment 14th buffer segment 13th buffer segment 12th buffer segment 11th buffer segment 10th buffer segment 9th buffer segment 8th buffer segment 7th buffer segment 6th buffer segment 5th buffer segment 4th buffer segment 3th buffer segment 2th buffer segment reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 213 of 676 bit(s) description bit association 31-30 defines the 16th buffer segment ? s connection. 00 associates this real buffer segment with real buffer base register 0 01 associates this real buffer segment with real buffer base register 1 10 associates this real buffer segment with real buffer base register 2 11 associates this real buffer segment with real buffer base register 3 29-28 defines the 15th buffer segment ? s connection. 27-26 defines the 14th buffer segment ? s connection. 25-24 defines the 13th buffer segment ? s connection. 23-22 defines the 12th buffer segment ? s connection. 21-20 defines the 11th buffer segment ? s connection. 19-18 defines the 10th buffer segment ? s connection. 17-16 defines the 9th buffer segment ? s connection. 15-14 defines the 8th buffer segment ? s connection. 13-12 defines the 7th buffer segment ? s connection. 11-10 defines the 6th buffer segment ? s connection. 9-8 defines the 5th buffer segment ? s connection. 7-6 defines the 4th buffer segment ? s connection. 5-4 defines the 3rd buffer segment ? s connection. 3-2 defines the 2nd buffer segment ? s connection. 1-0 reserved. the first real buffer is implicitly associated with the vir- tual buffer, these bits will always be read as ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 214 of 676 pnr25.chapt04.01 august 14, 2000 6.16: vimem buffer map base address this register contains the address in packet memory at which the buffer map table starts. the buffer map table consists of a variable number of eight-byte entries for each buffer that is allocated in the system. the first 16 bits of each eight-byte entry contains the pool id and various status flags associated with this buffer, thus this base register is used in both real and virtual memory modes. in virtual memory mode, each of the three subsequent 16 bits contains an index which is associated with a buffer size base register using the buffer segment limit register. the index and buffer size base register are used to determine a real buffer address. if the map size is set to eight bytes, only one eight-byte entry is used for each buffer. if the map size is set to 16 bytes, two eight-byte entries are used for each buffer. if the map size is set to 32 bytes, four eight-byte entries are used for each buffer. if the map size is set to 64 bytes, five eight-byte entries are used for each buffer, and the remaining 24 bytes of the map are unused by the hard- ware. length 32 bits type read/write address xxxx 0d08 power on value x ? 0020 0000 ? (this value is actually the power up contents of the packet memory real base register added to the power up contents of this register (x ? 00000000 ? ) due to the automatic address adjustment explained below.) restrictions the base address for the buffer map must begin on a 64-byte boundary. when a base register is written, the hardware performs an automatic adjustment to the address using the contents of the packet memory real base register, and the packet memory offset register. this results in the actual value being stored, not being the value that is written by the program. this is done to make the virtual accesses that use the base register execute more quickly. the reverse adjustment is made when the read operation is performed, so that it appears to the program no different than a normal operation. care must be taken, however, to ensure that both the packet memory real base register and the packet memory offset register are set-up before any of the base registers are writ- ten. if the packet memory base register or the packet memory offset register are changed, packet memory should not be accessed until all the base registers have been written again. starting address reserved map entry size 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 defines the starting address of the buffer map 5-2 reserved, should be written with ? 0 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm virtual memory logic (vimem) page 215 of 676 6.17: vimem real buffer base addresses these registers contain the address in packet memory at which a block of memory begins that is used to pro- vide a given size buffer. in general, the block allocated must be large enough to contain as many buffers as will be freed to pools on initialization. however, for real buffer base 4, the size of the block reserved must be large enough so that one buffer is available for each of the virtual buffers freed to pools. these buffers must not be freed to pools because they are implicitly used as the first real buffer segment for each of the virtual buffers. if a given base register (and associated buffer size) is not used, the low four bits of the register should be set to x ? f ? to ensure that accesses of this buffer size are detected and flagged as an error. when using real memory mode (controlled in pools), all of these base registers are unused with the exception of base register zero, which contains the base address for all real memory buffers. in real mode, the low four bits of base register zero are of no significance. the size of the real buffers is controlled through the buffer size register. 1-0 defines the size of each map entry: 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes buffer size 01234 (implicit) length 32 bits 32 bits 32 bits 32 bits 32 bits type read/write read/write read/write read/write read/write address xxxx 0d20 xxxx 0d24 xxxx 0d28 xxxx 0d2c xxxx 0d30 power on value x ? 0020 000f ? x ? 0020 000f ? x ? 0020 000f ? x ? 0020 000f ? x ? 0020 000f ? restrictions the base address for any given buffer size must begin on a boundary that is equal to the buffer size. for example, the base address for 128-byte buffers must be on a 128-byte boundary, and the base address for 4096-byte buffers must be on a 4096-byte boundary. when a base register is written, the hardware performs an automatic adjustment to the address using the contents of the packet memory real base register and the packet mem- ory offset register. this results in the actual value being stored, not being the value that is written by the program. this is done to make the memory accesses that use the base reg- ister execute quicker. the reverse adjustment is made when the read operation is per- formed, so that it appears to the program no different than a normal operation. care must be taken however to ensure that the packet memory real base register and the packet memory offset register are set-up before any of the base registers are written. if the packet memory base register or the packet memory offset register is changed, packet memory should not be accessed until all the base registers have been written again. the power on value of these registers is actually the power on value of the packet memory real base register added to the contents of the packet memory offset register added to the original contents of these registers (x'0000000f'). bit(s) description
IBM3206K0424 ibm processor for network resources preliminary atm virtual memory logic (vimem) page 216 of 676 pnr25.chapt04.01 august 14, 2000 starting address reserved real buffersize 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 defines the starting address in packet memory of the memory block used to provide real buffers of defined size 5-4 reserved (user should write zeros and ignore read value) 3-0 defines the size of the real buffers in this block of memory with the following encoding: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 217 of 676 entity 7: atm packet/control memory arbitration logic (arbit) this section contains descriptions of the registers used by the arbiter logic. 7.1: arbit control priority resolution register high the bits in this register define the priority of requesting entities to control memory. length 28 bits type read/write address xxxx 0e00 restrictions none power on value x ? edc ba98 ? priority level e priority level d priority level c priority level b priority level a priority level 9 priority level 8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 27-24 the value loaded into these bits defines which entity will be requesting at priority level e (lowest priority). value encoding is: f: reserved 7: segbf e: chksm 6: txlcd d: pcore lo 5: rxlcd c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: rxxlt 1: bcach hi 8: rxque 0: pools hi 23-20 the value loaded into these bits defines which entity will request at priority level d. value encoding is as listed in the description of bits 27-24. 19-16 the value loaded into these bits defines which entity will request at priority level c. value encoding is as listed in the description of bits 27-24. 15-12 the value loaded into these bits defines which entity will request at priority level b.value encoding is as listed in the description of bits 27-24. 11-8 the value loaded into these bits defines which entity will request at priority level a. value encoding is as listed in the description of bits 27-24. 7-4 the value loaded into these bits defines which entity will request at priority level 9. value encoding is as listed in the description of bits 27-24. 3-0 the value loaded into these bits defines which entity will request at priority level 8. value encoding is as listed in the description of bits 27-24.
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 218 of 676 pnr25.chapt04.01 august 14, 2000 7.2: arbit control priority resolution register low the bits in this register define the priority of requesting entities to control memory. length 32 bits type read/write address xxxx 0e04 restrictions none power on value x ? 7654 3210 ? priority level 7 priority level 6 priority level 5 priority level 4 priority level 3 priority level 2 priority level 1 priority level 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 the value loaded into these bits defines which entity will request at priority level 7. value encoding is: f: reserved 7: segbf e: chksm 6: txlcd d: pcore lo 5: rxlcd c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: rxxlt 1: bcach hi 8: rxque 0: pools hi 27-24 the value loaded into these bits defines which entity will request at priority level 6. for value encoding, see the descrip- tion of bits 31-28. 23-20 the value loaded into these bits defines which entity will request at priority level 5. for value encoding, see the descrip- tion of bits 31-28. 19-16 the value loaded into these bits defines which entity will request at priority level 4. for value encoding, see the descrip- tion of bits 31-28. 15-12 the value loaded into these bits defines which entity will request at priority level 3. for value encoding, see the descrip- tion of bits 31-28. 11-8 the value loaded into these bits defines which entity will request at priority level 2. for value encoding, see the descrip- tion of bits 31-28. 7-4 the value loaded into these bits defines which entity will request at priority level 1. for value encoding, see the descrip- tion of bits 31-28. 3-0 the value loaded into these bits defines which entity will request at priority level 0 (highest priority). for value encoding, see the description of bits 31-28.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 219 of 676 7.3: arbit control error mask register the bits in this register control whether arbit detected error conditions on an entity ? s interface will lock the control memory subsystem. bits in this register also control the locking of the control memory subsystem based on control memory, packet memory, virtual memory, and bcach detected error conditions. resetting the appropriate bit will force errors from that source to be ignored. length 20 bits type clear/set address xxxx 0e08 and 0c power on value x ? fffff ? restrictions none bit(s) bit name/function 19 reserved 18 arbit detected packet errors 17 pcore errors 16 pools errors 15 bcach errors 14 vimem errors 13 paktt errors 12 comet errors 11 chksm 10 pcore 9 bcach 8 pools 7 csked 6 rxxlt 5rxque 4 segbf 3txlcd 2rxlcd 1gpdma 0dmaqs
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 220 of 676 pnr25.chapt04.01 august 14, 2000 7.4: arbit control error source register the bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. length 20 bits type clear/set address xxxx 0e18 and 1c power on value x ? 00000 ? restrictions bits 17 through 12 are driven from external entities and cannot be set or reset in this register. they must be set or reset in the entity of origin. bit(s) bit name/function 19 reserved 18 arbit detected packet errors 17 pcore errors 16 pools errors 15 bcach errors 14 vimem errors 13 paktt errors 12 comet errors 11 chksm 10 pcore 9 bcach 8 pools 7 csked 6 rxxlt 5rxque 4 segbf 3txlcd 2rxlcd 1gpdma 0dmaqs
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 221 of 676 7.5: arbit control winner register the bits in this register indicate which entity currently owns control memory. length 32 bits type read address xxxx 0e2c power on value x ? f ? restrictions none lock set/reset reserved control winner b control winner a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 for performance reasons, two sets of operational latches (bank a and bank b) exist in the arbiter for control memory. when set, this bit indicates that the b latches are active, and when reset indicates that the a latches are active. when this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. if this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that was accessing memory most recently. 30-8 reserved. will read ? 0 ? . 7-4 control winner b. 3-0 control winner a. f: reserved 7: segbf e: chksm 6: txlcd d: pcore lo 5: rxlcd c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: rxxlt 1: bcach hi 8: rxque 0: pools hi
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 222 of 676 pnr25.chapt04.01 august 14, 2000 7.6: arbit control address register a if latch bank a is active, the bits in this register indicate the last address that was used to access control memory. 7.7: arbit control address register b if latch bank b is active, the bits in this register indicate the last address that was used to access control memory. length 32 bits type read address xxxx 0e10 power on value x ? 0000 0000 ? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the control memory controller. length 32 bits type read address xxxx 0e20 power on value x ? 0000 0000 ? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the control memory controller.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 223 of 676 7.8: arbit control length register the bits in this register indicate the last length that was used to access control memory. length 16 bits type read address xxxx 0e14 power on value x ? 0000 0000 ? restrictions none latch bank b length latch bank a length 1514131211109876543210 bit(s) description 15-8 these bits contain the length used to access control memory through latch bank b. 7-0 these bits contain the length used to access control memory through latch bank a.
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 224 of 676 pnr25.chapt04.01 august 14, 2000 7.9: arbit control lock entity enable register the value programmed in this register controls what entity, if any, has access to packet memory immediately after memory has locked. this register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. length 4 bits type read/write address xxxx 0e28 power on value x ? f ? restrictions none bit map value 3210 bit(s) description 3-0 the value in these bits map to the following entities: f: reserved 7: segbf e: chksm 6: txlcd d: pcore lo 5: rxlcd c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: rxxlt 1: bcach hi 8: rxque 0: pools hi
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 225 of 676 7.10: arbit control config register the bits in this register control the operation of the control memory arbiter. 7.11: arbit packet priority resolution register high the bits in this register define the priority of requesting entities to packet memory. length 4 bits type clear/set address xxxx 0e38 and 3c power on value x ? 0 ? restrictions none reserved arbit entity state set/reset 3210 bit(s) description 3-2 reserved 1 this bit controls the arbit entity state debug mux. when set, the incoming entity requests and outgoing acknowledges are routed to the entity state pins. when reset, the internal state information is routed to the entity state pins. 0 when set, this bit forces all operations to control memory to be serialized. an operation from one entity must be entirely complete before an operation from another entity will be started. when reset, if the memory operation in process can be overlapped, a second operation will be started before the first operation is complete. length 28 bits type read/write address xxxx 0e80 power on value x ? edc ba98 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 226 of 676 pnr25.chapt04.01 august 14, 2000 bit(s) description 27-24 the value loads into these bits defines which entity will request at priority level e (lowest priority). value encoding is : f: reserved 7: segbf e: chksm 6: reserved d: pcore lo 5: rxaal c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: reserved 1: bcach hi 8: rxque 0: pools hi 23-20 the value loaded into these bits defines which entity will request at priority level d. for value encoding, see the descri p- tion of bits 27-24. 19-16 the value loaded into these bits defines which entity will request at priority level c. for value encoding, see the descri p- tion of bits 27-24. 15-12 the value loaded into these bits defines which entity will request at priority level b. for value encoding, see the descri p- tion of bits 27-24. 11-8 the value loaded into these bits defines which entity will request at priority level a. for value encoding, see the descrip - tion of bits 27-24. 7-4 the value loaded into these bits defines which entity will request at priority level 9. for value encoding, see the descrip- tion of bits 27-24. 3-0 the value loaded into these bits defines which entity will request at priority level 8. for value encoding, see the descrip- tion of bits 27-24.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 227 of 676 7.12: arbit packet priority resolution register low the bits in this register define the priority of requesting entities to packet memory. length 32 bits type read/write address xxxx 0e84 restrictions none power on value x ? 7654 3210 ? priority level 7 priority level 6 priority level 5 priority level 4 priority level 3 priority level 2 priority level 1 priority level 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 the value loaded into these bits define which entity will be requesting at priority level 7. value encoding is: f: reserved 7: segbf e: chksm 6: reserved d: pcore lo 5: rxaal c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: reserved 1: bcach hi 8: rxque 0: pools hi 27-24 the value loaded into these bits defines which entity will request at priority level 6. for value encoding, see the description of bits 31-28 above. 23-20 the value loaded into these bits defines which entity will request at priority level 5. for value encoding, see the description of bits 31-28 above. 19-16 the value loaded into these bits defines which entity will request at priority level 4. for value encoding, see the description of bits 31-28 above. 15-12 the value loaded into these bits defines which entity will request at priority level 3. for value encoding, see the description of bits 31-28 above. 11-8 the value loaded into these bits defines which entity will request at priority level 2. for value encoding, see the description of bits 31-28 above. 7-4 the value loaded into these bits defines which entity will request at priority level 1. for value encoding, see the description of bits 31-28 above. 3-0 the value loaded into these bits defines which entity will request at priority level 0 (highest priority). for value encoding, see the description of bits 31-28 above.
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 228 of 676 pnr25.chapt04.01 august 14, 2000 7.13: arbit packet entity error mask register the bits in this register control whether arbit detected error conditions on an entity ? s interface will lock the packet memory subsystem. bits in this register also control the locking of the packet memory subsystem based on control memory, packet memory, virtual memory, and bcache detected error conditions. reset- ting the appropriate bit will force errors from that source to be ignored. length 18 bits type clear/set address xxxx 0e88 and 8c power on value x ? fffff ? restrictions none bit(s) bit name/function 19 re-arbitration failure 18 arbit detected control errors 17 pcore error 16 pools error 15 bcach error 14 vimem error 13 paktt error 12 comet error 11 chksm lo 10 pcore lo 9 bcach lo 8 pools lo 7 csked 6reserved 5rxque 4 segbf 3reserved 2 rxaal 1gpdma 0dmaqs
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 229 of 676 7.14: arbit packet error source register the bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. length 20 bits type clear/set address xxxx 0e98 and 9c power on value x ? 00000 ? restrictions bits 17, 16, and 11 through 14 are driven from external entities and can not be set/reset in this register. they must be set/reset in the entity of origin. rearb. error control error pcore error pools error bcache error vimem error pakit error comet error chksm lo pcore lo bcach lo pools lo csked reserved rxque segbf reserved rxaal gpdma dmaqs 191817161514131211109876543210 bit(s) bit name/function 19 rearbitration failure. rearbitration detected while already handling rearbitration condition. this condition would indicate tha t the priorities programmed in the priority resolution logic were incorrectly programmed and pools high was not given the highest priority. 18 arbit detected control errors 17 pcore error 16 pools error 15 bcach error 14 vimem error 13 paktt error 12 comet error 11 chksm lo 10 pcore lo 9 bcach lo 8 pools lo 7 csked 6reserved 5rxque 4 segbf 3reserved 2 rxaal 1gpdma 0dmaqs
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 230 of 676 pnr25.chapt04.01 august 14, 2000 7.15: arbit packet winner register the bits in this register indicate which entity currently owns packet memory. length 32 bits type read address xxxx 0eac power on value x ? f ? restrictions none reserved active set/reset reserved packet winner b packet winner a 313029282726252423222120191817161514131211109876543210 bit(s) description 31 reserved. 30 for performance reasons, two sets of operational latches (bank a and bank b) exist in the arbiter for packet memory. when set, this bit indicates that the b latches are active, and when reset it indicates that the a latches are active. when this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. if this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that was accessing memory most recently. 29-8 reserved. will read ? 0 ? . 7-4 packet winner b. 3-0 packet winner a. value encoding is: f: reserved 7: segbf e: chksm 6: reserved d: pcore lo 5: rxaal c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: reserved 1: bcach hi 8: rxque 0: pools hi
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 231 of 676 7.16: arbit packet address register a if latch bank a is active, the bits in this register indicate the last address that was used to access packet memory. 7.17: arbit packet address register b if latch bank b is active, the bits in this register indicate the last address that was used to access packet memory. length 32 bits type read address xxxx 0e90 power on value x ? 0000 0000 ? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the packet memory controller. length 32 bits type read address xxxx 0ea0 power on value x ? 0000 0000 ? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the packet memory controller.
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 232 of 676 pnr25.chapt04.01 august 14, 2000 7.18: arbit packet length register the bits in this register indicate the last length that was used to access packet memory. length 16 bits type read address xxxx 0e94 power on value x ? 0000 0000 ? restrictions none latch bank b length latch bank a length 1514131211109876543210 bit(s) description 15-8 these bits contain the length used to access packet memory through latch bank b 7-0 these bits contain the length used to access packet memory through latch bank a
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 233 of 676 7.19: arbit packet lock entity enable register the value programmed in this register controls what entity, if any, has access to packet memory immediately after memory has locked. this register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. length 4 bits type read/write address xxxx 0ea8 power on value x ? f ? restrictions none bit map value 3210 bit(s) description 3-0 the value in these bits map to the following entities: value encoding is: f: reserved 7: segbf e: chksm 6: reserved d: pcore lo 5: rxaal c: bcach lo 4: gpdma b: pools lo 3: dmaqs a: csked 2: pcore hi 9: reserved 1: bcach hi 8: rxque 0: pools hi
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 234 of 676 pnr25.chapt04.01 august 14, 2000 7.20: arbit packet config register the bits in this register control the operation of the packet memory arbiter. length 4 bits type clear/set address xxxx 0eb8 and bc power on value x ? 0 ? restrictions none reserved arbit entity state debug mux forces all operations to packet memory to be serialized 3210 bit(s) description 3-2 reserved 1 this bit controls the arbit entity state debug mux. when set, the incoming entity requests and outgoing acknowledges are routed to the entity state pins. when reset, the internal state information is routed to the entity state pins. 0 when set, this bit forces all operations to packet memory to be serialized. an operation from one entity must be entirely com- plete before an operation from another entity will be started. when reset, if the memory operation in process can be over- lapped, a second operation will be started before the first operation is complete.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 235 of 676 7.21: arbit performance counter control the bits in this register determine what events are counted by the memory performance counters. this 32-bit register is divided into four 8-bit values, one value for each of the counters. the eight bits determine what memory event is counted by the associated counter. length 32 bits type read/write address xxxx 0eb8 and bc power on value x ? 9f1e 8000 ? restrictions none memory event counted by performance counter 3 memory event counted by performance counter 2 memory event counted by performance counter 1 memory event counted by performance counter 1 313029282726252423222120191817161514131211109876543210
IBM3206K0424 ibm processor for network resources preliminary atm packet/control memory arbitration logic (arbit) page 236 of 676 pnr25.chapt04.01 august 14, 2000 bit(s) description 31-24 the value loaded into these bits defines what memory event is counted by performance counter 3. these bits are defined as follows: bit 7: when reset, control memory events are counted, when set, packet memory events are counted by the associated counter. bit 6: reset the associated counter to 0. this bit will be reset by the hardware, during the same cycle that the counter is bei ng reset. bit 5: reserved bits 4-0: cycle type, encoded as: 00000 any request 00001 any request between 0 and 4 bytes 00010 any request between 5 and 8 bytes 00011 any request between 9 and 16 bytes 00100 any request between 17 and 32 bytes 00101 any request between 33 and 64 bytes 00110 any request between 65 and 128 bytes 00111 reserved 01000 any read request 01001 any read request between 0 and 4 bytes 01010 any read request between 5 and 8 bytes 01011 any read request between 9 and 16 bytes 01100 any read request between 17 and 32 bytes 01101 any read request between 33 and 64 bytes 01110 any read request between 65 and 128 bytes 01111 reserved 10000 any write request 10001 any write request between 0 and 4 bytes 10010 any write request between 5 and 8 bytes 10011 any write request between 9 and 16 bytes 10100 any write request between 17 and 32 bytes 10101 any write request between 33 and 64 bytes 10110 any write request between 65 and 128 bytes 10111 reserved 11000 read op latency 11001 write op latency 11010 reserved 11011 reserved 11100 reserved 11101 reserved 11110 hold current count 11111 every cycle 23-16 the value loaded into these bits define what memory event is counted by performance counter 2. 15-8 the value loaded into these bits define what memory event is counted by performance counter 1. 7-0 the value loaded into these bits define what memory event is counted by performance counter 0.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 atm packet/control memory arbitration logic (arbit) page 237 of 676 7.22: arbit memory performance counter these registers count memory events as defined in the arbit performance counter control register. length 32 bits type read/write address counter 0 xxxx 0ec0 counter 1 xxxx 0ec4 counter 2 xxxx 0ec8 counter 3 xxxx 0ecc power on value x ? 0000 0000 ? restrictions none number of times the event selected in the performance counter control register has occurred 313029282726252423222120191817161514131211109876543210 bit(s) description 31-0 these bits count the number of times that the event selected in the performance counter control register has occurred.
IBM3206K0424 ibm processor for network resources preliminary the bus dram cache controller (bcach) page 238 of 676 pnr25.chapt04.01 august 14, 2000 entity 8: the bus dram cache controller (bcach) this entity provides the caching function for data transfers on the control processor bus. the array is orga- nized in four logically separate cache lines, any of which can be used for processor accesses or master/slave dma accesses. the cache is accessible on byte boundaries on the control processor side; access of this entity to comet is performed on 64-bit (word) boundaries. the address tags of each of the four 32-byte cache lines are compared to the requesting address to select the bank to be used to satisfy the control pro- cessor bus operation. streaming accesses of the cache use a predictive look-ahead scheme to fill the cache for read operations from packet memory. under normal conditions, a single cache miss will be expected at the start of each dma read operation. this cache miss will initiate a read operation from packet memory to fetch the requested data and enough additional data to fill the remainder of the cache line. if the requested data is in the last n bytes (n is programmable via the bcach control register) of the cache line, the read operation to comet will be extended to fill the next cache line with sequential data as well. this same programmable value is used to determine when to initiate the next sequential cache line fill operation during a dma read operation. during non-aligned write operations to packet memory, bcach will perform read/modify/write cycles to pakit. processor accesses operate without predictive caching. when a cache miss occurs, a comet read opera- tion will be initiated to fetch the 32-byte block of data that contains the requested data. the data read from comet will be loaded into the ? least recently used ? cache line. this section contains descriptions of the registers used by the bus cache logic.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the bus dram cache controller (bcach) page 239 of 676 8.1: bcach control register the bits in this register control the various functions provided by the cache logic. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 1000 and 004 power on value x ? 2000 0000 ? restrictions none enable caching packet memory reads enable caching packet memory writes retry delayed accesses bcach diagnostic mode flush cache line 3 flush cache line 2 flush cache line 1 flush cache line 0 use rxque advice ack rxque immediately enable ping pong buffer support disable locking on collisions enable automatic flush force predictive fill/flush for non-streaming accesses reserved predictive fill threshold timed flush time out value 313029282726252423222120191817161514131211109876543210 bit(s) function description 31 enable caching packet memory reads when this bit is set, reads of packet memory will be cached. 30 enable caching packet memory writes when this bit is set, writes to packet memory will be cached. 29 retry delayed accesses when this bit is set, and the cache is enabled, any access of packet memory that cannot be satisfied within one cycle will be terminated by the cache with a retry indication. the accessing device is expected to allow competing devices a chance to gain access to the bus and then retry the same operation. 28 bcach diagnostic mode when this bit is set, diagnostic mode is enabled and reads and writes of the bcach array from the processor are enabled. when reset, reads from the processor will return x ? baddbadd ? and writes will have no affect. care must be taken when performing writes from the processor: if a cache line fill operation is in process and a write is per- formed from the processor that writes to the same address in the array as is being written from the fill operation, results are indeterminate. 27 flush cache line 3 setting this bit forces a flush of cache line 3 if it is dirty. this bit is reset by the hardware when the flush completes. 26 flush cache line 2 setting this bit forces a flush of cache line 2 if it is dirty. this bit is reset by the hardware when the flush completes.
IBM3206K0424 ibm processor for network resources preliminary the bus dram cache controller (bcach) page 240 of 676 pnr25.chapt04.01 august 14, 2000 25 flush cache line 1 setting this bit forces a flush of cache line 1 if it is dirty. this bit will be reset by the hard- ware when the flush completes. 24 flush cache line 0 setting this bit forces a flush of cache line 0 if it is dirty. this bit will be reset by the hard- ware when the flush completes. 23 use rxque advice when set, advice from the receive queue entity causes the cache logic to fill a line with the data from the start of the buffer that was just dequeued by the software. this should improve performance by having the receive data available when the processor accesses the buffer after the dequeue. to make best use of this feature, the code should access the receive data shortly after the dequeue to avoid the data in the cache line from becom- ing stale and being invalidated due to other cache functions. when reset, advice from the receive queue entity will be ignored. 22 ack rxque immediately when reset, advice from the receive queue entity is acknowledged immediately even if the cache is not able to perform the requested data fetch. in this case, the advice is lost, and the cache will not fetch the data until the processor requests it again. when set, the advice from the receive queue entity is not acknowledged until the cache has actually latched the advice information. this guarantees that the advice will be used, but may cause delays in the receive queue entity ? s processing. 21 enable ping pong buffer support when reset, this bit disables the two-line ping pong feature associated with consistent sequential cache accesses. when set, a series of sequential accesses to packet mem- ory that would normally require more than two cache lines to be satisfied is limited to only two cache lines, regardless of the length of the transfer. this feature is intended to improves cache performance by preventing cache lines that contain the most recently used processor data from being flushed due to a long streaming access. 20 disable locking on collisions when set, this bit prevents detected collisions from locking up the memory control entity. 19 enable automatic flush when set, this bit enables the automatic flush feature of the cache. the auto flush fea- ture forces a flush of a cache line to be performed if a sequential write of the last 2 loca- tions in the cache line is detected. 18 force predictive fill/flush for non-streaming accesses when set, this bit forces the predictive fill/flush logic to operate on all accesses of the cache rather than just streaming accesses. when reset, the predictive fill logic will only be activated for streaming accesses in the cache. 17-16 reserved reserved. 15-8 predictive fill threshold these bits set the threshold at which a predictive fill will be initiated. if all of these bits are set to ? 1 ? , a predictive fill will be initiated on the first streaming access of a cache line, regardless of which byte in the line is accessed. if this field is set to x ? 3f ? a predictive fill will be initiated on any streaming access of bytes at offset x ? 2 ? through x ? 7 ? in the cache line. if this field is set to x ? 03 ? a predictive fill will be initiated on any streaming access of bytes at offset x ? 6 ? or x ? 7 ? in the cache line. setting the field to all ? 0 ? s will disable predic- tive fills. 7-0 timed flush time out value these bits control the time-out value used to monitor dirty cache lines for inactivity. the value loaded into these eight bits is the number of 240 ns ticks that can occur without any activity in a dirty cache line before the cache logic will force a flush of the line to main memory. setting these bits to all ? 0 ? s disables the timed flush feature. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the bus dram cache controller (bcach) page 241 of 676 8.2: bcach status register the bits in this register reflect the current status of the cache. see note on set/clear type registers on page 93 for more details on addressing. length 8 bits type clear/set address xxxx 1008 and 00c power on value x ? 00 ? restrictions none pools invalidation of dirty lines write hit on multiple lines read hit on multiple lines negative ack from vimem collision on cache line 3 collision on cache line 2 collision on cache line 1 collision on cache line 0 76543210 bit(s) function description 7 pools invalidation of dirty lines when this bit is set, it indicates that pools requested that the cache logic invalidate a line that was dirty. this is usually an indication that a buffer was freed by the software before data written out to the buffer had been flushed to memory. this may or may not be an error condition. 6 write hit on multiple lines when this bit is set, the cache logic has detected a write hit to multiple lines. this indi- cates an internal logic error in the cache. 5 read hit on multiple lines when this bit is set, the cache logic has detected a read hit to multiple lines. this indi- cates an internal logic error in the cache. 4 negative ack from vimem when set, the cache logic has detected a negative acknowledgment from the virtual memory logic entity. this indicates that a virtual buffer boundary was crossed and a new real buffer was needed to map the requested address space into, but no real buffer was available. in addition to setting this status bit, the cache logic writes the pattern x ? zzzzzbad ? into the header of the packet at offset x ? c ? where zzzzz is the offset of the failing write into the packet. 3 collision on cache line 3 when this bit is set, the cache logic has detected a collision in cache line 3. this is a sit- uation where another entity in IBM3206K0424 was accessing an area of memory that was contained in one of the cache lines that was dirty. further information for problem diagnosis is latched in the memory controller logic when this condition is detected. 2 collision on cache line 2 when this bit is set, the cache logic has detected a collision in cache line 2. 1 collision on cache line 1 when this bit is set, the cache logic has detected a collision in cache line 1. 0 collision on cache line 0 when this bit is set, the cache logic has detected a collision in cache line 0.
IBM3206K0424 ibm processor for network resources preliminary the bus dram cache controller (bcach) page 242 of 676 pnr25.chapt04.01 august 14, 2000 8.3: bcach interrupt enable register the low eight bits in this register allow the user to selectively determine which bits in the bcach status regis- ter will cause processor interrupts. a ? 0 ? in a bit position masks interrupts from the corresponding bit location in the bcach status register. a ? 1 ? in a bit position allows interrupts for the corresponding bit in the bcach status register. the high eight bits in this register allow the user to selectively determine which bits in the bcach status register will lock the cache. a ? 1 ? in any bit position forces the cache to lock if the correspond- ing bit is set in the bcach status register. if the cache locks, all status regarding the cache lines is main- tained until the cache enable bits in the control register are turned off. see note on set/clear type registers on page 93 for more details on addressing. 8.4: bcach high priority timer value this register defines the number of 15 ns cycles that w ill pass from the time that a valid pci bus request is raised to bcach until bcach will raise its high priority request to the memory controllers. a value of ? 0 ? in this register disables this function completely. length 16 bits type clear/set address xxxx 1010 and 014 power on value x ? ffff ? restrictions none length 8 bits type read/write address xxxx 1040 power on value x ? 40 ? restrictions none number of 15 ns cycles 76543210 bit(s) description 7-0 specifies the number of 15 ns cycles before a high priority request. for example, if bit 3 is set to ? 1 ? and all others are set to ? 0 ? , then 6 cycles (120 ns) will pass between receipt of request and sending request to controllers.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the bus dram cache controller (bcach) page 243 of 676 8.5: bcach line tag registers these registers are useful only in diagnostic testing of the cache logic. each register will contain the tag value for the data contained in that particular cache line. length 32 bits type read only address tag number 0 xxxx 1080 tag number 1 xxxx 10a0 tag number 2 xxxx 10c0 tag number 3 xxxx 10c0 power on value x ? 0000 0000 ? restrictions none 32-bit memory line address modulo read fill op. reserved 313029282726252423222120191817161514131211109876543210 bit(s) description 31-5 these bits contain the address of the 32-byte line of memory contained in the cache line. 4-3 in an attempt to provide the fastest possible access to data in memory, the 8 byte word in memory that contains the requested read data is accessed first and all other entries in the cache line are filled by wrapping back to the beginning of the cache line if required. these two bits contain the starting address for the modulo read fill operation. they will also contain the least significant address bits when a cache line is initially written to. 2-0 will always be returned as ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary the bus dram cache controller (bcach) page 244 of 676 pnr25.chapt04.01 august 14, 2000 8.6: bcach line valid bytes register these registers are useful only in diagnostic testing of the cache logic. each register will contain a bit signifi- cant flag indicating which bytes in the 32-byte cache line are valid. all of these bits will be active after a cache line fill operation has occurred, but any combination of these bits can be valid after the processor has per- formed a write operation to memory. length 32 bits type read only address tag number 0 xxxx 1084 tag number 1 xxxx 10a4 tag number 2 xxxx 10c4 tag number 3 xxxx 10e4 power on value x ? 0000 0000 ? restrictions none cache line fill operation set/reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 each bit indicates whether the associated byte in the cache line contains valid data or not. if the bit is set, the cache line contains valid data and a fetch from main storage is not required to fulfill a request for a read from this location. if the bi t is reset, a read of the associated location will require a cache line fill operation before the request can complete.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 the bus dram cache controller (bcach) page 245 of 676 8.7: bcach line status register these registers are useful only in diagnostic testing of the cache logic. each register will contain a bit signifi- cant flag indicating the current status of the associated cache line. length 32 bits type read only address tag number 0 xxxx 1088 tag number 1 xxxx 10a8 tag number 2 xxxx 10c8 tag number 3 xxxx 10e8 power on value tag number 0 x ? 0000 0000 ? tag number 1 x ? 0000 0010 ? tag number 2 x ? 0000 0020 ? tag number 3 x ? 0000 0030 ? restrictions none valid tag reserved loaded by pci read loaded by predictive fill loaded by rxque advice loaded by pci write reserved lru bits dirty bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 valid tag when set, this indicates that the associated tag register contains a valid tag. 30-12 reserved reserved 11 loaded by pci read when set, this bit indicates that the associated tag register was loaded due to a read request from the pci bus 10 loaded by predictive fill when set, this bit indicates that the associated tag register was loaded due to a predictive fill request 9 loaded by rxque advice when set, this bit indicates that the associated tag register was loaded due to advice from the receive queue entity 8 loaded by pci write when set, this bit indicates that the associated tag register was loaded due to a write request from the pci bus 7-6 reserved reserved 5-4 lru bits these bits indicate the cache lines current position with respect to the least recently used algorithm. a value of ? 0 ? indicates it is the most recently used while a value of ? 3 ? indicates the least recently used.
IBM3206K0424 ibm processor for network resources preliminary the bus dram cache controller (bcach) page 246 of 676 pnr25.chapt04.01 august 14, 2000 8.8: bcach cache line array this array is divided into four 32-byte buffers used as cache lines 0, 1, 2, and 3. 3-0 dirty bits these bits, when set, indicate that the associated eight-byte word of the cache line is dirty. this information is used on cache line flushes, to lower memory utilization, by eliminating non-dirty word flushes from the cache line flush operation. for example if these bits contain a x ? 1 ? , only the eight-byte word at offset zero in the cache line is dirty, so the flush operation will only write this one word to memory, saving three memory access cycles. if these bits contain a x ? c ? , only the two eight-byte words starting at offset x ? 10 ? in the cache line are dirty. length 16 words x 64 bits type read/write address xxxx 1100 - 17f restrictions this array can only be accessed when the diagnostic mode bit in the control regis- ter is set. bit(s) description ?? the four cache lines start at the following offsets into the array: line 0 offset x'00' line 1 offset x'20' line 2 offset x'40' line 3 offset x'60' bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 247 of 676 entity 9: buffer pool management (pools) pools acts as a memory manager for the IBM3206K0424. memory buffers are checked out and checked in via two operations (primitives) supported by pools: the get pointer primitive and the free pointer primitive. these primitives can be performed explicitly by accessing specified addresses within the pools entity, and they may also be done by hardware. csked can free a buffer upon transmission if specified by the corre- sponding packet header (see ecc syndrome bits on page 196), and raall gets buffers to store received data. in addition, pools contains mechanisms to control resource utilization and supports a real memory mode and a virtual memory mode. basic operation in real memory mode if memory is viewed as a series of buffers, pools maintains a circular list of available buffers. there are pointers (the head and tail) to the start and the end of the list. when a get pointer primitive is executed, the buffer at the head of the list is checked out, the head pointer is advanced and the correct resource group(s) is debited. when a free pointer primitive is executed, the freed buffer is checked in at the end of the list, the tail pointer is advanced, and the correct resource group is credited. basic operation in virtual memory mode with the addition of virtual memory, pools must maintain five sets of head and tail pointers, thresholds, and active counts: one for the virtual buffers themselves and the rest for the four regions of real buffers that con- stitute the virtual buffers. in this case the base virtual address is the item returned from a get pointer operation and returned during a free pointer operation. when the get buffer primitive is executed, pools creates an active buffer map (page table) for the virtual address. as the virtual address is used and buffer (page) bound- aries are crossed, vimem will request buffers from pools when a buffer (page) fault occurs. vimem then places the buffer index in the buffer map. when the virtual buffer is no longer needed and a free pointer prim- itive is issued with the starting virtual address, pools takes the contents of the buffer map and frees the resources that were assigned to the buffer map. resource controls pools adds another layer of service by creating "pools" of buffers (currently a maximum of 16 pools). for each pool, a maximum number of allowable buffers can be specified. the intent is to make it possible for sev- eral applications to use an IBM3206K0424 at once without one or more applications starving the remaining applications for memory buffers. particular pools buffers are divided into ? guaranteed ? and ? common ? buffers. all the guaranteed buffers are considered to be dedicated to their respective pool and are therefore not avail- able for general use. the common buffers are all the memory buffers remaining after the guaranteed buffers are subtracted from the total buffers. to maintain the buffer limits on each pool, every pool has a guaranteed threshold, total threshold, and an active count. when a request is made for a buffer from a particular pool, the guaranteed threshold is first checked. if the active count of the pool is less than the guaranteed threshold, the buffer is provided. if the guaranteed threshold has been reached, then the total threshold is checked. if the active count is equal to the total threshold, no buffer is provided. if the active count is less than the total threshold, and a common buffer is available, a buffer is provided. if there are no common buffers available, a buffer cannot be provided and a null index is returned. to determine if a common buffer is available, a count is maintained for each size of buffer.
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 248 of 676 pnr25.chapt04.01 august 14, 2000 virtual memory overview each virtual buffer consists of a number of real buffers. for each virtual buffer there is a buffer map that defines the size and number of real buffers that may be allocated to the virtual buffer. each map is built from a common template (the vimem virtual buffer segment size register) that associates 1 to n buffer indexes in the map to a real buffer in one of the four real buffer regions defined in vimem. in vimem, the buffer map base address register defines the size of the map and therefore also the number of buffer indexes in the vir- tual buffer map. each eight-byte entry of the map contains the pool id of the pool to which the buffer is allo- cated plus space for three real buffer segment indexes. this implies the smallest map yields a virtual buffer of one to four real buffer segments (three real buffer segments plus the implicit real buffer that all virtual buffers are allocated). the biggest map defines a virtual buffer of 1-16 real buffer segments (15 plus the implicit one). the intention of this structure is to allow the user to customize the value in the virtual buffer segment size register to utilize memory in an efficient manner relative to network data traffic. for example, if network traffic contained 50% packets of < 512 bytes, 35 % packets of < 1k bytes, and the rest was < 5k bytes, the user could set up virtual memory to use three real segments of 512 bytes, 512 bytes, and 4k bytes respectively. the incoming data would neatly fit into the segments and minimize wasted memory. pools and vimem maintain the maps for the virtual buffers. on a write that crosses a real buffer boundary into an as yet an unresolved region of a virtual buffer, a page fault occurs. when a page fault occurs, pools determines whether or not a real buffer can be assigned. if it can be assigned, the index of the real buffer rel- ative to the base address of the particular buffer size is placed by vimem into the buffer map. the first buffer is implicitly associated with the virtual memory address for a particular virtual buffer and enough real memory must be available to support the first real buffer of each virtual buffer at initialization time. there is not neces- sarily enough real storage for all the possible real buffers associated with a virtual buffer.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 249 of 676 all real buffers of a particular size are stored in a contiguous region of memory. the buffer index, in conjunc- tion with the base address for this real buffer size, points to a particular real buffer. the implicit buffers are also stored in a data structure of this type. virtual address buffer map packet size (17 bits max) 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit note: the buffer index of the first buffer and buffer limit segment register (32 bits) buffer index of the first buffer in the virtual address (16 bits max) number of bits for largest 32 bit virtual address the virtual address index are the same. also note that they are right justified. virtual address buffer map
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 250 of 676 pnr25.chapt04.01 august 14, 2000 the following example illustrates these concepts. buffer/virtual memory allocation structure in memory buffer size one base index zero buffer size one index one buffer size one index two ...... buffer size one index n skip to next buffer size bound buffer size two base index zero buffer size two index one buffer size two index two ...... buffer size two index n skip to next buffer size bound buffer size three base index zero buffer size three index one buffer size three index two ...... buffer size three index h skip to next buffer size bound buffer size four base index zero buffer size four index one buffer size four index two ...... buffer size four index n skip to implicit buffer base address implicit buffer index zero implicit buffer index one implicit buffer index two ...... implicit buffer index n the single box represents the storage for the whole buffer, whatever its size. these indexes are determined by the virtual buffer ? s virtual address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 251 of 676 virtual address buffer map buffer,size(4) 256 base index zero buffer, size(4) 256 index one buffer, size(4) 256 index two ... buffer, size(4) 256 index n skip to next buffer size base address buffer, size(0) 256 base index zero buffer, size(0) 256 index one buffer, size (0) 256 index two ... buffer, size(0) 256 index n skip to next buffer size base address buffer, size(1) 1024 base index zero buffer, size(1) 1024 index one buffer, size (1) 1024 index two ... buffer, size(1) 1024 index n skip to next buffer size base address buffer, size(2) 4096 base index zero buffer, size(0) 4096 index one buffer, size (0) 4096 index two ... buffer, size(2) 4096 index n skip to next buffer size base address buffer, size(3) 16384 base index zero buffer, size(3) 16384 index one buffer, size (3) 16384 index two ... buffer, size(3) 16384 index n skip to virtual address base address v.m. address index zero v.m. address index one v.m. address index two v.m. address index n ... brb4 + shifted buffer index 0 + offset into pkt pool id 0000 buffer index implicit 256 byte buffer index size(0) 256 byte buffer index size (0) 256 byte buffer index size (1) 1024 byte buffer index size(3) 16384 unused buffer index 1 buffer index 2 buffer index 0 pool id 0000 buffer index 4 buffer index last segment decode one yes? segment decode two yes? segment decode three yes? segment decode four yes? segment decode fourteen yes? segment decoder brb0 + shifted buffer index 0 + offset into pkt brb0 + shifted buffer index 2 offset into pkt brb2 + shifted buffer index 0 + offset into pkt bbr2 + shifted buffer index 4 offset into pkt bbr3 + shifted buf. index last + offset into pkt virtual address. index implicit buffer index size(4) 0 no. of bits for largest packet size(17 max) packet address region brbm + shifted buffer index 0 + offset into map 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 2 bits 2 bits 2 bits 2 bits 2 bits 2 bits base address registers base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer map brbm packet storage area byte buffer index size(2) 4096 byte segment decode zero yes?
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 252 of 676 pnr25.chapt04.01 august 14, 2000 the lower seventeen bits of the virtual address are used in conjunction with the segment template in the vimem virtual buffer segment size register to determine from which portion of the buffer map the buffer index is retrieved. once the buffer index is retrieved, it is combined with the appropriate base address for that particular buffer size. the offset into the buffer is then added to get the real 32-bit address that is used in physical memory. pools uses the data structures above to manage packet memory resources. each lcd is associated with a particular pool and multiple different lcds may be associated with that same pool. within a pool, there are five different resource categories and two variables to go with each resource. 9.1: pools get pointer primitive the pools get pointer primitive returns a pointer to the requester. the request to the virtual packet/buffer size 4 address will always return a memory address. if in virtual mode, the address will be virtual. requests made for buffer sizes 0 to 3 will not return an address but rather a buffer index in bits 15-0. the real address associated with this index can be generated by shifting the index by the buffer size (for example, six bit posi- tions for a 64-byte buffer) and adding the result to the base address for this size buffer. access to buffer sizes 0 to 3 is not permitted in operational mode. the address of the primitive also selects the pool id. the pool id is contained in address bits 5-2, and it selects which pool will be charged for the pointer. the buffer size is selected with address bits 8-6. if there are no more pointers available in the specified pool, a null pointer is returned. the active pointer count for that pool is incremented if a non-null pointer is returned. if the guaranteed threshold has been exceeded and a buffer from the common pool is returned, the common pools count for that size is decremented by 1. resources and variables example resource type, pool 0000 guaranteed number total number virtual memory addresses 100 150 buffer type one 200 300 buffer type two 50 100 buffer type three 10 5 buffer type four 0 10 virtual memory addresses 100 150 length 32 bits type read only address buffer size 0 xxxx 3200 buffer size 1 xxxx 3240 buffer size 2 xxxx 3280 buffer size 3 xxxx 32c0 virtual packets/ buffer size 4 xxxx 3300 power on value x ? 00000000 ? restrictions during normal operations this register is to be used as a read only register. writes to this address will be ignored.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 253 of 676 9.2: pools free pointer primitive the pools free pointer primitive returns the pointer to the proper free list. if it is a virtual memory address, the virtual memory buffer map is traversed to free the indexes associated with the virtual memory address. in the case where it is a real memory buffer, the single index is freed. this primitive uses address mapping to select the size of the object to be freed. the size is contained in address bits 4-2. during normal operation, only frees to buffer size four are relevant. during initialization mode, buffer sizes 0 to 3 can be used to load indexes. the indexes are loaded into bits 31-16. in normal operations it is not necessary to read this "register". 9.3: pools common pools count registers the pools common pools count registers indicates the number of pointers in the particular common pool. the bits are a 16-bit count. the get pointers that exceed the guaranteed allocation decrement this count by one assuming that the count is non-zero. when the count is zero, the get buffer operation will fail. the free pointers that operate beyond the guaranteed threshold for a particular client and free the pointer(s) increment this count by one. the microcode should initialize these registers to the value of the respective common pool that it desires to have. length 32 bits type write only address buffer size 0 xxxx 3350 buffer size 1 xxxx 3354 buffer size 2 xxxx 3358 buffer size 3 xxxx 335c virtual packets/ buffer size 4 xxxx 3360 power on value x ? 00000000 ? restrictions during normal operations this register is to be used as a write only register. reads from this address will return ? 0 ? . length 16 bits type read/write address buffer size 0 xxxx 3000 buffer size 1 xxxx 3004 buffer size 2 xxxx 3008 buffer size 3 xxxx 300c virtual packets / buffer size 4 xxxx 3010 power on value x ? 0000 ? restrictions during normal operations these registers are to be used as a read only. writing to these registers during operation could create a data loss situation. this register should be set up by the microcode at initialization time.
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 254 of 676 pnr25.chapt04.01 august 14, 2000 9.4: pools client thresholds array the pools client thresholds array holds the guaranteed and total threshold values for the 16 pools and the four (five) pointer sizes. this array contains the guaranteed and total thresholds for the managed pools. when a get pointer primitive is processed, the values in this array are used to determine if a primitive can return a pointer. the active count from the active packet count array is used with these registers to deter- mine if a threshold has been exceeded. if the guaranteed threshold has been exceeded and the total not exceeded and there is a common pointer available, then the common count will be incremented. if there are no common buffers available or the request will cause the total threshold to be exceeded, the request will be rejected. during a free pointer primitive processing, the pointer is returned to the free list and these thresh- olds are used to determine if a common count should be credited. length 32 bits x 16 words type read/write address buffer size 0 xxxx 3400 buffer size 1 xxxx 3440 buffer size 2 xxxx 3480 buffer size 3 xxxx 34c0 virtual packets/ buffer size 4 xxxx 3500 power on value x ? 00000000 ? restrictions none guaranteed threshold total threshold 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 guaranteed threshold 15-0 total threshold.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 255 of 676 9.5: pools user threshold and client active packet count array the pools user threshold and client active packet count array holds the user thresholds and active pointer counts for each of the 16 managed pools and four (five) pointer sizes. when a get pointer primitive is processed, the active count is retrieved and compared with the threshold counts. if it falls within bounds and a pointer is available, the active count will be incremented by one reflect- ing the additional buffer charged to that queue. when a free pointer primitive is processed, the active count is retrieved, and, when the pointer is returned to the free list, the active buffer count is decremented by one. the user threshold may be used to check on resource utilization as opposed to resource allocation. the guaranteed and total thresholds are used when allocating resources to make decisions. the user thresh- old is not used to govern resource allocation directly. one such use is for high water mark indication. when a free pointer primitive is processed or a get pointer is processed the active packet count is compared to the user threshold. if the event interface is enabled and a boundary condition is crossed an event is issued to the event interface. length 32 bits x 16 words type read/write address buffer size 0 xxxx 3600 buffer size 1 xxxx 3640 buffer size 2 xxxx 3680 buffer size 3 xxxx 36c0 virtual packets/ buffer size 4 xxxx 3700 power on value x ? 00000000 ? restrictions none user threshold active packet count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 user threshold 15-0 active packet count
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 256 of 676 pnr25.chapt04.01 august 14, 2000 9.6: pools pointer queues dram head pointer offset address register the pools pointer queues dram head pointer offset address register indicates the address in dram where the head of the queue starts. this address, however, is only relative to the dram portion of the queue. unless the head of the queue portion of the cache is locked out and needs two frames, the actual head of the queue is in the cache. these 19 bits on write represent the offset to the address in dram of the head of the queue relative to the dram base address. on a read, the address in dram of the pointer is returned. this pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. because each memory reference contains four indices, this allows for a possible 128k index locations in the queue. length 32 bits read/19 bits write type read/write address buffer size 0 xxxx 3014 buffer size 1 xxxx 3018 buffer size 2 xxxx 301c buffer size 3 xxxx 3020 virtual packets/ buffer size 4 xxxx 3024 power on value buffer size 0 x ? 00 01 c0 00 ? buffer size 1 x ? 00 02 00 00 ? buffer size 2 x ? 00 02 40 00 ? buffer size 3 x ? 00 02 60 00 ? virtual packets/ buffer size 4 x ? 00 02 70 00 ? restrictions during normal operations this register is to be used as a read only register. this regis- ter defaults to zero at initialization. it is assumed that the queues start on a maximum size queue boundary. these registers should be set up at initialization time. this regis- ter is cleared when the pools pointer queues dram lower bound address register is written to.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 257 of 676 9.7: pools pointer queues dram tail pointer offset address register the pools pointer queues dram tail pointer offset address register indicates the offset address in dram where the tail of the queue starts. this address, however, is only relative to the dram portion of the queue. unless a ? no cache frames to be written through ? state is in effect, the actual tail of the queue is in the cache. these 19 bits on write represent the offset to the address in dram of the tail of the queue relative to the dram base address. on a read, the address in dram of the pointer is returned. this pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. since each memory reference contains four indices this allows for 128k index locations possible in the queue. length 16 bits type read/write address buffer size 0 xxxx 3028 buffer size 1 xxxx 302c buffer size 2 xxxx 3030 buffer size 3 xxxx 3034 virtual packets/ buffer size 4 xxxx 3038 power on value buffer size 0 x ? 00 01 c0 00 ? buffer size 1 x ? 00 02 00 00 ? buffer size 2 x ? 00 02 40 00 ? buffer size 3 x ? 00 02 60 00 ? virtual packets/ buffer size 4 x ? 00 02 70 00 ? restrictions during normal operations this register is to be used as a read only register. this regis- ter defaults to zero at initialization. it is assumed that the queues start on the maximum size queue boundary. these registers should be setup at initialization time. this regis- ter is cleared when the pools pointer queues dram lower bound address register is written to.
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 258 of 676 pnr25.chapt04.01 august 14, 2000 9.8: pools pointer queues dram lower bound address register the pools pointer queues dram lower bound address register indicates the address in dram where the queue data structure is initially started. when the queue reaches the maximum address allowed for in the upper bound register, it wraps back around to the address specified in this register. this implements the queue in a circular buffer. these 32 bits represent the address in dram where the queue begins and eventually wraps to. at initializa- tion, this register and the pools pointer queues dram tail pointer offset address register and the pools pointer queues dram head pointer offset address register must be equal. length 32 bits type read/write address buffer size 0 xxxx 303c buffer size 1 xxxx 3040 buffer size 2 xxxx 3044 buffer size 3 xxxx 3048 virtual packets/ buffer size 4 xxxx 304c power on value buffer size 0 x ? 00 01 c0 00 ? buffer size 1 x ? 00 02 00 00 ? buffer size 2 x ? 00 02 40 00 ? buffer size 3 x ? 00 02 60 00 ? virtual packets/ buffer size 4 x ? 00 02 70 00 ? restrictions during normal operations, this register is to be used as a read only register. this regis- ter should be setup at initialization time. the size of the dram queue storage which is formed with the lower and upper bounds is constrained in its size. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. note that if the max- imum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 259 of 676 9.9: pools pointer queues dram upper bound register the pools pointer queues dram upper bound register indicates the max queue length in dram of the queue data structure. when the queue reaches this address, it wraps back to the address specified by the lower bound register. this implements the queue in a circular buffer. this upper bound is to be provided as an encoded field. the encoded field represents the number of eight-byte addresses that can be contained by the queue. these four bits represent the encoded maximum queue length in dram which, when matched, trigger the queue to wrap back to the address contained in the dram lower bound address register. length 4 bits type read/write address buffer size 0 xxxx 3050 buffer size 1 xxxx 3054 buffer size 2 xxxx 3058 buffer size 3 xxxx 305c virtual packets/ buffer size 4 xxxx 3060 power on value buffer size 0 x ? b ? buffer size 1 x ? a ? buffer size 2 x ? 9 ? buffer size 3 x ? 9 ? virtual packets/ buffer size 4 x ? b ? restrictions during normal operations, this register is to be used as a read only register. this regis- ter should be setup at initialization time. the size of the dram queue storage which is formed with the lower and upper bounds is constrained in its size. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. note that if the max- imum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available.
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 260 of 676 pnr25.chapt04.01 august 14, 2000 bit(s) description 3-0 encoded value number of 32 bit words number of indexes x ? 0 ? 816 x ? 1 ? 16 32 x ? 2 ? 32 64 x ? 3 ? 64 128 x ? 4 ? 128 256 x ? 5 ? 256 512 x ? 6 ? 512 1024 x ? 7 ? 1024 2048 x ? 8 ? 2048 4096 x ? 9 ? 4096 8192 x ? a ? 8192 16384 x ? b ? 16384 32768 x ? c ? 32768 65536 x ? d ? 65536 131072 x ? e ? 65536 131072 x ? f ? 65536 131072
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 261 of 676 9.10: pools pointer queues length registers the pools pointer queues length registers indicates the length of the queue. the bits are a 16-bit count. a primitive that adds to the queue increments this counter. primitives that remove items from the queue dec- rement this counter. 9.11: pools interrupt enable register this register is used to enable bits from the pools status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit(s) in the pools status register are set, the pools interrupt to pcint will be enabled. see note on set/clear type registers on page 93 for more details on addressing. see pools status regis- ter on page 265 for the bit descriptions. length 16 bits type read/write address buffer size 0 xxxx 3064 buffer size 1 xxxx 3068 buffer size 2 xxxx 306c buffer size 3 xxxx 3070 virtual packets / buffer size 4 xxxx 3074 power on value x ? 00 00 ? restrictions during normal operations, this register is to be used as a read only register. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. this register is cleared when the pools pointer queues dram lower bound address register is written to. length 32 bits type clear/set address xxxx 3078 and 07c power on value x ? 00 03 f8 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 262 of 676 pnr25.chapt04.01 august 14, 2000 9.12: pools event enables this register is used to enable an event based on bits from the corresponding primitive transaction. if the bits are set in the enable and a transaction occurs that matches the event, an event will be sent to the rxque. see note on set/clear type registers on page 93 for more details on addressing. 9.13: pools event hysteresis register the pools event hysteresis register provide the capability for hysteresis on threshold checking. length 16 bits type clear/set address gtd event enables x xxx 3a00 and a04 total event enables xxxx 3a08 and a0c user event enables x xxx 3a10 and a14 power on value x ? 0000 ? restrictions none length 8 bits type read/write address xxxx 3a18 power on reset value x ? 0000 ? restrictions none hysteresis value 76543210 bit(s) function description 7-0 hysteresis value when a free occurs, the value in this register is added to the next active packet count. this value will be then tested against the threshold value. if it is equal to the threshold, an event will be issued if events are enabled and the event associated with this transaction is enabled.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 263 of 676 9.14: pools event data register the pools event data register provides the data that was sent on the last event. length 32 bits type read address xxxx 3a1c power on reset value x ? 0000003e ? restrictions none free processed gtd threshold match with hysteresis free processed total threshold match with hysteresis free processed user threshold match with hysteresis get processed gtd threshold match get processed total threshold match get processed user threshold match reserved pool id of the event reserved buffer size of the event reserved event source id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 free processed gtd threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 30 free processed total threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 29 free processed user threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 28 get processed gtd threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 27 get processed total threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 26 get processed user threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 25-20 reserved reserved
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 264 of 676 pnr25.chapt04.01 august 14, 2000 19-16 pool id of the event this indicates which pool is associated with this event. 15-11 reserved reserved 10-8 buffer size of the event this indicates which size is associated with this event. 7-6 reserved reserved 5-0 event source id this indicates that pools is associated with this event. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 265 of 676 9.15: pools status register the pools status register provides status information about pools operations. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 3080 and 084 power on reset value x ? 00 00 00 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved pools event issued packet memory access timer expired control memory access timer expired pools locked initialization error detected unused buffer freed error bad map detected active count error detected bad index detected pointer common buffers size 4 exhausted common buffers size 3 exhausted common buffers size 2 exhausted common buffers size 1 exhausted common buffers size 0 exhausted buffer size 4 threshold crossed buffer size 3 threshold crossed buffer size 2 threshold crossed buffer size 1 threshold crossed buffer size 0 threshold crossed get pointer primitive failed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-21 reserved reserved 20 pools event issued this bit is set when a pools event is issued. 19 packet memory access timer expired this bit is set when the packet memory access timer hits the packet memory access threshold and the control bit in the control register is set to enable this func- tion. 18 control memory access timer expired this bit is set when the control memory access timer hits the control memory access threshold and the control bit in the control register is set to enable this func- tion. 17 pools locked this bit is set when a lock enable bit is set and the corresponding status bit is set. this causes all state machines to be held in idle once this bit is set. it is the func- tional equivalent to pools control register bit 0. 16 initialization error detected this bit is set when too many indexes are freed to a queue. 15 unused buffer freed error this bit is set when a previously freed buffer is detected during a free operation. this typically would occur when the buffer was freed two or more times. 14 bad map detected this bit is set when a bad map is detected during a free operation. 13 active count error detected this bit is set when an active packet count is decremented from ? 0 ? to x ? ffff ? . this is most likely the result of a subtle map corruption where a pool id has been changed. 12 bad index detected this bit is set when an index threshold is crossed.
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 266 of 676 pnr25.chapt04.01 august 14, 2000 11 free pointer primitive null detected/max pointer queue length exceeded. this bit is set as a result of one of two detectable errors: null index detected within free address. total allowed storage for a particular queue has been exceeded. 10 common buffers size 4 exhausted common buffer count for size 4 is zero. 9 common buffers size 3 exhausted common buffer count for size 3 is zero. 8 common buffers size 2 exhausted common buffer count for size 2 is zero. 7 common buffers size 1 exhausted common buffer count for size 1 is zero. 6 common buffers size 0 exhausted common buffer count for size 0 is zero. 5 buffer size 4 threshold crossed the number of size 4 buffers is equal to or less than the threshold that was set for size 4 buffers. 4 buffer size 3 threshold crossed the number of size 3 buffers is equal to or less than the threshold that was set for size 3 buffers. 3 buffer size 2 threshold crossed the number of size 2 buffers is equal to or less than the threshold that was set for size 2 buffers. 2 buffer size 1 threshold crossed the number of size 1 buffers is equal to or less than the threshold that was set for size 1 buffers. 1 buffer size 0 threshold crossed the number of size 0 buffers is equal to or less than the threshold that was set for size 0 buffers. 0 get pointer primitive failed this bit is set when a null address is returned on a get. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 267 of 676 9.16: pools control register the pools control register provide status information about pools operations. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 30c8 and 0cc power on reset value x ? 00 00 20 01 ? restrictions caution must be used when asserting some of the bits during operation. reserved use compressed virtual maps primitive trap source selector lock pools on error packet high priority on get or free fifos full packet high priority always control high priority always packet high priority with request timer control high priority with request timer fast free mode initialization mode virtual memory mode limit event generation enable event interface enable out of range index checking force all queue transactions to memory diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-19 reserved reserved 18 use compressed virtual maps this bit selects compressed virtual maps when set. 17-14 primitive trap source selector these bits will select the source of the last primitive trapped register. 0000 free from the pci bus 0001 free from raall 0010 free from rxque 0011 free from csked 0100 free from segbf 0101 free from dmaqs 0110 get from pci bus 0111 get from reasm 1(ra) 1000 get from dmaqs 1001 get from vimem (pool id (4 bits)), size (2 bits), blank (10 bits), index (16 bits)) ? 1010 ? get from reasm 0(rc) ? 1010 ? last get processed (buffer addr:(31-4)), source (3-0) see above) ? 1011 ? last free accepted (buffer addr:(31-4)), source (3-0) see above) ? 1100 ? last primitive processed (buffer addr:(31-4)), source (3-0) see above) ? 1101 ? last free processed
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 268 of 676 pnr25.chapt04.01 august 14, 2000 13 lock pools on error when set, this bit in conjunction with the lock mask will hold pools state machines in an idle state until cleared. 12 packet high priority on get or free fifos full when set, this bit causes pools to turn on its high priority request to packet memory when either the free or get fifo is full. 11 packet high priority always when set, this bit causes pools to always use its high priority request to packet mem- ory. 10 control high priority always when set, this bit causes pools to always use its high priority request to control mem- ory. 9 packet high priority with request timer when set, this bit causes pools to time the wait for packet memory service and when the timer expires move to high priority. 8 control high priority with request timer when set, this bit causes pools to time the wait for control memory service and when the timer expires move to high priority. 7 fast free mode when this bit is set, fast free mode is enabled. when pools is in fast free mode it does not write out the buffer map with the modified control information that indicates that the map is unused. when in this mode unused buffer free error checking is dis- abled. 6 initialization mode when the value of the bit is ? 0 ? , initialization mode is set. when the value is ? 1 ? , opera- tional mode is set. during initialization mode indexes are in the upper 16 bits of the data word. it is assumed that when initialization mode is on other normal operations are not active such as transmit or receive. during operational mode packet addresses assumed to be on the data bus. 5 virtual memory mode when set to ? 0 ? , virtual memory mode is enabled. when set to ? 1 ? , real memory mode is enabled. 4 limit event generation when set, this bit causes pools to limit the issuance of events to rxque when a gtd threshold, total threshold or pool threshold is reached. it will issue the first event and disable the related event enable bit. software must then reset the bit if it wishes to see another such event. however, it is possible that events may be lost when this bit is set on. 3 enable event interface when set, this bit causes pools to issue resource events to rxque when a gtd threshold, total threshold or pool threshold is reached. 2 enable out of range index checking when set, this bit causes pools to check the indexes that are streaming by to be checked against a maximum value for that size index. if the normal initialization sequence is used, these maximum values will auto set. 1 force all queue transactions to memory when set, this bit disables the internal tail to head transfer path within the queue. all indexes will proceed into memory before being brought to the head of the queue. this effectively preserves the operational history in memory. however, some caution is warranted since four full entries are required for a write to memory. this could cause indexes to get "stuck" at the back of the queue. when this residue occurs, a zero pointer is returned even though the operation might have otherwise returned a valid pointer. 0 diagnostic mode when set, pools is in diagnostic mode. when cleared, pools is in normal mode. when in diagnostic mode, state machines are held in idle. if they are already active, when they next go to idle they will hold there. bit(s) function description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 269 of 676 9.17: pools buffer threshold registers 0-4 the pools buffer threshold registers 0-4 is the threshold set by the software to set the threshold crossed bit in the pools status register. this register is used to compare with the queue length register. this register consists of a 16-bit count match. the threshold count is compared to the queue length count. if the queue length is less than the value in this register, the appropriate bit is set in the status register respec- tive to this queue. 9.18: pools index threshold registers 0-4 the pools index threshold registers 0-4 provide error checking. these are the thresholds set by the soft- ware or hardware to set the index threshold crossed bit in the pools status register. this register is used to check indexes during free operations to look for an out of bounds index. each register consists of a 16-bit compare value. the threshold count is compared to the index while being processed. if an index is greater than the value in this register, the appropriate bit is set in the status register. length 16 bits type read/write address buffer size 0 xxxx 3088 buffer size 1 xxxx 308c buffer size 2 xxxx 3090 buffer size 3 xxxx 3094 virtual packets/ buffer size 4 xxxx 3098 power on value x ? 0000 ? restrictions none length 16 bits type read/write address buffer size 0 xxxx 30f0 buffer size 1 xxxx 30f4 buffer size 2 xxxx 30f8 buffer size 3 xxxx 30fc virtual packets/ buffer size 4 xxxx 3100 power on value x ? 0000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 270 of 676 pnr25.chapt04.01 august 14, 2000 9.19: pools last primitive trap register the pools last primitive trap register provide debug assistance. it contains the 32-bit last primitive address, and it is the last primitive address to pools, as selected in the pools control register, while in operational mode. 9.20: pools last buffer map read on free register the pools last buffer map read on free register provide debug assistance. it contains the 32-bit address of the buffer map used in the last free operation, and it is the address of the last buffer map read on a free. 9.21: pools error lock enable register the pools error lock enable register provides the ability to halt pools when the corresponding status bit in the status register are set. when a bit in this register that corresponds to a bit that is set in the status register, the state machines in pools will be held in idle state until the lock is disabled. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read address xxxx 30e8 power on reset values x ? 00 00 00 00 ? restrictions none length 32 bits type read address xxxx 30ec power on reset values x ? 00 00 00 00 ? restrictions none length 21 bits type clear/set address xxxx 30d8 and dc power on reset value x ? 00 f8 00 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt04.01 august 14, 2000 buffer pool management (pools) page 271 of 676 9.22: pools packet and control memory access threshold the pools packet and control memory access threshold timers are used to help limit the amount of time that pools can be held off from its respective memory. the bits are a 12-bit count. when the proper bit in the pools control register is set and a request is made to the requisite memory, a counter is loaded with this value. the counter will then count down to zero in 30 ns ticks. when it hits zero, it forces the request to high priority. 9.23: pools buffer map group the pools buffer map group holds the buffer map of the packet that is in the process of being freed. from this map, the pool id and the indexes that have been used are returned to their correct queue. this register consists of a 16-bit flag field and 16-bit indexes. the flag field contains the pool id and the valid bit. when a packet is freed, the valid bit is set to ? 0 ? . when a get operation occurs, the valid bit is then set. this helps to find address duplicates and other address related problems that software can generate. length 12 bits type read/write address packet memory timer threshold xxxx 30e4 control memory timer threshold xxxx 30e0 power on reset value x'080' restrictions none length 32 bits type read/write address upper 16 bits: lower 16 bits: flag field 0 index 0 xxxx 309c index 1 index2 xxxx 30a0 flag field 1 index 3 xxxx 30a4 index 4 index 5 xxxx 30a8 flag field 2 index 6 xxxx 30ac index 7 index 8 xxxx 30b0 flag field 3 index 9 xxxx 30b4 index 10 index 11 xxxx 30b8 flag field 4 index 12 xxxx 30bc index 13 index 14 xxxx 30c0 power on reset value x'ffffffff' restrictions none
IBM3206K0424 ibm processor for network resources preliminary buffer pool management (pools) page 272 of 676 pnr25.chapt04.01 august 14, 2000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 273 of 676 transmit data path entities entity 10: transmit buffer (csked) the transmit cell scheduler entity is responsible for receiving a packet from the processor, determining when cells from the packets need to be transmitted, and passing this information to the segmentation buffer entity. the logic consists of timers and counters for determining transmit opportunities and interfaces to arbit (for accessing the timing data and descriptors), pcint (for register accesses), rxque (for queuing events), pools (for returning buffers when finished transmitting), and segbf (for getting the data from memory to transmit). scheduling overview this entity provides traffic shaping to ensure that traffic sent by the IBM3206K0424 conforms to the quality of service (qos) parameters as defined by the atm forum. csked provides support for the following qos parameters: peak cell rate (pcr) - the maximum number of cells per second that the connection can transfer into the network. sustained cell rate (scr) - the average number of cells per second that the connection can transfer into the network. the burst tolerance determines the length of time over which the network measures this average. burst tolerance - the maximum length of time that the user can transfer at the peak cell rate. burst toler- ance can be measured in number of cells, a measurement known as maximum burst size (mbs). csked will send out cells at the scr. if transmit opportunities are missed, as is the case when there is no data to send, the actual rate will become less than scr. when data becomes available to send, c sked will transmit up to mbs cells at the pcr, until the transmit rate returns to scr.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 274 of 676 pnr25.chapt05.01 august 14, 2000 operational description lcd initialization a logical channel data structure (lcd) containing scheduling parameters for the circuit must be initialized before segmentation can be started. the parameters that are important to the operation of this entity are: see transmit logical channel descriptor data structures on page 66 for further information. a scheduling example if a connection is to have an scr of 50 mbps and a pcr at the line rate of 150 mbps and a mbs of 10 cells, the lcd needs to be initialized as follows: average_interval = 150 mbps/50 mbps = 3 peak_interval = 150 mbps/150 mbps = 1 max_burst_value = 10*(3-1) = 20 the following example uses a timeline to show how a connection with these parameters is scheduled. cells are sent every third slot while there is data to send. after the first two cells are sent there is no more data to average_interval this field contains the minimum average spacing allowed between cells transmitted on this connection. it is the reciprocal of the sustainable cell rate (scr), as speci- fied in the atm forum traffic management specification. the value for this field is expressed in slot times. the length of time for a slot is defined by the timeslot prescaler register and should normally be set to one cell time. peak_interval this field contains the minimum spacing allowed between consecutive cells on this connection. it is the reciprocal of the peak cell rate as specified in the atm forum traffic management specification. this spacing is also expressed in slot times. a connection that can transmit every slot time would have a value of ? 1 ? for this field. max_burst_value and max_burst_mult the values in these fields are used to limit the number of cells that can be trans- ferred at the peak rate. the max_burst_value will be multiplied by four to the power of the max_burst_mult to yield the maximum credit time. this time is expressed in slot times and represents the time it would take to acquire the maximum number of cell credits. this maximum credit time should equal the average interval minus the peak interval, multiplied by the maximum number of cells (mbs) that can be trans- ferred at the peak rate. transmit_priority this field specifies the priority of transmission on this connection. three levels of priority are available. connections needing the highest quality of service, such as a cbr connection, should use the highest priority. connections with the lowest quality of service requirements, such as a ubr connection, should use the lowest priority. drop data can be sent on up to four physical drops. this field specifies the drop for this connection. max_resolution if this bit is set, the lower eight bits of the average interval and peak interval param- eters contain a fractional component. this allows a finer resolution for scheduling. for example, for a peak interval of 1.5 time units, the value written to the peak_interval field should be hex 0180. if this bit is set, the initial value of time- stamp should contain the current timeslot counter shifted 16 bits to the left.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 275 of 676 send until another packet is enqueued. for each missed transmit opportunity, a cell can be sent at the peak interval, which is one. in the 15 timeslots after the first cell, five cells are sent for an scr of 50 mbps. the burst size is three, which is less than mbs. the unfilled slots can be used by other connections. csked initialization before packets are enqueued for transmission, in addition to initializing the above scheduling parameters in the lcd, the following registers need to be set up. timeslot prescaler register - the amount of time for one timeslot is defined by this register. it defaults to 707 ns which is one cell time on a 622 mbps sonet interface. csked control register - additional scheduling options such as number of physical drops needs to be set in this register. timeline example of scheduling e s |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|-> time |---| represents 1 time slot (the time it takes to send one cell). s represents a cell being sent. t represents a transmit opportunity at scr. e represents a packet enqueue. ss s s s ttttt t
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 276 of 676 pnr25.chapt05.01 august 14, 2000 packet initialization packets to be segmented are written to packet memory, which has been allocated by pools. the address of the lcd describing the channel that this packet is to be transmitted on must be written to the header of the packet. packet segmentation is started by issuing the transmit enqueue primitive to this entity. this entity will schedule segmentation of the packet according to the parameters set up in the lcd. scheduling options abr scheduling csked has logic to assist in the processing of abr connections. if the connection is abr, the lcd will have a different configuration, as specified in transmit logical channel descriptor data structures on page 66. the following fields need to be initialized before the packets are sent on the connection. scheduling type - this field must be set to the value specifying an abr connection. nrm - this field should specify the maximum number of cells a source may send for each forward rm-cell. number of cells = (2 ?? nrm)+1. trm - this field provides an upper bound on the time between forward rm-cells for an active source. time = 100 ? (2 ?? -trm) msec. adtf - the acr decrease time factor is the time permitted between sending rm-cells before the rate is decreased to icr. time = adtf ? 0 .01 msec. all other abr fields should be initialized to ? 0 ? . frame scheduling csked has logic to support frame-based scheduling. it is enabled whenever the phy type is configured for pos-phy in linkc. in frame-based scheduling the packet is sent out at the line rate, but the start time of the next frame is determined by multiplying the peak interval by the number of 64-byte blocks in the packet. the average portion of the bandwidth used by a connection will be 1/(peak interval). for example, if a connection is to use 1/4 of the bandwidth, the peak interval should be set to four. the frames will be sent out at line rate, but the spacing between the start of each frame will be four timeslots for each cell sent from the packet, so on average 1/4 of the bandwidth will be used by the connection. the follow- ing timeline example depicts sending two packets, the first contains four cells and the second contains three cells. the unfilled slots can be used by other connections.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 277 of 676 the above example assumes that one slot time is initialized to the time it takes to send 64 bytes out on the line. the term "cells" was used in this example to mean a 64-byte block of packet data. in frame mode, the atm header is not prepended to the data being sent. weighted fair queueing on a frame basis is supported on the low priority queue by setting bit 17 in the csked control register. when using frame-based scheduling and weighted fair queuing together, the average inter- val will be used to limit the spacing between packets, not cells. path scheduling csked has logic to support sharing scheduling parameters between multiple connections. in path schedul- ing, an lpd is set up to contain the scheduling parameters for the group of connections in the same way it is done for lcds. all connections that wish to share this bandwidth set the alter_sched field in their lcd to indicate this vc is on a vp, and initialize the lpd_pointer field to point to the lpd. the segmentation portion of the lpd is not used since the segmentation parameters are taken from the lcd. the scheduling parameters in the lcds are not used as they are in the lpd. the bandwidth is shared on a packet or cell basis depending the value of the alter_sched field in the lcd. since both the lpd and lcd need to be fetched for each trans- mit opportunity, this scheduling method should not be used where the performance boundaries are being pushed, as in 622 mbps. see transmit logical channel descriptor data structures on page 66 for further information on lpd descriptors. primitives enqueue after a packet has been written to memory and the packet header updated with the offset and length of the data and the lcd address of the connection, an enqueue primitive needs to be issued to the transmit enqueue primitive address. close connection when no more traffic is to be sent on a connection, this primitive can be executed to cause an event to be generated when segmentation has stopped on this connection. segmentation will be stopped immediately, or stopped after all packets on this connection have been transmitted as specified in the csked control regis- ter. timeline example of frame scheduling 4 cells 3 cells x 4 slots/cell x 4 slots/cell = 16 timeslots = 12 timeslots |<----------------------------->|<--------------------->| s s s s s s s s ... |-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|->time |-| represents 1 time slot (the time it take to send 1 cell). s represents a cell being sent.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 278 of 676 pnr25.chapt05.01 august 14, 2000 start/stop timer when this primitive is executed, a timer is started or stopped whose parameters are contained in the speci- fied lcd. when the timer pops, a dma descriptor specified in the lcd will be executed. 10.1: transmit enqueue primitive enqueues a buffer for transmission. 10.2: resume transmission primitive resumes transmission on an abr connection that has been suspended. on an abr connection, adtf, crm, and ccr=0 events will cause the transmission to be suspended until a rate conversion is completed, normally by the internal processor. this primitive will resume transmission on those connections, once the rate conversion is completed. length: 32 bits type write only address xxxx 1200 power on value x ? 0000 0000 ? restrictions none transmitted buffer address ignored 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 this must contain the address of the buffer to be transmitted. buffers must be aligned on at least 64 byte boundaries. the lower six bits are ignored. 5-0 ignored length 32 bits type read/write address xxxx 1204 power on value x ? 0000 0000 ? restrictions this address should be written with care. this primitive should only be used on connections that have been suspended. resume lcd address ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 this must contain the address of the lcd that is to resume transmission. the lower seven bits are ignored. 6-0 ignored
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 279 of 676 10.3: start/stop timer primitive start or stop a timer with the parameters in the specified lcd address. when this primitive is executed, a timer is started or stopped whose parameters are contained in the specified lcd. bit 0 specifies whether to start (0) or stop (1) the timer. when the timer pops, a dma descriptor specified in the lcd will be executed. 10.4: close connection primitive transmission is complete on a connection specified by an lcd address. when no more traffic is to be sent on a connection, this primitive can be executed to cause an event to be generated when segmentation has stopped on this connection. segmentation will be stopped immediately, or stopped after all packets on this connection have been transmitted, as specified in the csked control register. length: 32 bits type: read/write address: xxxx 1208 power on value: x ? 0000 0000 ? restrictions: none start/stop timer reserved start - stop 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 this must contain the address of the lcd that contains the timer parameters. 6-1 reserved. 0 this bit specifies whether the timer is to be started (0) or stopped (1). length 32 bits type read/write address xxxx 120c power on value x ? 0000 0000 ? restrictions none close lcd address reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 this must contain the address of the lcd that is to be closed. the lower seven bits are ignored. 6-0 reserved.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 280 of 676 pnr25.chapt05.01 august 14, 2000 10.5: timeslot prescaler register this register determines the length of time for one timeslot. this controls the rate that the cell scheduling counters are incremented. each clock cycle, the value in this register is added to a 24-bit counter. when the upper bit of the counter changes state, the current timeslot counter is incremented. this should normally be set to the time it takes to transmit one cell. it will be initialized to the cell time for a 622 mb/s sonet connec- tion (599.04 mb/s payload). the following formula should be used to determine the value to load in this regis- ter: timeslot prescaler = (clock interval/timeslot interval) x 2 ?? 23. 10.6: current timeslot counter this counter contains a count of how many prescaled intervals have elapsed. it is used to determine if sched- uling needs to be done or credits exist. length 24 bits type read/write address xxxx 1210 power on value x ? 02b67c ? restrictions this register should be written only at initialization time. timeslot counter rate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 23-0 this value will determine the rate at which the current timeslot counter is advanced. length 32 bits type read/write address xxxx 1218 power on value x ? 0000 0000 ? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. elapsed interval count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents how many expirations have occurred since the counter rolled over.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 281 of 676 10.7: csked control register this register is used to control the actions of csked. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write address xxxx 1220 and 224 power on value x ? 0759 ? restrictions none reserved disable preflushing txlcd cache reserved disable overlapping transmit requests close connection immediately queue lcd-based memory management events lcd-based memory management use weighted fair queueing for low priority reserved reserved queue lcd address disable virtual buffer error detection disable queuing virtual buffer errors flush transmit lcd cache segbf queue length threshold disable segbf queue length buffer request priority enable timers reschedule packets enable high priority traffic enable medium priority traffic enable low priority traffic enable cell scheduling 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-28 reserved reserved 27 disable preflushing txlcd cache this bit disables automatically, flushing a cache line when all lines are dirty 26-22 reserved reserved 21 disable overlapping transmit requests this bit is meant for debug purposes only. it will disable the ability of csked to overlap requests to segbf. 20 close connection immediately setting this bit will cause segmentation to stop immediately on any connection that has been issued a close connection primitive. if this bit is not set, an event will be gener- ated after all traffic queued to this connection has been sent. 19 queue lcd-based memory man- agement events setting this bit will cause lcd-based memory management events to be queued to the transmit complete queue, if enabled by bit 18 of this control register. if lcd-based memory management is enabled and this bit is off, the receive pool id associated with this connection will be updated when a threshold is crossed. 18 lcd-based memory management setting this bit will enable lcd-based memory management for received packets. see definition of lcd-based memory management of transmit lcd on page 73 for further information on this function.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 282 of 676 pnr25.chapt05.01 august 14, 2000 17 use weighted fair queueing for low priority setting this bit will cause low priority traffic to be scheduled using weighted fair queue- ing. the peak interval in the lcd is used to provide a relative weight in determining the amount of bandwidth the connection will use. for example, a peak interval of one will use twice the bandwidth as a connection with a peak interval of two. the average inter- val specifies the maximum rate that the connection can use. for example if the aver- age interval is set to two, the maximum rate at which it can send a cell is every two timeslot times (as defined in the timeslot prescaler register). 16 reserved reserved. 15 reserved reserved. 14 queue the lcd address if freeing and queueing setting this bit will cause the lcd address, instead of the packet address, to be queued if both freeing and queueing on transmit are complete. 13 disable virtual buffer error detec- tion setting this bit will cause the buffer enqueue logic to ignore virtual buffer errors. 12 disable queuing virtual buffer errors if virtual buffer error detection is not disabled, detected errors will be queued. if this bit is set, this queueing is disabled and the buffer will be freed. 11 flush transmit lcd cache if this bit is set, the transmit lcd cache will be flushed. this bit will be reset after the cache has been flushed. flushing the cache should not be needed in normal opera- tion. 10-8 segbf queue length threshold cells can be queued in segbf up to the number specified in this register. the default is seven, which is above the limit for pass two. writing these bits to ? 0 ? will also disable this function. 7 disable segbf queue length in scheduling csked will normally include segbfs queue length in the calculations when resched- uling a cell. if this bit is on it will disable this function and the cell will be scheduled as if the cells were transferred when segbf accepted the cells. 6 priority of buffer requests if this bit is not set, scheduling requests have a higher priority than buffer requests. if this bit is set this priority is reversed. it should be set if a significant percentage of pack- ets are only a few cells in length. 5 enable timers timer descriptors can be enqueued to this entity that will cause a dma descriptor to be executed on expiration. if these timers are used, this bit must be set. if they are not used, this bit should be reset. 4 reschedule packets in the slow queue to the fast queue this function is not implemented in pass one. it is implemented in pass two. if the average or peak interval is greater than 255, the cells will be scheduled in the slow queue. the slow queues will be serviced every 64 pre-scaler time units. this means that a jitter of up to 64 pre-scaler time units should be expected for slow traffic. if this bit is set, packets in the slow queue will be rescheduled at the appropriate time to the fast queue. this will decrease the variation in the scheduling but may cause some performance degradation if traffic is heavy. 3 enable high priority traffic for each priority enabled 16kb of control memory must be reserved for timing data. if only one or two priorities are to be used, bits corresponding to unused priorities should be cleared to improve performance. 2 enable medium priority traffic enable medium priority traffic. 1 enable low priority traffic enable low priority traffic. 0 enable cell scheduling if this bit is off, no primitives will be handled or cells scheduled. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 283 of 676 10.8: transmit segmentation throttle register this register contains the number of cycles to wait between successive requests to transmit a cell. its purpose is to slow segmentation on all vcis if it is determined by software that the network can not handle the generated load. the value in this register will be loaded into the transmit segmentation counter each time a cell is accepted for transmission. for normal operation the value in this register should be ? 0 ? . length 16 bits type read/write address xxxx 1230 power on value x ? 0000 ? restrictions none queue length 1514131211109876543210 bit(s) description 15-0 when the transmit complete queue length reaches this value an interrupt will be generated.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 284 of 676 pnr25.chapt05.01 august 14, 2000 10.9: transmit segmentation throttle counter this register is loaded with the value in the transmit segmentation throttle register after each cell is accepted for transmission and counts down until it reaches ? 0 ? . a new cell transmission will not be requested until this counter reaches ? 0 ? . 10.10: mpeg conversion register this register is used to convert mpeg time units into timeslot time units. if mpeg traffic is configured in the lcd, the data stream will be monitored for pcrs. if a pcr is detected, it will be scheduled at the time speci- fied in the pcr. a conversion factor needs to be written into this register to convert the mpeg time units into timeslot units. it will be initialized to a value that converts the mpeg time units (90 khz) into the timeslot units (353.2 khz, assuming one timeslot is the time it takes to send one cell over a sonet connection). the lower 12 bits of this register contain the fractional portion of this conversion factor. example: 353.2076 khz / 90 khz = 3.924528 = 3.ecb hex length 16 bits type read only address xxxx 1234 power on value x ? 0000 ? restrictions read only transmit segmentation throttle counter 1514131211109876543210 bit(s) description 15-0 when this counter reaches ? 0 ? , a new cell can be transmitted. length 15 bits type read/write address xxxx 125c power on value x ? 3ecb ? restrictions none mpeg time conversion factor 14131211109876543210 bit(s) description 14-0 contains the conversion factor.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 285 of 676 10.11: abr timer prescaler register this register determines the length of time for a tick of the rm cell timer. this controls the rate that the cell scheduling counters are incremented. each clock cycle, the value in this register is added to a 24-bit counter. when the upper bit of the counter changes state, the rm cell timer is incremented. this should be set to value of 0.78 ms. it will be initialized to 0.78 ms assuming a 30-ns clock (as set up in sclock). the following formula should be used to determine the value to load in this register: abr timer prescaler = (clock interval/0.78 ms) x 2 ?? 23. 10.12: rm cell timer this register is used to keep track of the last time that an abr rm cell was sent. its period should be 0.78 ms. length 24 bits type read/write address xxxx 127c power on value x ? 0000a2 ? restrictions this register should be written only at initialization time. abr counter rate 23222120191817161514131211109876543210 bit(s) description 23-0 this value will determine the rate at which the abr counter is advanced. length 24 bits type read/write address xxxx 126c power on value x ? 000000 ? restrictions none rm timer value 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 23-0 timer value.
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 286 of 676 pnr25.chapt05.01 august 14, 2000 10.13: csked lcd update data registers used to specify data to write into the lcd on the update lc operation. these registers contain the data used in the lc update operation. for more information on its use, see the csked lcd update operation regis- ters on page 287. this register changes to contain the updated data written to the lc word while the operation is completing. the second set of lcd update registers is meant for the core to use, but is available for general use. 10.14: csked lcd update mask registers used to specify data to write into the lcd on the update lc operation. these registers contain the mask used in the lc update operation. for more information on its use, see the csked lcd update operation regis- ters on page 287. the second set of lcd update registers is meant for the core to use, but is available for general use. length 32 bits type read/write address update1 xxxx 1300 update2 xxxx 130c power on value x ? 000000 ? restrictions none length 32 bits type read/write address update1 xxxx 1304 update2 xxxx 1310 power on value x ? 000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 transmit buffer (csked) page 287 of 676 10.15: csked lcd update operation registers used to specify the lcd word to update. this operation is used to update a portion of an lcd. if this opera- tion is not used, software or IBM3206K0424 updates of the lcd may be lost because the lcd is cached in IBM3206K0424 while cells are being processed. this register is written with the address of the lcd word to update. once this register is written the update operation starts. all subsequent reads or writes to the data, mask, or update registers are held off until the operation completes. a read-modify-write will occur to update the portion specified by the mask with the masked value in the data register. normally this register would not be read. however, if it is read then the low order bit is read as ? 0 ? and the next lowest order bit (bit 1) is read as the busy bit. this signifies whether an operation is still going on. if an opera- tion is still going on, then a new write to any of the data, mask, or update operation registers is held off until the original operation is complete. the second set of lcd update registers is meant for the core to use, but is available for general use. length 32 bits type read/write address update1 xxxx 1308 update2 xxxx 1314 power on value x ? 000000 ? restrictions the low order two bits are not writable
IBM3206K0424 ibm processor for network resources preliminary transmit buffer (csked) page 288 of 676 pnr25.chapt05.01 august 14, 2000 10.16: drop access control register each drop(4) has registers that can be used for debugging purposes and bandwidth limiting. to conserve address space, this register determines the drop for the register access. these registers are fast serviced counters, slow serviced counters, and priority bandwidth limit registers. this register must be rewritten whenever values for a different drop need to be read or written. length 2 bits type read/write address xxxx 1288 power on value x ? 00000000 ? restrictions none drop 10 bit(s) description 1-0 this value represents the drop number or the above registers that will be accessed.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 performance registers page 289 of 676 performance registers this section contains registers that are for performance purposes. 10.17: high priority bandwidth limit register this register can be used to limit the bandwidth used by high priority connections. the upper eight bits of this register specifies the number of high priority cells that can be sent in a window specified by the lower eight bits of this register. if no data needs to be sent by lower priority connections, high priority connections will not be limited. length 16 bits type read/write address xxxx 1270 power on value x ? 00000000 ? restrictions none cells transmitted cell times in window 1514131211109876543210 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from high priority connections in one time window. 7-0 this value specifies the number of cell times in the window.
IBM3206K0424 ibm processor for network resources preliminary performance registers page 290 of 676 pnr25.chapt05.01 august 14, 2000 10.18: medium priority bandwidth limit register this register can be used to limit the bandwidth used by medium priority connections. the upper eight bits of this register specify the number of medium priority cells that can be sent in a window specified by the lower eight bits of this register. if no data needs to be sent by low priority connections, medium priority connections will not be limited. 10.19: low priority bandwidth limit register this register can be used to limit the bandwidth used by low priority connections. the upper eight bits of this register specify the number of low priority cells that can be sent in a window specified by the lower eight bits of this register. length 16 bits type read/write address xxxx 1274 power on value x ? 00000000 ? restrictions none cells transmitted cell times in window 1514131211109876543210 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from medium priority connections in one time window. 7-0 this value specifies the number of cell times in the window. length 16 bits type read/write address xxxx 1278 power on value x ? 00000000 ? restrictions none cells transmitted cell times in window 1514131211109876543210 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from low priority connections in one time window. 7-0 this value specifies the number of cell times in the window.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 performance registers page 291 of 676 10.20: high priority cells transmitted counter this register contains the number of cells transmitted from high priority connections. 10.21: medium priority cells transmitted counter this register contains the number of cells transmitted from medium priority connections. length 32 bits type read/write address xxxx 1260 power on value x ? 00000000 ? restrictions none number of high priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from high priority connections. length 32 bits type read/write address xxxx 1264 power on value x ? 00000000 ? restrictions none number of medium priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from medium priority connections.
IBM3206K0424 ibm processor for network resources preliminary performance registers page 292 of 676 pnr25.chapt05.01 august 14, 2000 10.22: low priority cells transmitted counter this register contains the number of cells transmitted from low priority connections. length 32 bits type read/write address xxxx 1268 power on value x ? 00000000 ? restrictions none number of low priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from low priority connections.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 performance registers page 293 of 676 10.23: bytes queued counters these registers (12) contain the number of bytes queued for transmission for each priority (3) on each drop (4). the addresses are assigned to the range in the following order: high priority port 0 high priority port 1 high priority port 2 high priority port 3 medium priority port 0 medium priority port 1 medium priority port 2 medium priority port 3 low priority port 0 low priority port 1 low priority port 2 low priority port 3 length 32 bits type read/write address xxxx 1290-2bc power on value x ? 00000000 ? restrictions none number of bytes waiting to be transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of bytes waiting to be transmitted for each priority on each drop.
IBM3206K0424 ibm processor for network resources preliminary debugging register access page 294 of 676 pnr25.chapt05.01 august 14, 2000 debugging register access this section contains registers that are for debug purposes only. these registers need not be written or read during normal operations. 10.24: fast serviced counters there are three fast serviced counters, one for each transmit priority: high, medium, and low. these registers contain the value of the last fast time slot that has been serviced. when this count differs from the current timeslot count, at least one fast slot needs servicing. each time the fast slot is serviced, this counter will incre- ment. 10.25: slow serviced counters there are three slow serviced counters, one for each transmit priority: high, medium, and low. these regis- ters contain the value of the last slow time slot that has been serviced. when this count differs from the current timeslot count, at least one slow slot needs servicing. each time the slow slot is serviced, this counter will increment. length 16 bits type read/write address xxxx 1240 xxxx 1244 xxxx 1248 power on value x ? 0000 ? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. fast serviced counters 1514131211109876543210 bit(s) description 15-0 this value represents how many times this time wheel has been serviced since the counter rolled over. length 10 bits type read/write address xxxx 124c xxxx 1250 xxxx 1254 power on value x ? 000 ? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. slow serviced counters 9876543210 bit(s) description 9-0 this value represents how many times this slow wheel has been serviced since the counter rolled over.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 debugging register access page 295 of 676 10.26: timer serviced counters in addition to the counters above, there is an additional counter for processing timer requests. these regis- ters contain the value of the last timer slot that has been serviced. when this count differs from the current timeslot count (bits 22-15), at least one slow slot needs servicing. each time a timer slot is serviced, this counter will increment. length 16 bits type read/write address xxxx 1280 power on value x ? 00 ? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. service count 1514131211109876543210 bit(s) description 15-0 this value represents how many times this timer wheel has been serviced since the counter rolled over.
IBM3206K0424 ibm processor for network resources preliminary debugging register access page 296 of 676 pnr25.chapt05.01 august 14, 2000 10.27: csked status register this register is used to control the actions of csked. see note on set/clear type registers on page 93 for more details on addressing. length 14 bits type clear/set address xxxx 1228 and 22c restrictions none power on value x ? 0 ? virtual memory error detected high priority serviced counter medium priority serviced counter low priority serviced counter high priority serviced counter medium priority serviced counter low priority serviced counter high priority serviced counter medium priority serviced counter low priority serviced counter high priority serviced counter medium priority serviced counter low priority serviced counter current timeslot counter 131211109876543210 bit(s) name description 13 virtual memory error detected if a virtual memory write operation could not complete because a real buffer was not available, a signature is written to the packet header. if this signature is detected when the buffer is enqueued for transmission, this bit will be set and an event will be posted to rxque. 12 high priority serviced counter high priority serviced counter has overrun on drop 3. 11 medium priority serviced counter medium priority serviced counter has overrun on drop 3. 10 low priority serviced counter low priority serviced counter has overrun on drop 3. 9 high priority serviced counter high priority serviced counter has overrun on drop 2. 8 medium priority serviced counter medium priority serviced counter has overrun on drop 2. 7 low priority serviced counter low priority serviced counter has overrun on drop 2. 6 high priority serviced counter high priority serviced counter has overrun on drop 1. 5 medium priority serviced counter medium priority serviced counter has overrun on drop 1. 4 low priority serviced counter low priority serviced counter has overrun on drop 1. 3 high priority serviced counter high priority serviced counter has overrun on drop 0. 2 medium priority serviced counter medium priority serviced counter has overrun on drop 0. 1 low priority serviced counter low priority serviced counter has overrun on drop 0. 0 current timeslot counter current timeslot counter has wrapped. if this bit is on, the timeslot counter has wrapped.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 debugging register access page 297 of 676 10.28: csked interrupt enable register this register is used to enable interrupts from csked. if a bit is on in the status register and the correspond- ing enable bit is on in this register then an interrupt will be generated if enabled in intst. see note on set/clear type registers on page 93 for more details on addressing. 10.29: csked timing data array pointer the csked timing data array contains data relevant to scheduling cells. it contains 96 32-bit words. it should only be written for diagnostic purposes to test the array. it will power up to all zeros and should be rewritten to zeros after the array has been tested. this register points to an offset in the csked timing data array for accesses from the pci bus. this register must be loaded with the correct offset before the desired data can be read from the csked timing data array data register. this register will auto-increment after each access to the associated data register. when the last address is accessed, this register wraps to zero. length 14 bits type clear/set address xxxx 1238 and 23c power on value x ? 0 ? restrictions none enables interrupts 131211109876543210 bit(s) description 13-0 enables interrupts length 9 bits type read/write address xxxx 12c0 power on value x ? 000 ? restrictions none offset into csked not used 876543210 bit(s) description 8-2 these bits provide an offset into the csked cell staging array for accesses from the pci bus. these bits provide access to the 256 unique four-byte locations in the array. accessing the last location in the array will cause the address to wrap back around to the beginning of the array. 1-0 these bits are not implemented. they cannot be written and will always return ? 0 ? when read.
IBM3206K0424 ibm processor for network resources preliminary debugging register access page 298 of 676 pnr25.chapt05.01 august 14, 2000 10.30: csked timing data array data this register is used to access the array pointed to by the csked timing data array pointer. 10.31: csked time wheel array pointer the csked time wheel array contains data relevant to scheduling cells. it contains 16k 19-bit words. it should only be written for diagnostic purposes to test the array. it will power up to all zeros and should be rewritten to zeros after the array has been tested. this register points to an offset in the csked time wheel array for accesses from the pci bus. this register must be loaded with the correct offset before the desired data can be read from the c sked time w heel array data register. this register will auto-increment after each access to the associated data register. when the last address is accessed, this register wraps to zero. length 32 bits type read/write address xxxx 12c4 power on value restrictions should be written for diagnostic use only. initialize back to ? 0 ? s when through testing. access data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 access data length 17 bits type read/write address xxxx 12c8 power on value x ? 000 ? restrictions none offset into csked not used 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 16-2 these bits provide an offset into the csked cell staging array for accesses from the pci bus. these bits provide access to the 16k unique 19-bit locations in the array. accessing the last location in the array will cause the address to wrap back around to the beginning of the array. 1-0 these bits are not implemented, they can not be written and will always return ? 0 ? when read.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 debugging register access page 299 of 676 10.32: csked time wheel array data this register is used to access the array pointed to by the csked time wheel array pointer. 10.33: csked lcd cache array pointer the csked lcd cache array contains the transmit portion of lcds used by csked and segbf. it contains 64 32-bit words. it should only be written for diagnostic purposes to test the array. it will power up to all zeros and should be rewritten to zeros after the array has been tested. this register points to an offset in the lcd cache array for accesses from the pci bus. this register must be loaded with the correct offset before the desired data can be read from the lcd cache array data register. this register will auto-incre- ment after each access to the associated data register. when the last address is accessed, this register wraps to zero. length 19 bits type read/write address xxxx 12cc power on value restrictions should be written for diagnostic use only. initialize back to zeros when through testing. access data 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 18-0 access data length 18 bits type read/write address xxxx 1318 power on value x ? 000 ? restrictions none offset into csked not used 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 17-2 these bits provide an offset into the csked cell staging array for accesses from the pci bus. these bits provide access to the 64 unique 32-bit locations in the array. accessing the last location in the array will cause the address to wrap back around to the beginning of the array. 1-0 these bits are not implemented. they can not be written and will always return ? 0 ? when read.
IBM3206K0424 ibm processor for network resources preliminary debugging register access page 300 of 676 pnr25.chapt05.01 august 14, 2000 10.34: csked lcd cache array data this register is used to access the array pointed to by the csked lcd cache array pointer. 10.35: csked congestion control register csked can halt scheduling on up to 160 groups of connections. a connection specifies which group it belongs to by encoding the qnr(0-39) and dp(0-3) bits in the lcd. this register contains 160 bits which specify which of the 160 groups should be halted. bit xx in the c sked control register must be set in order to write to these bits from software. this register is read in eight groups of 20 bits. the group is specified by bits four through two of the address, with increasing addresses corresponding to increasing group numbers. length 32 bits type read/write address xxxx 131c power on value restrictions should be written for diagnostic use only. initialize back to zeros when through testing. access data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 access data length 28 bits type read/write address xxxx 120f0-2fc power on value x ? 000 ? restrictions none specifies which groups written specifies segmentation will be halted 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 27-20 these bits specify which eight groups of 20 bits will be written when writing this register. from one to all eight groups can be written at the same time, but all will be written with the same data specified in bits 19-0. 19-0 when set, these bits specify that segmentation will be halted for all connections associated with the corresponding group.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 debugging register access page 301 of 676 10.36: state machine variables this register contains the current state of the three main state machines in this entity. length 14 bits type read address xxxx 1258 power on value x ? 0000 ? restrictions none state machine variables 131211109876543210 bit(s) description 13-0 value of state machine variables.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 302 of 676 pnr25.chapt05.01 august 14, 2000 entity 11: atm transmit buffer segmentation (segbf) the segmentation buffer entity (segbf) accepts frames from the cell scheduler (csked) or software, and then generates atm cells to send out over the external physical interface. this entity knows or cares nothing about scheduling cells over time; it will simply construct a cell when it is provided an address of a logical circuit descriptor to operate on. all rate and scheduling concerns must be addressed by the c sked logic or software prior to queueing a frame to segbf. the segbf logic consists of four input lcd address latches, two specialized processors and the associated rom/ram for each, a 16-cell array buffer, and various support logic. the input latches and cell buffers are logically divided into four different drops, with each drop consisting of an input latch and four cell buffers. under normal operation (csked providing lcd), the drop is defined by the drop field in the transmit lcd. when an lcd is enqueued by software, data bits five and six of the enqueued address define which drop the enqueued lcd is associated with. the four logical drops in segbf can be mapped to any of the physical link level addresses via registers in linkc (linkc map transmit ports to configuration). the processors fetch instructions from rom/ram and handle normal segmentation activity such as lcd update operations and cell generation functions. the type of cell that is generated by the segmentation logic is determined by the initial instruction pointer that is contained in the lcd structure. for example, software can enqueue an lcd that has the initial instruction pointer field set for normal aal5 cells, and segbf will generate a single aal5 cell as a result of the enqueue operation. if, however, software enqueues an lcd that has the initial instruc- tion pointer field set for pos-phy operation, then segbf will continue to generate buffers to pass to the link level until all the data has been exhausted. for a more complete description of the segmentation entry points, refer to the seg_prc_entry_point field in the transmit lcd data structure section of this document. after the buffers/cells are built in a 16-by-64 byte array, they are marked as available to the link level layer (linkt) in the IBM3206K0424. a simplified block diagram is shown in the segbf block diagram.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 303 of 676 the sequence of events that happens when an aal5 frame is enqueued to segbf is as follows: 1. an initial check is made to determine if there is space available in the cell buffer. if no space is available, processing stops for this drop until a cell buffer is freed by the link logic (linkt). 2. when buffer space becomes available, the enqueued lcd address is requested from the transmit lcd cache (there are four entries in the lcd cache). the segmentation logic waits for a valid indication from the cache; at this time all lcd information is available to the segmentation logic on the lcd cache inter- face. 3. the initial instruction pointer (ip) is fetched from the lcd and loaded for both of the segmentation proces- sors. software controls what type of cells are generated by the segmentation logic by initializing this field in the lcd to the entry points defined for different types of cell generation. for a more complete descrip- tion of the segmentation entry points, refer to the seg_prc_entry_point field in the transmit lcd data structure section of this document. 4. assuming an aal5 entry point is setup in the lcd, the segmentation logic will first initiate a memory fetch of the data required to build the cell. 5. while the data fetch is in process, the segmentation processors will update various fields in the lcd including statistics and the next segmentation pointer. cell construction will be started using the atm segbf block diagram csked lcd interface software lcd enq interface drop 0 drop 1 drop 2 drop 3 lcd processor cell processor ram ram cell array drop 0 cell 0 drop 0 cell 1 drop 0 cell 2 drop 0 cell 3 drop 1 cell 0 drop 1 cell 1 drop 1 cell 2 drop 1 cell 3 drop 2 cell 0 drop 2 cell 1 drop 2 cell 2 drop 2 cell 3 drop 3 cell 0 drop 3 cell 1 drop 3 cell 2 drop 3 cell 3
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 304 of 676 pnr25.chapt05.01 august 14, 2000 header from the lcd. 6. when the payload data is available from memory, it is written to the cell buffer following the header. 7. if the segmentation logic determines that the current cell being assembled will be the last cell of this frame, the aal5 trailer is appended to the cell buffer, with any unused bytes being padded with zeros. 8. if the current cell is not the last of the frame, the partial crc is written back out to the lcd. 9. after the cell has been completed, it is marked as available to the link level logic
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 305 of 676 11.1: segbf software lcd enqueue this register provides a mechanism for software to transmit a single cell or a group of cells making up a buffer that can contain any user-defined data at any time. to cause a cell/buffer to be transmitted, the software must write the address of a valid lcd control block to this register. the segmentation hardware will then construct a cell to match the aal type defined in the lcd control block, using the segmentation pointer contained in the lcd to fetch data and present this cell to the next lower level of hardware to transmit. this method of cell transmission bypasses the cell scheduler completely, so it is the responsibility of the software to ensure that peak and average rates are not violated. when the segmentation logic has completed building the cell/frame and queued it for transmission, the lcd address will be loaded into the software lcd complete register. this method of cell transmission is not designed for high performance and, as such, there is only a single level of queueing underneath the complete register. it is recommended that only a single software lcd be queued to the segmentation logic at any one time to prevent hanging the segmentation logic as it attempts to queue a complete software lcd to the complete queue. length 32 bits type read/write address xxxx 1400 power on value x ? 0000 0000 ? restrictions before enqueing a vci, software must ensure that the previous software enqueue has been handled by the hardware. this is accomplished by reading this register before an enqueue is attempted. if a value of ? 0 ? is returned, the segmentation hardware is ready to accept an enqueue operation. if a non-zero value is returned, it will be the address of the previous vci that was enqueued and this indicates that the segmentation hardware has not been able to enqueue the vci to it's internal vci buffer segmentation queue. if this mechanism shows that this interface is busy and unable to accept new vci addresses for any appreciable amount of time (tens of s), it is likely that a condition exists which is preventing the hardware below the segmentation logic from accepting cells for transmission, and the segmentation logics input buffer is full. this mechanism also adds the restriction that a vci control block should never exist at address ? 0 ? . vci control block address drop cell type 313029282726252423222120191817161514131211109876543210 bit(s) description 31-7 these bits contain the upper 25 bits of the address of the vci control block. 6-5 these bits define which drop this enqueue operation will be associated with. 4-0 these bits control what type of cell will be built by the segmentation logic. there are currently only two valid values for these bits. if these bits are all ? 0 ? , a normal cell as defined by the lcd will be built. if these bits have a value of 0x1f, an abr cell will be built using fields defined in the lcd.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 306 of 676 pnr25.chapt05.01 august 14, 2000 11.2: segbf control register this register provides a mechanism to control the various programmable features of segbf. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 1408 and 40c power on value x ? 98400000 ? restrictions none steer internal status to enstate outputs free enqueued buffer queue ? complete ? event pause at idle reserved drop priority reset segbf control logic # of buffers for ? not ready ? enable transmit complete logic disable lcd statistics wrapping ignore all requests from scked disable couner wraps enter segbf diagnostics mode 313029282726252423222120191817161514131211109876543210 bit(s) description 31-16 these bits are used to steer internal segbf status to the enstate outputs. 15 this bit, when set, will cause the segmentation processors to free a software enqueued buffer after the last cell has been generated. 14 this bit, when set, will cause the segmentation processors to queue a transmit complete event after the last cell has been generated for a software enqueued frame. 13 this bit, when set, will cause the segmentation logic to pause when it reaches the idle state. segmentation will not be continued until this bit has been reset. care must be taken to leave this bit set for a very short duration so that segmenta- tion throughput will not be adversely affected. 12-10 reserved 9-8 these two bits define the prioritization scheme used by the segmentation logic to determine which drop to build a cell for when running in frame mode. a value of ? 00 ? will provide for equal priority among all drops, the drops will be processed in order from zero to three as long as data is available to segment and space is available in the cell buffer for the drop. a value of ? 01 ? will provide descending priority from drop 0 to drop 3. if data exists and a cell buffer is available for drop 0, a drop 0 cell will always be built regardless of the situation on any other drops. in this mode, a cell will only be built on dro p three if all other drops either have not data or no cell buffer available. 7 this bit, when set, will reset all control logic in the entity. after being set, this bit must be reset before the segmentation logic will function properly. this bit must remain set for at least one microsecond to reset the segmentation logic properly. 6-5 these two bits define the number of cell buffers that can be filled on a given drop before a not ready condition is returned to the cell scheduler. this addresses latency issues caused by multiple cells waiting for transmission by the lower link level. a value of ? 00 ? allows all four cell buffers to be used at any time; a value of ? 01 ? allows one cell buffer to be used; a value of ? 10 ? allows two cell buffers to be used, and a value of ? 11 ? allows three buffers to be used. 4 this bit, when set, enables the transmit complete event modification logic in the segmentation processors. this logic will retrieve two bits from the xmit_comp_evnt_mod field in the lcd and logically or them with bits eight down to seven of the buffer address being enqueued to rxque. this logic only functions when buffer addresses are being queued; it will not modify the event if lcd addresses are being enqueued. this also adds the restriction that all buffer addresses must start on a 512-byte boundary or greater.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 307 of 676 3 this bit, when set, disables the lcd statistics wrap events. 2 this bit, when set, will cause all requests from the cell scheduler to be ignored. this allows complete program control of all cells being sent out on the external interface. 1 this bit, when set, disables the programmable counter wrap events. 0 this bit, when set, causes the segbf entity to enter diagnostic mode. this bit must be set in order to access the internal array. when accessing the array, care must be taken that normal entity reads and writes of the array are not happening at the same time or the results will be indeterminate. bit(s) description
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 308 of 676 pnr25.chapt05.01 august 14, 2000 11.3: segbf status register this register provides feedback to the user on the current status of segbf. see note on set/clear type registers on page 93 for more details on addressing. length 8 bits type clear/set address xxxx 1410 and 414 power on value x ? 00 ? restrictions none reserved cell generation complete invalid condition detected 76543210 bit(s) description 7-2 reserved 1 this bit, when set, indicates that the segmentation logic has completed cell generation for an lcd that was enqueued by the software to the software lcd enqueue register. 0 this bit, when set, indicates that the segmentation logic has detected an invalid condition in one of the lcds that it was processing. the address of the lcd in error is contained in the invalid lcd register. any invalid lcds detected are not processed further by the segmentation logic, so the program must do something to clear this condition.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 309 of 676 11.4: segbf invalid lcd register this register provides feedback to the program when the segmentation logic detects an invalid lcd. if multi- ple invalid lcds are being processed, this register will contain the address of the last one that was processed by the segmentation logic. there are several invalid lcd situations that the segmentation logic checks for: the first is the lcd address not being on the correct boundary. for example, if the chip is configured to have all lcds on 128-byte boundaries and an lcd is encountered that is not on a 128-byte boundary. another invalid condition is when the transmit length configured in the lcd plus the offset in the lcd when added together exceed the maximum overall packet size configured in the chip. it is up to the program to determine which of the possible conditions caused the error to be reported. length 32 bits type read/write address xxxx 1418 power on value x ? 00000000 ? restrictions none detected vcd error address always read as ? 0 ? 313029282726252423222120191817161514131211109876543210 bit(s) description 31-7 these bits contain the 32-bit address of the lcd detected to be in error. 6-0 reserved. always read as ? 0 ? .
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 310 of 676 pnr25.chapt05.01 august 14, 2000 11.5: segbf software lcd complete this register provides feedback to the program when the segmentation logic completes cell generation for an lcd that was enqueued by the software. after the segmentation logic has updated the lcd, the address of the lcd is copied into this register providing any previous lcd addresses written to this register have been read by the software. if multiple software queued lcds are outstanding to the segmentation logic at any time, the segmentation process can be delayed when multiple software enqueued lcds complete without the software getting a chance to read the lcd addresses from this register. to guarantee that the segmentation logic never has to wait for the software to read this register, it is recommended that only one software lcd be enqueued at any one time. length 32 bits type read/write address xxxx 141c power on value x ? 00000000 ? restrictions bits 5 through 0 are not implemented and will always return ? 0 ? . to maintain future compatibility, ? 0 ? s should be written to these bits. upper 25 bits of lcd address drop read as 0 last cell 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 these bits contain the upper 25 bits of the lcd address that the segmentation logic has finished processing. 6-5 these bits indicate the drop on which the cell was sent. 4-1 these bits will read back as ? 0 ? . 0 this bit will be set when the cell that was built was the last cell of a frame and reset if the cell that was built was not the last cell of a frame.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 311 of 676 11.6: segbf interrupt enable register this register allows the user to selectively determine which bits in the segbf status register will cause processor interrupts. a ? 0 ? in a bit position masks interrupts from the corresponding bit location in the segbf status register. a ? 1 ? in a bit position allows interrupts for the corresponding bit in the segbf status register. see note on set/clear type registers on page 93 for more details on addressing. 11.7: segbf programmable counters this register provides the user with feedback on the number of times that a particular event or condition has occurred in the segmentation logic. the event or condition that causes this counter to increment is defined by the associated segbf programmable counter source specification register. when the counter wraps, an event is generated. length 12 bits type clear/set address xxxx 1420 and 424 power on value x ? 00 ? restrictions none length 32 bits type read/write address counter 0 xxxx 1430 counter 1 xxxx 1434 counter 2 xxxx 1438 counter 3 xxxx 143c power on value x ? 0000 0000 ? restrictions none count of occurrences 313029282726252423222120191817161514131211109876543210 bit(s) description 31-0 these bits contain a count of the occurrences of the desired event or condition.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 312 of 676 pnr25.chapt05.01 august 14, 2000 11.8: segbf transmit lcd size this register should be loaded with the number of eight-byte words that are needed for the maximum-sized lcd that will be setup by software. refer to the previous section describing lcd layout to determine the number of words required to support the different modes. the minimum value is six. this is the correct value when running only aal5 mode; it includes three words of scheduling information, two words shared between csked and segbf, and one word for segbf to maintain statistics. setting this register to a value that is too small will likely cause the chip to function improperly. setting this register to a value that is too large will adversely affect performance. length 4 bits type write/read address xxxx 1488 power on value x ? 6 ? (this is the correct value when running aal5 with statistics.) restrictions minimum is 6, maximum is 0xa number of words 3210 bit(s) description 3-0 these bits contain the number of eight-byte words in the lcd to be used by the transmit logic.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 313 of 676 11.9: segbf cell queue status this register indicates the number of cells queued up for transmission over the media. segbf can have a maximum of 16 cells queued up for transmission: four cells on each of four drops. when a bit is set to ? 1 ? , the corresponding cell buffer contains a cell that has not been completely processed by the link logic. length 16 bits type read address xxxx 148c power on value x'0000' restrictions none incomplete cell in drop 3 incomplete cell in drop 2 incomplete cell in drop 1 incomplete cell in drop 0 1514131211109876543210 bit(s) description 15-12 these bits indicate which cell buffers contain cells that have not been processed by the link level for drop 3. 11-8 these bits indicate which cell buffers contain cells that have not been processed by the link level for drop 2. 7-4 these bits indicate which cell buffers contain cells that have not been processed by the link level for drop 1. 3-0 these bits indicate which cell buffers contain cells that have not been processed by the link level for drop 0.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 314 of 676 pnr25.chapt05.01 august 14, 2000 11.10: segbf processor 1 control/status reading this register provides feedback to the user on the current state of segmentation processor 1. writing the appropriate bits in this register causes processor 1 to begin executing at a new location specified in the data that was written. length 32 type read/write address xxxx 14a0 power on value x ? 0000c000 ? restrictions none reserved load ip 1 halt processor 1 reset processor 1 reserved instruction pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 reserved 15 writing ? 0 ? to this bit causes the instruction pointer (ip) for processor 1 to be loaded with the data in bits 8 down to 0. this bit will immediately be set back to '1' after the ip load completes. 14 writing ? 0 ? to this bit halts processor 1. writing ? 1 ? makes the processor fetch and execute instructions. 13 setting this bit to '1' resets processor 1. 12-9 reserved. 8-0 when written, these 9 bits contain the new ip for processor 1. when read, these bits reflect the current ip for processor 1.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 315 of 676 11.11: segbf processor 2 control/status reading this register provides feedback to the user on the current state of segmentation processor 2. writing the appropriate bits in this register causes processor 2 to begin executing at a new location specified in the data that was written. length 32 type read/write address xxxx 14a4 power on value x ? 0000c000 ? restrictions none reserved load ip 2 halt processor 2 reset processor 2 reserved instruction pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 reserved 15 writing a ? 1 ? to this bit will cause the instruction pointer (ip) for processor 2 to be loaded with the data in bits 8-0. this bit will immediately be set back to a ? 1 ? after the ip load completes. 14 writing a ? 0 ? to this bit will halt processor 2; writing a ? 1 ? will make the processor fetch and execute instructions. 13 setting this bit to a ? 1 ? will reset processor 2. 12-9 reserved 8-0 when written, these nine bits contain the new ip for processor 2. when read, these bits reflect the current ip for proces- sor 2.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 316 of 676 pnr25.chapt05.01 august 14, 2000 11.12: segbf programmable counter source specification this register determines what event or condition will cause the associated counter to increment. length 32 type read/write address counter 0 xxxx 14b0 counter 1 xxxx 14b4 counter 2 xxxx 14b8 counter 3 xxxx 14bc power on value counter 0 x ? 000 0803 ? counter 1 x ? 000 0903 ? counter 2 x ? 008 0803 ? counter 3 x ? 002 0203 ? restrictions none reserved event source count all drops data byte mask byte specificdrop offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-27 reserved. 26-25 these bits select the source of the event to be counted. ? 00 ? selects the cell events that are further defined in bits 23 down to 0 of this register. ? 01 ? selects the number of bytes transmitted on a given drop. ? 10 ? selects the number of frames trans- mitted on a given drop. the drop is selected by bits seven and six, or all drops can be included by setting bit 24. 24 this bit, when set, causes the counter to count the specified event for all drops, not just the drop specified in bits seven and six. 23-16 these bits define the data byte that is compared to the result of logically anding the data byte being written to the cell array at the offset specified in bits 5-0 with the mask in bits 15-8. if there is an exact match, the counter will increment. 15-8 these bits define the mask byte to be logically anded with the data byte being written to the cell array. 7-6 these bits determine which drop this counter is associated with. 5-0 these bits define a byte offset into the cell being built in the segmentation cell array. zero corresponds to the first byte in the cell and 63 corresponds to the last byte in the cell. when the segmentation logic copies a byte of data into the cell array at this offset, the logic compares the byte defined in bits 23-16 to the logical and of the data being written and the mask defined in bits 15-8 of this register. if an exact match is detected, the counter will be incremented.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 317 of 676 11.13: segbf cell staging array pointer this register points to an offset in the segbf cell staging array for accesses from the pci bus. this register must be loaded with the correct offset before the desired data can be read from the segbf cell staging array data register. this register will auto-increment after each access to the associated data register. when the last address is accessed, this register wraps to zero. length 10 type read/write address xxxx 14c0 power on value x ? 000 ? restrictions none offset ? 00 ? 9876543210 bit(s) description 9-2 these bits provide an offset into the segbf cell staging array for accesses from the pci bus. these bits provide access to the 256 unique four-byte locations in the array. accessing the last location in the array will cause the address to wrap back around to the beginning of the array. 1-0 these bits are not implemented, they can not be written and will always return ? 0 ? when read.
IBM3206K0424 ibm processor for network resources preliminary atm transmit buffer segmentation (segbf) page 318 of 676 pnr25.chapt05.01 august 14, 2000 11.14: segbf cell staging array data this array is divided into 16 64-byte buffers used to assemble cells that are ready for transmission on the physical interface. 11.15: segbf instruction sram pointer this register points to an offset in the segbf sram that is used to store processor instructions. this register must be loaded with the correct offset before the desired data can be read/written from/to the segbf instruc- tion sram data register. this register will auto-increment after each access to the associated data register. when the last address is accessed, this register wraps to zero. the first 256 locations in the array should be loaded with the instructions for processor 1, and the second 256 locations should be loaded with the instruc- tions for processor 2. length 32 type read/write address xxxx 14c4 power on value undefined restrictions this array can only be accessed when the diagnostic mode bit in the control regis- ter is set. accesses attempted when not in diagnostic mode will return 0xbaddbadd. length 10 type read/write address xxxx 14c8 power on value x ? 000 ? restrictions none offset ? 0 ? 9876543210 bit(s) description 9-1 these bits provide an offset into the segbf instruction sram for accesses from the pci bus. these bits provide access to the 512 unique two-byte locations in the array. accessing the last location in the array will cause the address to wrap back around to the beginning of the array. 0 this bit is not implemented; it can not be written and will always return ? 0 ? when read.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 atm transmit buffer segmentation (segbf) page 319 of 676 11.16: segbf instruction sram data this register address can be used to read/write the instruction data that is needed by the segmentation processors. all instructions must be written before the processors can be brought out of the halt state. 11.17: mpeg-2 pcr increment register each tick of the time base will add the contents of this register to the mpeg pcr reference register. this register contains a fixed point number with 27 bits of fraction and five bits of units. this means that the exter- nal reference clock can range in speed from 22.5 khz to the maximum speed of this entity which is tbd. assuming that the entity will run with a 50 mhz clock, the conversion to 720khz can be done with an accuracy of 1.1 parts in two million. (a clock of 19.4 mhz will give a conversion accuracy of one part in 4.9 million.) if the input clock is 19.4 mhz, then the value to put in the increment register is (720,000 / 19,400,000) * 2**27 or 4,981,277. if the input clock is 33 mhz, then the value to put in the increment register is (720,000 / 16,666,666) * 2**27 or 5,798,206. length 16 type read/write address xxxx 14cc power on value undefined restrictions this array can only be accessed when the processors are in the halt state. reads attempted when the processor is in run mode will return invalid data. writes attempted when the processor is in run mode will be ignored. length 32 type read/write address xxxx 1468 power on value x ? 002c3c9f ? (33 mhz) restrictions none units fraction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-27 these bits contain the whole part of the increment value. 26-0 these bits contain the fractional part of the increment value.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 320 of 676 pnr25.chapt05.01 august 14, 2000 receive data path entities entity 12: cell/packet re-assembly (reasm) reasm is the top level receive entity that encapsulates all of the receive sub-entities. note: the receive portion of the chip is very different from previous versions of the processor. reasm no longer does hec correction or detection, since everything we interface to already does this function. the following figure shows how reasm interacts with the other entities: reasm entity interfaces pools rxque dmaqs comet pakit intst pcint reasm linkr
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 321 of 676 reasm is made up of a number of sub-entities to provide the overall receive functionality. r easm contains the following sub-entities: rxxlt, rxcrc, and rxaal form a cell processing pipeline. each st age is allowed up to a cell time to process the cell it is currently working on. this means each cell has the potential to have a three-cell time latency through the reasm entity. the overall performance should be at its maximum since a single cell completes processing every cell time. the stages are allowed to run faster if there is no blocking condition. the only blocking condition is the latency of memory accesses and the total length of the nano-program that needs to run. the following sections provide a brief description of each sub-entity and the function it provides. rxbuf provides receive cell/packet buffering between linkc and r easm. also defines the port configurations and mappings. rxxlt provides general lcd translation facilities. rxcrc provides crc fac ilities. rxaal performs the cell and packet reassembly functions including aal processing and all cell and packet post-processing functions. rxlcd provides rx lcd caching for the reasm sub-entities. reasm sub-entity block diagram pools rxque dmaqs comet pakit linkr rxxlt rxcrc rxlcd rxaal rxbuf reasm
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 322 of 676 pnr25.chapt05.01 august 14, 2000 miscellaneous reassembly functions atm oam cell processing when processing an atm data stream, oam cell processing may be necessary. this function needs to be enabled in the reasm reassembly modes register. reasm performs oam discrimination when enabled. this function can be enabled on a per port basis. as cells arrive for processing, the nano-code works together with some dedicated logic to discriminate between different types of oam cell traffic. each type that is discriminated produces a different event when traffic is surfaced to a receive queue. the different types that are discriminated are: both the rxcrc and rxaal nano-c ode understand and process oam traffic differently when enabled. in the receive lcd there are control bits that allow the user to specify on a per connection basis how the oam traffic should be handled. there are two types of flows when processing oam traffic. a connection can be either "routed" or "terminated." a terminated connection is any connection that terminates either cells or packets. aal5 and packet lcds that are fast forwarded are considered "terminated" because the packet is terminated before the packet is fast forwarded. a "routed" connection is a raw lcd that is fast forwarded including raw mode with early packet discard. when oam traffic is processed on a "terminated" connection, the oam traffic can be terminated or dropped based on the discrimination configuration bits in the receive lcd. a mask value of ? 0 ? specifies to terminate the cell, and a mask value of ? 1 ? specifies to drop the cell. when oam traffic is processed on a "routed" connection, the oam traffic can be fast forwarded or dropped based on the discrimination configuration bits in the receive lcd. a mask value of ? 0 ? specifies to fast forward the cell, and a mask value of ? 1 ? specifies to drop the cell. this allows the user to filter the oam traffic based on the type of oam traffic on a per connection basis. the mask bit is determined by using the sub-type mask bit if pertinent. for example, an f5 segment pm cell will use the "segment pm cell" mask bit. if one of the sub-types does not match, then the basic types are segment vci = 0003 end to end vci=0004 segment not f4 and pti field = "100" end to end not f4 and pti field = "100" forward cell pti = "110" and dir=0 backward cell pti = "110" and dir=1 reserved cell pti field = "111" end to end alarm end to end and oam type=0001 and func=0000 or 0001 segment alarm segment and oam type=0001 and func=0000 or 0001 end to end loopback end to end and oam type=0001 and func=1000 segment loopback segment and oam type=0001 and func=1000 end to end pm cell end to end and oam type=0010 segment pm cell segment and oam type=0010 end to end activate/deactivate cell end to end and oam type=1000 segment activate/ deactivate cell segment and oam type=1000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 323 of 676 used (that is, f4 end-to-end). there is a 16-bit mask field in the receive lcd. a description of each bit is in the table below: when an oam cell is processed, the configuration information from the gpmtage is used to make reassembly decisions like which buffer pool or receive queue to use. tcp/ip receive checksum verification when enabled, the IBM3206K0424 is able to perform verification of the ip header checksum and the associ- ated protocol checksum for the user. the final checksum status is raised to the user in the packet header flags. this function is accomplished by the rxcrc entity using the crc nano-program. to enable and use the function, several things must be done: tcp/ip checksum function must be enabled in the reasm mode register. this enables the overall func- tion and includes the checksum state words in the receive portion of the lcd. specify a frame type in the frametype field of the receive lcd. this field specifies an entry point into the checksum verification nano-code. the entry point points to a piece of code that understands how to locate the ip header based on the current frame type. for example, a connection might be native ip over atm or lane eth. for the currently supported types, see the crc.txt file provided with the rxcrc code load. note: other types can be added if needed. once properly enabled, tcp/ip checksums are verified as packets arrive. the status is raised to the user in the packet header using four bits of status (two bits for ip and two bits for protocol). the format and meanings of the bits are specified in packet header. for connections that have mixed traffic, the checksum operation is only run on packets that are recognized as tcp/ip. for example, on a lane eth connection packets of different protocols can be interleaved. bit description 15 reserved 14 f4 segment 13 f4 end to end 12 f5 segment 11 f5 end to end 10 rm forward cell 9 rm backward cell 8 pti reserved cell 7 end to end alarm 6 segment alarm 5 end to end loopback 4 segment loopback 3 end to end pm cell 2 segment pm cell 1 end to end activate/deactivate cell 0 segment activate/deactivate cell
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 324 of 676 pnr25.chapt05.01 august 14, 2000 scatter/cut through receive processing the scatter/cut through support is very versatile and easy to use. scatter typically refers to scattering pages from a contiguous IBM3206K0424 buffer into multiple non-contiguous host pages. cut through refers to moving contiguous data from IBM3206K0424 buffers into contiguous storage in host memory. the functions are similar, and the terms scatter and cut through may be interchanged in the following text since cut through is really a special case of scatter. the correct term is used when context requires it. the scatter processing is performed by rxaal along with rxque and dmaqs. the following items need to be setup: dmaqs should be setup and ready to run. rxque should be setup and ready to run. each queue that is used should have the proper event size selected, the direction should be set correctly, and timestamps and bcach advice should be disabled. page buffers or descriptors should be placed on the configured receive queues. the scatter configurations need to be set in the rxall - scatter/cut through info registers. the scatter flags need to be set in the rxall - scatter/cut through flag registers. each lcd that is to use scatter, needs to have the ppmode field set to do scatter. a scatter configuration needs to be selected for each connection by setting the cutthrusel field in the receive lcd. once set up, the scatter mechanism is performed by r xaal for the user. there is user intervention r equired to process the packets when the scatter is complete, and for page recovery in error scenarios. there are many options when setting up scatter, and the selection of the type of scatter processing to perform depends on the users environment. the basic scatter mechanism will be described followed by a discussion of the different options that can be used. when packets are received and scattered, the following structure shows the main components of the received packet: the dma list is maintained immediately after the IBM3206K0424 packet header, and before the receive packet data. for this reason, the user should allocate enough space between the packet header and the packet data to accommodate a maximum-sized dma list based on the maximum number of pages that could be dmaed. the rxoffset field in the receive lcd is where this offset is specified. the maximum receive offset is 256 bytes, which is specified with an rxoffset value of ? 0 ? . the following is the layout of the dma list: general layout of a received packet in scatter mode struct scatterrxpacket { packetheader; // charm packet header dmalist; // scatter dma list padbytes; // pad out to receive offset from lcd packetdata; // actual receive packet };
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 325 of 676 the first eight bytes are always present and are filled in when the packet is complete or when an error occurs. the actual page list is filled in as the data is dmaed. the first location is initially skipped and is filled in later when the header is dmaed. the second and subsequent entries are filled as each page is dmaed. each page list entry contains either physical page addresses, IBM3206K0424-based dma descriptor addresses, or user data. whether a physical page address or dma descriptor address is present depends on the cut through configuration. from here on, the term page address and dma descriptor are used interchangeably as either is valid based on the configuration, but the correct term is used when the context requires it. a page list entry can contain one or two pieces of information. each page list entry can be 32, 64, or 128 bits long. if using 32 bit addresses, then the entry is 32 or 64 bits. if using 64-bit addresses, then the entry is 64 or 128 bits. the first piece is always the page address or the dma descriptor address. each cut through config- uration allows the user to specify an optional second deque operation from the receive queue being used. this allows the user to place user information associated with the particular page address in the receive queue and the page list. thus, the corresponding virtual address of a page could be surfaced along with the physical page address. it is very important to enque information to the receive queue in the proper order if using this mode. the physical page address is first, followed by the user information. as the receive packet data is being received, it is dmaed as soon as a page crossing occurs if there is a dma descriptor available on the receive queue being used. if no descriptor is available, then no dma takes place until the next receive cell is received, at which time the receive queue availability is checked again. this catch-up process continues until the packet is complete. when the packet is complete, all dmas are sched- uled if page addresses are available. if a page address is not available, then a "no dma descriptor available" is surfaced to the user so the packet can be used and the dma list recovered. as each data page is dmaed to the user, a dma descriptor is formed and enqueued to the dmaqs dma queue specified in the cut through configuration. the dma descriptor is formed based on if page addresses or dma descriptor are provided on the receive queue being used. if IBM3206K0424-based dma descriptors are being used, then the receive queue contains dma descriptor chains where the low order bits of the dma descriptor address specify how many descriptors are in the chain. typically, this chain length is one, but more can be used. the first descriptor in the chain provides the destination address (page address) which is filled in by the user. the source address, the length, and the flags are filled in by the IBM3206K0424 for the first descriptor in the chain. the source address is filled in with the beginning address of the page within the current receive buffer. the length is filled in with either the page size (if a full page is present) or the number of bytes in the last page for the last page. the flags are filled in using the flags from the appropriate rxall - scatter/cut through flag registers. if physical page addresses are contained in the receive queue, then a general layout of a scatter dma list struct dmalist { bit16 numheadbytes; // number of bytes included with header dma bit16 numtailbytes; // number of bytes in last dma page bit1 deqlocked; // error status bit1 deqinvalid; // " bit1 headertruncated; // " bit1 baddmalist; // " bit4 deqlockedqueuenum; // " bit16 reserved; bit2 cutthrusel; // copy of cutthrusel used from receive lcd bit6 numpages; // number of page entries that follow (max=63) bit32 pagelist[n]; // actual dma descriptors or page addresses // note: each entry can be 32, 64, or 128 bits wide };
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 326 of 676 pnr25.chapt05.01 august 14, 2000 single dma descriptor is formed by dmaqs directly in dma queue storage using the page address and the same information that would have been filled into the dma descriptor. generally, using page addresses performs better, but is less versatile, which is usually a good trade off. normally no dma event is generated in the flags when pages are dmaed. when the last cell of a packet is received, and all the data pages have been dmaed, the packet header and dma list are updated and dmaed into a header buffer. the mechanism and configuration of the header buffer is similar to the pages, but separate configuration is usually necessary for correct functionality. for example, different flags are normally used in order to get an event for the header dma so the user can process the packet. the header dma normally frees the IBM3206K0424 buffer; another difference is the page (or buffer) size used for headers is normally different than the normal page size. some of the optional features described later also drive having different configuration for the header dmas. once the user gets the event for the header dma, the user processes the received packet using the dma list and the packet header. once the packet has been processed, the pages or descriptors need to be returned to the proper receive queue when the pages can be reused, thus completing the scatter processing. there are several ways of getting that important event to start the receive processing. usually the event is generated when the last header dma is complete. if dma descriptors are being used, then there are two choices. first, the normal dma flag that generates an event can be used. this generates an event with the dma descriptor address in the significant bits. while this works and may be desirable in some environments, the dma descriptor needs to be read in order to get access to the host header buffer address. the second way to generate an event when using descriptors is to provide a second dma descriptor in the dma descrip- tor chain that enqueues the header buffer address and a user-defined event in the lower order bits. generat- ing an event in this manner provides the user with the buffer address; the header dma descriptor address is available in the header buffer as part of the dma list. when using page addresses, the event source in the cut through configuration should be set to use the desti- nation address as the event data. when this is done, the event data contains the header buffer address as in the second case above. error recovery there are two types of error that need to be handled. first, if there is no error on the receive packet and a page address was not available, then the packet is surfaced to the user with a "no dma descriptor available" event in the event type field and the IBM3206K0424 buffer address in the event information field. the user has a choice at this point. the packet is good so it can be used or freed by the user. in either case, the dma list in the packet header must be recovered. so if the dma list in the header is not used, it should be recov- ered by returning it to the proper receive queues. the event surfaced specifies which type of page address failed so the user can parse the dma list properly. the event will specify whether a normal page descriptor, optional header descriptor, or packet header descriptor. the same descriptor recovery must be performed when an error event is surfaced (that is, crc error). when there is an error event, no packet header dma is performed so no packet header descriptor is in the dma list. scatter options most of the optional scatter features have to do with the header bytes and how the header dma is performed. how the number of header bytes is determined is explained below. for now, just assume there are some number header bytes. the numheadbytes field in the dma header specifies the number of header bytes that are available. the location of the header bytes in the dma buffers can be configured. the default is for them to be kept with the packet header and dma list in the packet header buffer. for this case, the user should be sure the packet header buffer size is large enough to contain all of this data. alternatively, the header bytes can be placed in a separate buffer. to do this, split header mode should be
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 327 of 676 enabled in the cut through configuration. this buffer is referred to as the optional header page and uses its own page size and receive queue to allow for better storage utilization. when enabled, the second entry in the dma list becomes the optional header page entry, and should be treated accordingly for page recovery. in split header mode, the header bytes are dmaed as soon as they are all received. this mode is useful if the user environment requires the header bytes to be in a separate buffer from the packet header and dma list. another optional feature is to dma the header only. this feature is enabled in the cut through configuration. when enabled, only the packet header, dma list, and header bytes are dmaed. either a single dma or two dmas occur based on if the optional header feature is enabled. this feature can be useful when a routing decision needs to be made for a packet and the entire packet does not need to be brought into host storage. another possible scenario is the header bytes may determine how the user wants to dma the packet data to the host. for smaller packet sizes, it may be more efficient to perform a single dma and keep the packet header, dma list, and packet data in a single buffer. to do this, single page mode should be enabled in the cut through configuration. when enabled, the header page size is used to determine the dma behavior. if a packet completes and the total length of the packet and headers will fit in the header page size, then a single dma is performed. if the data length exceeds the single page size as it is being received, the data is scattered using the normal options (might need to catch up). this feature can be useful for optimizing user processing for smaller packets. for example, all packets less than 2k might be a candidate for this feature. head bytes there are two ways to set the number of head bytes. they are set on a per connection basis in the receive lcd using the numheadbytes and usecrcnumhead fields. when the usecrcnumhead field is set to ? 0 ? , the numheadbytes field provides a fixed number of bytes that is used as the number of header bytes. when usecrcnumhead field is set to ? 1 ? , then the rxcrc nano code will calculate the number of header bytes using the frametype field to index an ip procedure. currently, rxcrc w ill only set the number of header bytes for recognized tcp/ip headers. other headers can be recognized. contact ibm technical support to discuss requirements.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 328 of 676 pnr25.chapt05.01 august 14, 2000 12.1: reasm logical channel descriptor base register the reasm logical channel descriptor base register indicates the starting address of the logical channel descriptor table. this register defines where the logical channel descriptors are located. length 32 bits type read/write address xxxx 1618 power on value x ? 00008000 ? restrictions the value must be in the range of the physical memory allocated for control memory. lcd table base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this register defines where the logical channel descriptors are located.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 329 of 676 12.2: reasm mode register used to set reasm and sub-entity modes. this register contains the mode bits that specify how reasm is to operate. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write address xxxx 1610 and 614 power on value x ? 00000000 ? restrictions none rxaal rxcrc rxxlt reserved reset receive logic disable counter overflow rxrto free buffer enable tcp/ip checksums diagnostic 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 rxaal code specific mode bits. if used, documented in code load documentation. 27-24 rxcrc code specific mode bits. if used, documented in code load documentation. 23-8 rxxlt code specific mode bits. if used, documented in code load documentation. each nibble is for a port. bits 23-20 are rxxlt mode bits 3-0 for port 3, bits 19-16 are rxxlt mode bits 3-0 for port 2, bits 15-12 are for port 1, and bits 11-8 are for port 0. 7-5 reserved. 4 reset receive logic. 3 disable counter overflow events. 2 rxrto free buffer option. when set, a buffer that times out is freed and the event will contain the lcd address instead. 1 enable tcp/ip checksums. when set, tcp/ip checksum verification is enabled. when enabled, the receive lcd data structure includes the ip state. 0 diagnostic mode. when set, reasm is placed in diagnostic mode.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 330 of 676 pnr25.chapt05.01 august 14, 2000 12.3: reasm reassembly modes register used to set reassembly modes. this register contains the mode bits that specify different reassembly modes. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write address xxxx 1630-34 power on value x ? 00000000 ? restrictions none reserved enable new rm events enable oam cell discrimination reserved specifies congestion bit source specifies chip source disable aal5 length checking disable aal5 crc checking disable aal5 cpi checking 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-13 reserved reserved 12 enable new rm events when set, the new rm cell events are enabled, and the abr event routing register is ignored. this allows separate events for forward and backward rm cells, but routes the events to the general oam cell receive queue. 11-8 enable oam cell discrimination when set, the oam processing is enabled for ports 0-3. when cleared, oam cells are not discriminated. 7 reserved reserved 6-5 specify which congestion bit source to use if doing routing. values are: 00 use value from lcd routed lcd ptr field 01 use ored congestion value (or last in case of cell) 10 use value from last cell 4-3 specify which clp source to use if doing routing. values are: 00 use value from lcd routed lcd ptr field 01 use ored clp value (or last in case of cell) 10 use value from last cell. 2 disable aal5 length checking when set, the aal5 trailer length field is not checked. 1 disable aal5 crc checking when set, the aal5 trailer crc is not checked. 0 disable aal5 cpi checking when set, the aal5 trailer cpi bytes are not checked against zero.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 331 of 676 12.4: reasm status register used to surface reasm and sub-entity status. this register contains the status bits for the reasm sub-entities. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write address xxxx 1600 and 604 power on value x ? 00000000 ? restrictions none reserved rxbuf cell buffer thrshd exceeded bad lcd receive offset detected rxque dequeue state mach. locked bad lcd update operation rxaal nano status rxcrc nano status rxxlt drop 3 nano status rxxlt drop 2 nano status rxxlt drop 1 nano status rxxlt drop 0 nano status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 reserved. 27 rxbuf cell buffer threshold exceeded. this bit is set when the number of receive cell buffers exceeds the threshold set in rxbuf receive buffer threshold. this bit is sticky and must be reset by software after being set. 26 bad lcd receive offset detected. this bit is set when a receive lcd is used that does not have a good receive offset. either the receive offset does not allow for enough room for the configured packet header, or there is not enough room for the dma list entry that would have been written. 25 rxque deque state machine is locked. this bit is set when an rxque deque operation is attempted in order to get a piece of user data for the dma list and there is no data available. when using two pieces of data in a dma list entry, both must be available. 24 bad lcd update operation. this bit is set when a receive lcd update was attempted on an offset that falls in the transmit portion of the lcd, or when an lcd that is out of range is updated. 23-20 rxaal nano status. these bits can be set from the rxaal nano code. if they are used, they are documented in the code load instructions (that is, aal.txt). they may or may not be used. 19-16 rxcrc nano status. these bits can be set from the rxcrc nano code. if they are used, they are documented in the code load instructions (that is, crc.txt). they may or may not be used. 15-12 rxxlt drop 3 nano status. these bits can be set from the rxxlt nano code for drop 3. if they are used, they are docu- mented in the code load instructions (that is, atm.txt). they may or may not be used. 11-8 rxxlt drop 2 nano status. these bits can be set from the rxxlt nano code for drop 2. if they are used, they are docu- mented in the code load instructions (that is, atm.txt). they may or may not be used. 7-4 rxxlt drop 1 nano status. these bits can be set from the rxxlt nano code for drop 1. if they are used, they are docu- mented in the code load instructions (that is, atm.txt). they may or may not be used. 3-0 rxxlt drop 0 nano status. these bits can be set from the rxxlt nano code for drop 0. if they are used, they are docu- mented in the code load instructions (that is, atm.txt). they may or may not be used.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 332 of 676 pnr25.chapt05.01 august 14, 2000 12.5: reasm interrupt enable register used to enable interrupts for reasm status conditions. when set, the corresponding status condition gener- ates an interrupt from reasm to intst. see note on set/clear type registers on page 93 for more details on addressing. 12.6: reasm debug state selector register selects which entity states are surfaced. this register specifies which entity states are surfaced. use this register only under the advice of ibm technical support. length 32 bits type read/write address xxxx 1608 and 60c power on value x ? 00000000 ? restrictions none status interupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 see the bitwise descriptions for the reasm status register on page 331. length 2 x 32 bits type read/write address xxxx 1620-24 power on value x ? 00000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 333 of 676 rxbuf functional description rxbuf provides the cell/packet buffering mechanism between linkr and the rest of reasm. the buffering provides enough storage for 16 64-byte cells and the associated control information for each cell buffer. linkr writes the cell/packet data and control information into the buffers. the buffering mechanism is then exposed to the remainder of the r easm sub-entities for r eading. the cell buffers are sequenced through in sequential order regardless of which port received cells arrive on. thus, a total of 16 cells of buffering exists and is used as a shared 16-cell fifo. 12.7: rxbuf cell data buffer address provides the read/write address for accessing cell data buffer. this register provides the read/write address for accessing cell data buffer. when rxbuf cell data buffer read/write port is read/written, this register is auto-incremented. when the last address is read/written, the address rolls over to zero. rxbuf block diagram length 11 bits type read/write address xxxx 1640 power on value x ? 00000000 ? restrictions low two bits are always zero read interface to rxxlt read interface to sub-entities done rxbuf 16 entry cell info 16 64-byte cell buffers asynchronous boundary with linkr clst(16-0) ovrs rest clst(16-0) ovrs sop eop err portid(4-0) cfgid(1-0) celllen(6-0) addr(6-3) clps addr(6-0) data963-0) wrtic wrtc
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 334 of 676 pnr25.chapt05.01 august 14, 2000 12.8: rxbuf cell data buffer read/write port provides read/write access to receive cell data buffer. the array is divided into 16 64-byte buffers used to buffer/assemble cells received from the line. when this register is read/written, the address provided by rxbuf cell data buffer address is used to select the array word to be accessed. rxbuf cell data buffer address is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. 12.9: rxbuf cell info buffer address provides the read/write address for accessing cell information buffer. this register provides the read/write address for accessing cell information buffer. when rxbuf cell info buffer read/write port is read/written, this register is auto-incremented. when the last address is read/written the address rolls over to zero. 12.10: rxbuf cell info buffer read/write port provides read/write access to the receive cell info buffer. the array is divided into 16 areas used to provide information about each received cell from linkr. when this register is read/written, the address provided by rxbuf cell info buffer address is used to select the array word to be accessed. rxbuf cell info buffer address is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. length 256 words x 32 bits type read/write address xxxx 1648 power on value x ? 00000000 ? restrictions the array can only be accessed in diagnostic mode. if not in diagnostic mode, zero is returned on reads and writes are silently ignored. length 6 bits type read/write address xxxx 1644 power on value x ? 00000000 ? restrictions low two bits are always zero length 16 words x 32 bits type read/write address xxxx 1650 power on value x ? 00000000 ? restrictions the array can only be accessed in diagnostic mode. if not in diagnostic mode, zero is returned on reads and writes are silently ignored.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 335 of 676 12.11: rxbuf receive buffer threshold provides a method to monitor number of cell buffers in use. the value of this register is used to compare against the number of active cell buffers. when this threshold is exceeded, the status is raised in the reasm status register. length 5 bits type read/write address xxxx 1660 power on value x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 336 of 676 pnr25.chapt05.01 august 14, 2000 rxxlt functional description rxxlt is the first stage in the cell processing pipeline. rxxlt provides general lcd translation facilities and link level statistics. these are provided via a nano-processor and nano-programs. up to four unique drops/ports can be supported, each with a unique configuration. each port is able to run a unique nano-program to do lcd address translation. for example, one port may be a packet-based phy using 64-byte segments with ppp lcd translation, and another port may be an atm cell based phy. the drop/config number (0-3) along with the port id is passed to rxxlt from rxbuf/linkr. the drop number (0-3) is used to specify which nano-program is executed by rxxlt to translate cell/packet information into an lcd address. this is different from previous versions of the processor which had a fixed lcd translation mechanism. rxxlt instruction formats are not defined here and are ibm confidential. rxxlt uses the resulting lcd address to load the lcd cache for the next stage of the pipeline. the lcd address and cell buffer address are passed to rxcrc upon completion of processing. there are a number of degrees of freedom in the lcd translation. generally, the nano program performs the following steps: gather some bytes from the cell buffer do some error checking and default lcd checking select and shift appropriate bits to form an lcd translate table index read the lcd translate table to get an lcd index generate the lcd address from the lcd index and the lcd base address there are eight general purpose registers per phy drop and four drops. these eight registers contain values that the nano-code uses, and are available on a per port basis. for example, the lcd translate table addresses would reside in these registers (this is different from previous versions of the processor where these registers were at fixed addresses). other items that might reside in these registers are default/error lcd addresses, compare values, and masks. because these are general purpose registers, multiple lcd tables or multiple default lcds can be specified. one quarter of the total registers are available to each port, so there can be an lcd translate table (etc.) for each port. the total lcd translate tables and lcd table sizes are only limited in size by the amount of memory that is available to the IBM3206K0424. the lcd indexes are limited to 16 bits, and lcd addresses are always 128-byte aligned. the lcd translation code must execute in one cell time in order to run at full bandwidth. the only variable portion of the code execution time is the reads to IBM3206K0424 memory when reading the lcd translation rxxlt block diagram pools get interface cm read interface rxlcd interface rxxlt xlate nano processor lcd translation cache rxcrc rxbuf interface interface
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 337 of 676 table. thus, while a double lookup is possible, it may not meet the time constraints of running at full bandwidth. the following pseudo code shows some of the types of lcd translations that are possible using the nano-processor. note: the following do not imply types/numbers of instructions needed, but the different variable names imply different general purpose registers are being used, so variables are specified on a per port basis. in the following code there are shift, mask, and compare values that are not specified. these are values that would be customizable at run time. these will be customized via the general purpose registers. the following code uses nomenclature that matches the IBM3206K0424 (zero-based big endian). so bit(1) in a comm spec might be bit(0) in the following code. the comments use spec nomenclature so you can match the two up. standard atm atmh = read 4 bytes from rxbuf at offset 0 -- read the atm header from cell if non_user_data { -- non-user data as specified in pti lcdaddr = defaultlcd -- field is handled by the deafult lcd return } tblindex = (atmh and vcimask) >> 4 -- gather pertinent vci bits tblindex |= ((atmh and vpimask) >> x) -- gather pertinent vpi bits -- x depends on num of vci bits used if non-masked bits on { -- check for out of range out of range counter++ -- update counter if mode(x) { -- if configured to flush out of flush cell -- range cells flush and we are done } else { lcdaddr = errorlcdaddr } return } if tblindex == 0 { -- check for zero id zero id counter++ -- update counter if mode(x) { -- if configured to flush zero id flush cell -- cells flush and we are done } else { lcdaddr = errorlcdaddr } return } lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 338 of 676 pnr25.chapt05.01 august 14, 2000 ppp label = read 4 bytes from rxbuf at offset 0 -- read the ??? if label == 0xff030021 { -- what is this field called?? read 1 bytes from rxbuf at offset 4 -- read the ip header version (5th byte) if ipver_headerlgt == 0x45 { tblindex = read byte from offset 5 -- read qos field (6th byte) lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index } else { lcdaddr = defaultportlcd -- use port default lcd } } else { lcdaddr = defaultportlcd -- use port default lcd } q.922 2 byte addressing head = read 2 bytes from rxbuf at offset 0 -- read the header (network bytes 0-1) if (bit(0) == 1) && (bit(8) == 0) { -- ea bits indicate two byte addr -- byte 0 bit 1 == 0 && byte 1 bit 1 == 1 tblindex = (head and dlcimask0) >> x -- gather 6 of 10 dlci bits from byte 0 tblindex |= ((head and dlcimask1) >> x) -- gather 4 of 10 dlci bits from byte 1 lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index } else { lcdaddr = errorlcdaddr -- not a two byte addr } q.922 4 byte addressing head = read 4 bytes from rxbuf at offset 0 -- read the header (network bytes 0-3) if (bit(0) == 1) && (bit(8) == 0) && -- ea bits indicate four byte addr (bit(16) == 0) && (bit(24) == 0) { -- byte 0 bit 1 == 0 && byte 1 bit 1 == 0 && -- byte 2 bit 1 == 0 && byte 3 bit 1 == 1 if dcbit == 1 { -- check for dc bit being set lcdaddr = defaultportlcd -- and surface on default port lcd } else { -- gather 16 least significant dlci bits tblindex = (head and dlcimask1) >> x -- gather 3 dlci bits from byte 1 tblindex |= ((head and dlcimask2) >> x) -- gather 7 dlci bits from byte 2 tblindex |= ((head and dlcimask3) >> x) -- gather 6 dlci bits from byte 3 lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index } } else { lcdaddr = errorlcdaddr -- not a four byte addr }
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 339 of 676 funi 2.0 2 byte addressing head = read 2 bytes from rxbuf at offset 0 -- read the header (network bytes 0-1) if (bit(0) == 1) && (bit(8) == 0) { -- ea bits indicate two byte addr -- byte 0 bit 1 == 0 && byte 1 bit 1 == 1 if (bit(2) == 0) && (bit(9) == 0) { -- fid1 & fid2 == 0 (byte 0 bit 2 & byte 1 bit 3) tblindex = (head and famask1) >> x -- gather 6 of 10 fa bits from byte 0 tblindex |= ((head and famask0) >> x) -- gather 4 of 10 fa bits from byte 1 lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index } else { lcdaddr = defaultportlcd -- otherwise surface on port default lcd } } else { lcdaddr = errorlcdaddr -- not a two byte addr } funi 2.0 4 byte addressing head = read 4 bytes from rxbuf at offset 0 -- read the header (network bytes 0-3) if (bit(0) == 1) && (bit(8) == 0) && -- ea bits indicate four byte addr (bit(16) == 0) && (bit(24) == 0) { -- byte 0 bit 1 == 0 && byte 1 bit 1 == 0 && -- byte 2 bit 1 == 0 && byte 3 bit 1 == 1 if (bit(18) == 0) && (bit(25) == 0) { -- fid1 & fid2 == 0 (byte 0 bit 2 & byte 1 bit 3) -- gather 16 vpi/vci bits tblindex = (head and vcimask0) >> 1 -- gather x vci bits from byte 3 tblindex = (head and vcimask1) >> x -- gather x vci bits from byte 2 tblindex = (head and vcimask2) >> x -- gather x vci/vpi bits from byte 1 tblindex = (head and vpimask3) >> x -- gather x vpi bits from byte 0 lcdindex = lookup(lcdtable, tblindex) -- read index from cm using tableindex lcdaddr = lcdbase + lcdindex*128 -- calc lcd addr from index } else { lcdaddr = defaultportlcd -- otherwise surface on port default lcd } } else { lcdaddr = errorlcdaddr -- not a four byte addr }
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 340 of 676 pnr25.chapt05.01 august 14, 2000 12.12: rxxlt register array address port provides the read/write address for accessing register array. this register provides the read/write address for accessing register array. when rxxlt register array read/write port is read/written, this register is auto-incremented. when the last address is read/written the address rolls over to zero. 12.13: rxxlt register array read/write port provides read/write access to the register array. the array is divided into four groups of eight registers. each group is associated with a receive port (0-3). so each nano-program has eight registers to use. these regis- ters have intended uses and also serve as the link level counters, so they are not general purpose registers. when this register is read/written, the address provided by rxxlt register array address port is used to select the array word to be accessed. rxxlt register array address port is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. length 7 bits type read/write address xxxx 1680 power on value x ? 00000000 ? restrictions low two bits are always zero length 32 words x 32 bits type read/write address xxxx 1688 power on value x ? 00000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 341 of 676 12.14: rxxlt processor state selector allows user to select which data should be accessed with rxxlt processor state read/write port. this register provides the encoded selector for accessing internal processor registers and state via reads/writes to the rxxlt processor state read/write port. 12.15: rxxlt processor state read/write port provides read/write access to the internal state of the processor. the internal processor state is externalized for debug and testing reasons. see the description of rxxlt processor state selector for definitions on the addresses. length 4 bits type read/write address xxxx 1698 power on value x ? 00000000 ? restrictions none bit(s) description 3-0 the following are the meanings of the encoded values: 0000 accumulator register 0001 header register 0010 lcd index register 0011 reserved 0100 reserved 0101 flags 0110 reserved 1111 instruction ptr length 32 bits type read/write address xxxx 169c power on value x ? 00000000 ? restrictions processor state can only be set in diagnostic mode.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 342 of 676 pnr25.chapt05.01 august 14, 2000 12.16: rxxlt instruction array address port this register provides the read/write address for accessing the instruction array. when rxxlt instruction array read/write port is read/written, this register is auto-incremented. when the last address is read/written, the address rolls over to zero. 12.17: rxxlt instruction array read/write port provides read/write access to the instruction array. the instruction array is divided into four groups of 32 entries. each group is associated with a receive port (0-3) so a nano-program can be loaded for each active port. when this register is read/written, the address provided by rxxlt instruction array address port is used to select the array word to be accessed. rxxlt instruction array address port is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. length 9 bits type read/write address xxxx 1684 power on value x ? 00000000 ? restrictions low two bits are always zero length 128 words x 19 bits type read/write address xxxx 1690 power on value x ? 00000000 ? restrictions none, but the instruction stream of an active nano-program should not be written
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 343 of 676 12.18: rxxlt last lcd index register these registers provide the previous lcd index that was used for the corresponding port. length 16 bits type read/write address xxxx 16a0-ac power on value x ? 0000 ? restrictions can only be written in diagnostic mode
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 344 of 676 pnr25.chapt05.01 august 14, 2000 rxcrc functional description rxcrc is the second stage in the cell processing pipeline. it performs the atm crc-32 (ethernet fcs) and atm crc-10 functions if necessary. rxcrc gets lcd type, state, and seed information from the lcd cache, and updates the cache on completion. the results are passed to rxaal upon completion, along with the lcd address. 12.19: rxcrc instruction array address port this register provides the read/write address for accessing the instruction array. when rxcrc instruction array read/write port is read/written, this register is auto-incremented. when the last address is read/written, the address rolls over to zero. rxcrc block diagram length 10 bits type read/write address xxxx 16c4 power on value x ? 00000000 ? restrictions low two bits are always zero rxlcd interface rxcrc crc-32 generation logic rxbuf interface crc-10 generation logic rxcrc interface rxxlt interface
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 345 of 676 12.20: rxcrc instruction array read/write port provides read/write access to the instruction array. the instruction array contains a single nano-program. when this register is read/written, the address provided by rxcrc instruction array address port is used to select the array word to be accessed. rxcrc instruction array address port is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. 12.21: rxcrc processor state selector allows user to select which data should be accessed with rxcrc processor state read/write port. this register provides the encoded selector for accessing internal processor registers and state via reads/writes to the rxcrc processor state read/write port. length 256 words x 19 bits type read/write address xxxx 16d0 power on value x ? 00000000 ? restrictions none, but the instruction stream of an active nano-program should not be written length 3 bits type read/write address xxxx 16d8 power on value x ? 00000000 ? restrictions none bit(s) description 2-0 the following are the meanings of the encoded values: 000 accumulator register 001 header register 010 reserved 011 reserved 100 reserved 101 flags 110 reserved 111 instruction ptr
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 346 of 676 pnr25.chapt05.01 august 14, 2000 12.22: rxcrc processor state read/write port provides read/write access to the internal state of the processor. the internal processor state is externalized for debug and testing reasons. see the description of rxcrc processor state selector on page 345 for definitions on the addresses. 12.23: rxcrc last lcd index register these registers provide the previous lcd index that was used for the corresponding port. 12.24: rxcrc checksum protocol registers these registers provide additional protocol bytes for which checksum calculations should be enabled. the first register allows up to four protocols to be enabled with headers that are similar to udp and tcp which use a pseudo-header. the second register allows up to four protocols to be enabled with headers that are similar to icmp (no pseudo header). ip, udp, tcp, v4 icmp, and v6 icmp are automatically recognized and should not be specified again in these registers. each byte specifies a different protocol. length 32 bits type read/write address xxxx 16dc power on value x ? 00000000 ? restrictions processor state can only be set in diagnostic mode length 16 bits type read/write address xxxx 16e0 power on value x ? 0000 ? restrictions can only be written in diagnostic mode length 2x32 bits type read/write address checksum type: with header xxxx 16e4 checksum type: with no header xxxx 16e8 power on value x ? 00000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 347 of 676 rxaal functional description the following is a block diagram of rxaal: rxaal performs the cell and packet reassembly functions. this includes the aal processing and moving cell data and packet headers to packet memory. the nano-program uses state and configuration informations from the lcd cache to perform the necessary function for each cell. the nano-processor is capable of executing programs to run the following types of reassembly: aal5 aal3/4 raw cells non-user data (this might be the same as raw) packets mpeg fifo mode rxaal also performs the cell/packet post processing step. this includes event generation to rxque, cut through processing, scatter processing, and dma enqueues. rxaal block diagram rxlcd interface rxaal rxbuf interface aal nano processor rxque interface rxcrc interface dmaqs interface pm write interface
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 348 of 676 pnr25.chapt05.01 august 14, 2000 12.25: rxaal instruction array address port this register provides the read/write address for accessing the instruction array. when rxaal instruction array read/write port is read/written, this register is auto-incremented. when the last address is read/written, the address rolls over to zero. 12.26: rxaal instruction array read/write port provides read/write access to the instruction array. the instruction array contains a single nano-program. when this register is read/written, the address provided by r xaal instruction array address port is used to select the array word to be accessed. rxaal instruction array address port is auto-incremented on each read/write. thus, this port can be read/written multiple times to read/write the entire array. length 11 bits type read/write address xxxx 1704 power on value x ? 00000000 ? restrictions low two bits are always zero length 512 words x 24 bits type read/write address xxxx 1710 power on value x ? 00000000 ? restrictions none, but the instruction stream of an active nano-program should not be written
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 349 of 676 12.27: rxaal processor state selector allows user to select which data should be accessed with rxaal processor state read/write port. this register provides the encoded selector for accessing internal processor registers and state via reads/writes to the rxaal processor state read/write port. 12.28: rxaal processor state read/write port provides read/write access to the internal state of the processor. the internal processor state is externalized for debug and testing reasons. see the description of rxaal processor state selector on page 349 for definitions on the addresses. length 3 bits type read/write address xxxx 1718 power on value x ? 00000000 ? restrictions none bit(s) description 2-0 the following are the meanings of the encoded values: 000 accumulator register 001 header register 010 reserved 011 reserved 100 reserved 101 flags 110 reserved 111 instruction ptr length 32 bits type read/write address xxxx 171c power on value x ? 00000000 ? restrictions processor state can only be set in diagnostic mode.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 350 of 676 pnr25.chapt05.01 august 14, 2000 12.29: rxaal last lcd index register this register provides the previous lcd index that was used. length 16 bits type read/write address xxxx 1720 power on value x ? 0000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 351 of 676 12.30: rxaal transmit queue length compression configuration this register allows the user to configure how the transmit queue lengths should be compressed for use in the receive packet header. csked provides twelve transmit queue lengths specified in bytes. a 32-bit register (the bytes queued counters in csked) is available for the high, medium, and low priority queues for each of the four phy ports. using the full counts in the receive packet header generally uses too much room. this register allows the user to configure how this information should be compressed for use in the receive packet header. length 4 bits type read/write address xxxx 1730 power on value x ? 00000000 ? restrictions none bit(s) description 3-0 the following are the options: 0000 use the full register representation for port zero only (3 - 32 bit words) 0001 use the 2k scaled representation for port zero only (1 - 32 bit words) 0010 use the 4k scaled representation for port zero only (1 - 32 bit words) 0011 use the 8k scaled representation for port zero only (1 - 32 bit words) 0100 use the 16k scaled representation for port zero only (1 - 32 bit words) 0101 use the 32k scaled representation for port zero only (1 - 32 bit words) 0110 use the 64k scaled representation for port zero only (1 - 32 bit words) 0111 use the 128k scaled representation for port zero only (1 - 32 bit words) 1000 reserved 1001 use the 2k scaled representation for all ports (3 - 32 bit words) 1010 use the 4k scaled representation for all ports (3 - 32 bit words) 1011 use the 8k scaled representation for all ports (3 - 32 bit words) 1100 use the 16k scaled representation for all ports (3 - 32 bit words) 1101 use the 32k scaled representation for all ports (3 - 32 bit words) 1110 use the 64k scaled representation for all ports (3 - 32 bit words) 1111 use the 128k scaled representation for all ports. (3 - 32 bit words) for example, using option "0001," a single 32-bit word is used. the most significant byte contains the transmit queue length for the high priority queue for port zero divided by 2k bytes. if the scaled count overflows (greater than 2k*0xff), a value of 0xff is used. the next byte contains the scaled count for the medium priority queue, and the third byte contains the scaled count for the low priority queue. the least significant byte is not used. using option "1010" three 32-bit words are used. the first word contains the scaled counts for the high priority queue. the second word contains the scaled counts for the medium priority queue. the third word contains the scaled counts for the low priority queue. within each word, the first byte contains the scaled count for port zero, and the subsequent bytes are used for the other ports (1, 2, 3). the counts are divided by 4k in this case.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 352 of 676 pnr25.chapt05.01 august 14, 2000 12.31: rxaal packet header configuration allows user to configure the contents of each optional packet header word, and specify how many optional packet words are used. this register configures the contents of each optional packet header word in the optional portion of the packet header. there are four possible configurations, and the configuration used is selected with the packheadsel field in the receive lcd. the first three words of the packet header are fixed, and up to seven additional words can be configured. the low nibble of this register specifies how many optional packet header words are used, and the remaining nibbles of the register configure each packet header word if used. note: the base receive and transmit packet headers must be compatible if internal cell or packet routing is being used. the receive packet header becomes the transmit packet header in this scenario. user 0 and user 1 values can be used to place non-standard values in the packet header. these values are built by the nano-code, and are then placed in the packet header. in order to use these values, the nano-code must be customized. do this only under the advisement of ibm technical support. length 32 bits type read/write address config 0 xxxx 1740 config 1 xxxx 1744 config 2 xxxx 1748 config 3 xxxx 174c power on value x ? 00000000 ? restrictions none configure packet header word 3 configure packet header word 4 configure packet header word 5 configure packet header word 6 configure packet header word 7 configure packet header word 8 configure packet header word 9 reserved optional packet header words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 configure packet header word 3 27-24 configure packet header word 4 23-20 configure packet header word 5 19-16 configure packet header word 6 15-12 configure packet header word 7
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 353 of 676 12.32: rxaal error count register maintains a count of detected errors. this register maintains a count of error conditions that are detected. for example, crc errors and other protocol types of errors are counted. this count is useful when the chip is configured to only surface good packets. when this counter overflows, a counter overflow event is generated to rxque. 11-8 configure packet header word 8 7-4 configure packet header word 9 3reserved 2-0 specifies how many optional packet header words to use. each nibble specifies what should be selected for the corresponding packet header word. the following are the options: 0000 start timestamp 0001 end timestamp 0010 atm header 2 0011 host data 0100 vba - virtual buffer address 0101 transmit queue length word 0 0110 transmit queue length word 1 0111 transmit queue length word 2 1000 user 0 1001 user 1 1010 aal5 trailer, two user bytes and the length 1011 vba with the number of header bytes in the low 10 bits 1100 reserved length 32 bits type read/write address xxxx 1734 power on value x ? 00000000 ? restrictions none bit(s) description
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 354 of 676 pnr25.chapt05.01 august 14, 2000 12.33: rxaal dropped count register this register maintains a count of packets that are dropped due to a lack of resource. for example, if no pools buffer (real or virtual mode) is available, the packet is dropped and this counter is incremented. this count is useful when the chip is configured to only surface good packets. when this counter overflows, a counter overflow event is generated to rxque. 12.34: rxaal maximum sdu length register specifies the maximum sdu size for a packet. this register contains the maximum sdu size for a packet. this size includes only the protocol data length of the packet. for example, this length would be compared with the aal5 length field in the aal5 trailer. when a packet is completely received, this register is used to make sure it does not exceed the msdu specified. 12.35: rxaal oam lcd information register this register specifies the reassembly information for oam cells. the format of this register is equivalent to word zero of the receive lcd. the following fields are valid: ppmode, size, storecrc10, rxqnum, rxpoolid, rxoffset, and cutthrusel. refer to the format of lcd word zero for the raw receive lcds. length 32 bits type read/write address xxxx 1738 power on value x ? 00000000 ? restrictions none length 18 bits type read/write address xxxx 173c power on value x ? 0000ffff ? restrictions none length 32 bits type read/write address xxxx 172c power on value x ? 0000ffff ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 355 of 676 12.36: rxall - scatter/cut through info registers these registers specify the scatter/cut through configurations. a configuration is selected in the lcd via the cut through selector field when doing cut through/scatter mode. a configuration consists of three registers. the first two registers, described here, define the four possible configurations for scatter/cut through. the third register, rxall - scatter/cut through flag registers, is described in "rxall - scatter/cut through flag registers. the first register, one of cti(0-3), is defined as follows: 12.36.1: scatter/cut through info register 1 length 32 bits type read/write address config 0 xxxx 1750 config 1 xxxx 1754 config 2 xxxx 1758 config 3 xxxx 175c config 4 xxxx 1770 config 5 xxxx 1774 config 6 xxxx 1778 config 7 xxxx 177c power on value x ? 00000000 ? restrictions none enable single page mode enable double deq enable header addresses enable optional header addresses vent source dmaqs rxque to deq header header page size rxque to deq optional enable split header mode optional header page size rxque to deq page enable page addresses page size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 enable single page mode 30 enable double deq for packet header buffers to get virtual addresses 29 enable header addresses vs. descriptor (1->addresses 0->descriptor) 28 enable optional header addresses vs. descriptor (1->addresses 0->descriptor)
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 356 of 676 pnr25.chapt05.01 august 14, 2000 27-26 event source: specify how the event data (if any) is formed. normally, the dma descriptor is used for dma events, but when the entire dma descriptor is built there is no descriptor address to use. the following sources are possible: 00 use dma descriptor address (dma queue address where built) 01 use source address 10 use destination address 25-24 dmaqs dma queue to enqueue dma descriptor to 23-20 rxque to deq header dma descriptor addresses from 19-16 header page size: specifies the page size of the buffer that the header is dmaed into. the following encodings are used: 0 128 bytes 1 256 bytes 2 512 bytes 3 1k bytes 4 2k bytes 5 4k bytes 6 8k bytes 7 6k bytes 8 32k bytes 9 64k bytes 15-12 rxque to deq optional header dma descriptor addresses from 11 enable split header mode (optional header buffer) 10-8 optional header page size: specifies the page size of the buffer that the header is dmaed into. the following encodings are used: 0 64 bytes 1 128 bytes 2 256 bytes 3 512 bytes 4 1k bytes 5 2k bytes 6 4k bytes 7 8k bytes 7-4 rxque to deq page dma descriptor addresses from 3 enable page addresses vs. page descriptor 2-0 page size: specifies the page size of the page buffers that the scatter pages are dmaed into. the following encodings are used: 0 512 bytes 1 1k bytes 2 2k bytes 3 4k bytes 4 8k bytes 5 16k bytes 6 32k bytes 7 64k bytes bit(s) description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 357 of 676 12.36.2: scatter/cut through info register 2 length 32 bits type read/write address config 0 xxxx 1750 config 1 xxxx 1754 config 2 xxxx 1758 config 3 xxxx 175c config 4 xxxx 1770 config 5 xxxx 1774 config 6 xxxx 1778 config 7 xxxx 177c power on value x ? 00000000 ? restrictions none reserved packet header optional header page deq size enable double deq for optional header enable double deq for page buffers enable header only dma optional header flags 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-22 reserved. 21 packet header deq size: 0 = 32 bit, 1 = 64 bit 20 optional header deq size: 0 = 32 bit, 1 = 64 bit 19 page deq size: 0 = 32 bit, 1 = 64 bit 18 enable double deq for optional header buffers to get virtual addresses 17 enable double deq for page buffers to get virtual addresses 16 enable header only dma. when set, only the header bytes as specified in the lcd or from rxcrc will be dmaed along with the dma list and packet header 15-0 optional header flags. these flags are used when dmaing the optional header page.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 358 of 676 pnr25.chapt05.01 august 14, 2000 12.37: rxall - scatter/cut through flag registers use to specify the scatter/cut through flags. these registers specify the scatter/cut through flags. a flag regis- ter is selected in the lcd via the cut through selector field when doing cut through/scatter mode. the flags are used when building dma descriptors for scatter pages and the first scatter buffer (packet header, dma list, etc.). length 32 bits type read/write address config 0 xxxx 1760 config 1 xxxx 1764 config 2 xxxx 1768 config 3 xxxx 176c power on value x ? 00000000 ? restrictions none header flags page flags 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-16 header flags these flags are used when dmaing the packet header, dma list, and header bytes from the packet. 15-0 page flags these flags are used when dmaing a scatter page (other than the header page).
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 359 of 676 rxlcd functional description rxlcd provides an lcd cache for reasm sub-entities. this cache holds the last four receive lcds. the sub-entities can request to load an lcd, read the lcd words, and update parts of the lcd. 12.38: rxlcd cache data array address port this register provides the read/write address for accessing the lcd cache data array. when the rxlcd cache data array read/write port is read/written, this register is auto-incremented. when the last address is read/written, the address rolls over to zero. the cache is organized as 64 32-bit words. each 16 words comprises an lcd. the first four words and the last word of each lcd do not contain valid data and can not be written. these locations return zero on reads. rxlcd block diagram length 6 bits type read/write address xxxx 1780 power on value x ? 00000000 ? restrictions the low two bits are always zero rxlcd rxcrc lcd cache cm read/write interface rxaal rxrto rxxlt interface interface interface interface
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 360 of 676 pnr25.chapt05.01 august 14, 2000 12.39: rxlcd cache data array read/write port provides read/write access to the lcd cache data array. when this register is read/written, the address provided by rxlcd cache data array address port is used to select the array word to be accessed. rxlcd cache data array address port is auto-incremented on each read/write so this port can be read/written multi- ple times to read/write the entire array. the cache is organized as 64 32-bit words. each 16 words comprises an lcd. the first four words and the last word of each lcd do not contain valid data and can not be written. these locations return zero on reads. 12.40: rxlcd cache line info registers these registers provide the cache line tags, valid, and dirty bits. there is a register for each of the four cache lines. length 64 words x 32 bits type read/write address xxxx 1788 power on value x ? 00000000 ? restrictions must be in diagnostic mode to read/write the cache length 4 x 32 bits type read/write address xxxx 17a0-7ac power on value x ? 00000000 ? restrictions must be in diagnostic mode to write these registers valid dirty lru reserved lcd index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 valid 30-20 dirty bits 19-17 lru bits 16 reserved 15-0 lcd index
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 361 of 676 12.41: rxlcd mode register this register provides a means to control cache operation. length 1 bit type read/write address xxxx 17b8-7bc power on value x ? 00000000 ? restrictions none bit(s) name description 0 flush all entries when set, all dirty entries are flushed to memory but remain in the cache. this bit will reset when the operation is complete.
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 362 of 676 pnr25.chapt05.01 august 14, 2000 rxrto functional description rxrto performs periodic reassembly timeout processing and lcd update operations. reassembly timeout (rto) processing reassembly timeout processing is generally an aal5 operation. it is supported for other lcd types as well. it can be enabled on an lcd basis by turning on the rto enable bit in the lcd. the following registers also need to be properly set up to run rto processing: rxrto rto lcd table bound registers rxrto reassembly timeout value register rxrto reassembly timeout pre-scaler register see the register descriptions for more register details. the lcd table registers define the lcd table that the rto process examines. the value register is used as a compare value against a counter that counts based on a pre-scaler. each time the registers compare, rto processing is started for a single lcd and the time base is reset. rto processing checks the rto test and set bit. if it is reset, it sets it and continues. if it is set, then a timeout occurs and the lc is placed in error state and the current packet is surfaced to the user via an event. any resource associated with the packet must be recovered by software. for example, if the lcd is setup to use scatter mode, then there may be scatter dma pages in the dma list that need to be returned to the proper receive queue. the rto bit is reset with each inbound cell received. an lcd needs to be touched twice to cause a timeout (once to set it and once to detect that it is already set). the time base starts running as soon as the rto processing is complete. thus, rto processing is a low priority task. shutting down an lcd to shut down a receive lcd, the following steps should be followed: clear the entry for this lcd in the lcd table (to stop receiving cells for this lcd) do an lcd update operation that sets lcd state to down read the lcd r easm ptr if reasm ptr is non-zero and lcd is set up to do cut through, be sure to free any dma descriptor that was added with cut through operation if reasm ptr is non-zero and lcd is set up to do scatter, be sure to free any pages in the dma list if reasm ptr is non-zero, free it to pools rxrto block diagram rxrto rto nano processor pm read/write interface rxlcd interface rxque pools interface interface
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 363 of 676 12.42: rxrto lcd update data registers these two registers are used to specify data to write into the receive lcd on the update lc operation. they contain the data used in the lc update operation. for more information on their use, see the rxrto lcd update op registers on page 364. the update date register changes to contain the updated data written to the lc word while the operation is completing. the second set of lcd update registers is meant for the core to use, but is available for general use. 12.43: rxrto lcd update mask registers these two registers are used to specify which data to write into the lcd on the update lc operation. they contain the mask used in the lc update operation. for more information on their use, see the rxrto lcd update op registers on page 364. the second set of lcd update registers is meant for the core to use, but is available for general use. length 32 bits type read/write address update 1 register xxxx 17c0 update 2 register xxxx 17d0 power on value x ? 00000000 ? restrictions none length 32 bits type read/write address update 1 register xxxx 17c4) update 2 register xxxx 17d4 power on value x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary cell/packet re-assembly (reasm) page 364 of 676 pnr25.chapt05.01 august 14, 2000 12.44: rxrto lcd update op registers used to specify the lcd word to update. this operation is used to update a portion of the receive lcd. if this operation is not used, then software or the IBM3206K0424 updates of the lcd may be lost because the receive lcd is cached in the IBM3206K0424. this register is written with the address of the lcd word to update. once this register is written the update operation starts. all subsequent reads or writes to the data, mask, or update registers are held off until the operation completes. a read-modify-write will occur to update the portion specified by the mask with the masked value in the data register. normally this register would not be read. however, if it is read then the low order bit is read as ? 0 ? and the next lowest order bit (bit 1) is read as the busy bit. this signifies whether an operation is still going on. if an opera- tion is still going on, then a new write to any of the data, mask, or update operation registers is held off until the original operation is complete. the second set of lcd update registers is meant for the core to use, but is available for general use. 12.45: rxrto rto lcd table bound registers used to specify the lower/upper bounds of the lcd table. the lower bound should be initialized to the lcd index of the first lcd in the lcd table if reassembly timeout processing is to be done. the upper bound should be initialized to the lcd index of the last lc in the lc table if reassembly timeout processing is to be done. length 32 bits type read/write address update 1 register xxxx 17c8 update 2 register xxxx 17d8 power on value x'00000000' restrictions the low order two bits are not writable length 16 bits type read/write address lower bound 1 register xxxx 17e0 upper bound 1 register xxxx 17e4 lower bound 2 register xxxx 17f0 upper bound 2 register xxxx 17f4 power on value x'00000000' restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 cell/packet re-assembly (reasm) page 365 of 676 12.46: rxrto reassembly timeout value register used to specify the time interval used for reassembly timeout processing. this register is the number of pre-scaler intervals between reassembly processing. the pre-scaler interval is determined by rxrto reassembly timeout pre-scaler register. a single lc is checked for reassembly timeout during each reassembly processing interval. when this register is set to ? 0 ? , reassembly timeout processing is disabled. for more information on how reassembly timeout conditions are processed see reassembly timeout (rto) processing on page 362. 12.47: rxrto reassembly timeout pre-scaler register used to specify the time interval of each rto timer tick. this register determines the number of 15 ns inter- vals between rto timer ticks. the value in the register plus 1 is the number of 15 ns intervals between rto timer ticks. thus, the default value of ? 0 ? means that the rto timer ticks every 15 ns. if a value of nine is placed in this register, the rto timer ticks every 150 ns (10 * 15 ns). for more information on how reassembly timeout conditions are processed, see reassembly timeout (rto) processing on page 362. length 32 bits type read/write address timeout 1 register xxxx 17e8 timeout 2 register xxxx 17f8 power on value x'00000000' restrictions none length 16 type read/write address prescale 1 xxxx17ec prescale 2 xxxx 17fc power on value x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 366 of 676 pnr25.chapt05.01 august 14, 2000 entity 13: receive queues (rxque) functional description rxque has a single function: to manage the receive queues for software by providing an easy to use primi- tive interface. when talking about the receive queues, the term rxq is used to talk about a receive queue, and the term deq is used to refer to a dequeue operation, and the term enq is used to refer to an enqueue opera- tion. receive queue interface a group of sixteen receive queues is available for software use. the receive queues hold events or user specified data. each queue entry (event) is either 32 or 64 bits and contains two fields: event-identifier and event-informa- tion. the seven least significant bits in the entry contain the event-identifier field. the most significant bits in the entry comprise the event-information field. warning: in order to maintain the atomicity of 64-bit atomic transfers, the user must ensure that 64-bit trans- fers are bus atomic within the particular bus system in which IBM3206K0424 is being used. the event information typically contains a pointer (when low order bits are zeroed) to a packet buffer, a cell buffer, or an lcd. it can also contain a dma descriptor address or user-specified data. event summary and routing information on page 367 lists the different event types.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 367 of 676 event summary and routing information (page 1 of 3) event number description event information error count tx comp abr pools 0000000 = 00 aal5 packet event (packet complete) packet/lcd 0000001 = 01 aal5 packet header event (packet start) packet 0000010 = 02 aal5 packet with bad crc packet/lcd x 0000011 = 03 aal5 packet with bad length field packet/lcd x 0000100 = 04 aal5 packet that exceeds maximum length in lc packet/lcd x 0000101 = 05 aal5 packet timeout packet/lcd x 0000110 = 06 aal5 packet forward abort packet/lcd x 0000111 = 07 aal5 packet cpi field not equal to zero packet/lcd x 0001110 = 0e aal5 fifo packet packet 0001000 = 08 cell event (user data) packet/lcd 0001001 = 09 nud cell event (non-user data) packet/lcd 0001010 = 0a nud cell with bad crc-10 packet/lcd x 0001011 = 0b bad cell - bad hec packet x 0001100 = 0c bad cell - out of range packet x 0001101 = 0d bad cell - index equal zero packet x 0010000 = 10 aal0 cell dropped - lack of pools buffers lcd x 0010001 = 11 aal5 cell dropped - lack of pools buffers lcd x 0010010 = 12 oam cell dropped - lack of pools buffers lcd x 0011000 = 18 total user cells receive counter overflow lcd x 0011001 = 19 total user cells rx clp=0 counter overflow lcd x 0011010 = 1a total user cells tx counter overflow lcd x 0011011 = 1b total user cells tx clp=0 counter overflow lcd x 0011100 = 1c threshold 1 crossed - down lcd x 0011101 = 1d threshold 1 crossed - up lcd x 0011110 = 1e threshold 1 crossed - down lcd x 0011111 = 1f threshold 2 crossed - up lcd x 0100000 = 20 transmit complete packet x 0100001 = 21 transmit complete buffer freed packet/lcd x 0100010 = 22 "bad" found in first word of packet packet x 0100011 = 23 connection closed lcd x 0100100 = 24 transmit dma complete descriptor 0100101 = 25 receive dma complete descriptor 0100110 = 26 transmit dma complete with error descriptor 0100111 = 27 receive dma complete with error descriptor 0101000 = 28 transmit dma complete with virtual error descriptor
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 368 of 676 pnr25.chapt05.01 august 14, 2000 0101001 = 29 zero address in dma descriptor src/dst address descriptor 0101010 = 2a transmit buffer allocated 0101100 = 2c adtf event lcd x 0101101 = 2d crm event lcd x 0101110 = 2e ccr=0 event lcd x 0101111 = 2f rm cell event packet x 0110000 = 30 user event 0110001 = 31 user event 0110010 = 32 user event 0110011 = 33 user event 0110100 = 34 user event 0110101 = 35 user event 0110110 = 36 user event 0110111 = 37 user event 0111000 = 38 virtual memory resource event packet/lcd x 0111001 = 39 buffer overflow event packet/lcd x 0111010 = 3a no dma descriptor for aal7 packet packet/lcd x 0111011 = 3b dma canceled for aal7 packet due to error descriptor 0111100 = 3c no scatter pages available and packet complete packet/lcd x 0111101 = 3d entity counter overflow event counter x 0111110 = 3e pools status event status x 1000000 = 40 frame event (good frame) 1000001 = 41 frame event (error) x 1000010 = 42 frame event (protocol error) x 1000011 = 43 frame event (dropped - lack of buffers) x 1000100 = 44 frame event (reserved) 1000101 = 45 frame event (reserved) 1000110 = 46 frame event (reserved) 1000111 = 47 frame event (reserved) 1010000 = 50 pcore event 1010001 = 51 pcore event 1010010 = 52 pcore event 1010011 = 53 pcore event 1010100 = 54 pcore event 1010101 = 55 pcore event event summary and routing information (page 2 of 3) event number description event information error count tx comp abr pools
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 369 of 676 1010110 = 56 pcore event 1010111 = 57 pcore event 1011000 = 58 reasm counter-overflow event counter x 1011001 = 59 segbf counter-overflow event counter x 1011100 = 5c system - receive queue event (start of buffer) previous lower bound 1011101 = 5d system - receive queue event (end of buffer) next lower bound 1011110 = 5e timestamp event timestamp 1011111 = 5f 64-bit timestamp event timestamp 1100100 = 64 tx dma complete descriptor 1100101 = 65 rx dma complete descriptor 1100110 = 66 tx dma complete with error descriptor 1100111 = 67 rx dma complete with error descriptor 1101000 = 68 tx dma complete with virtual error descriptor 1101001 = 69 zero address in dma descriptor src/dst address descriptor event summary and routing information (page 3 of 3) event number description event information error count tx comp abr pools
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 370 of 676 pnr25.chapt05.01 august 14, 2000 aal5 packet events for aal5 packet events, the event specifies the packet buffer address, and the event type field specifies the type of packet event. the following event types are defined: bit(s) name description 0x00=0000000 normal aal5 packet event (packet complete) this event specifies that an aal5 packet was received and has passed all aal5 protocol checks (crc, length). the event information contains a pointer to the packet. 0x0e=0001110 normal aal5 fifo packet event this event specifies that an aal5 fifo packet was received and has passed all aal5 protocol checks (crc, length, ...). the event information contains a pointer to the packet. 0x01=0000001 normal aal5 packet header threshold event (packet start) this event specifies that the aal5 packet header threshold was exceeded as set in the lcd. the event information contains a pointer to the packet header, and the user can access up to the packet header threshold bytes of data. 0x02=0000010 aal5 packet with bad crc was rx on lc this event specifies that an aal5 packet was received and the aal5 crc is bad. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x03=0000011 aal5 packet with bad length field was rx on lc this event specifies that a aal5 packet was received and the aal5 length field is bad. for example, there is too much data or not enough, but typically the bad crc is detected first. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x04=0000100 aal5 packet that exceeds max len in lc was rx this event specifies that an aal5 packet was received but the amount of data has exceeded the maximum length as specified in the lcd or in the msdu register. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x05=0000101 aal5 packet timeout on this lc this event specifies that a reassembly timeout has occurred for an aal5 packet that was being reassembled. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x06=0000110 aal5 packet forward abort this event specifies that an aal5 packet was terminated with a forward abort. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x07=0000111 aal5 packet cpi field not equal to zero this event specifies that a aal5 packet was received and the aal5 cpi field was not set to ? 0 ? which is an aal5 protocol violation. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 371 of 676 cell events for aal0 events, the event specifies a cell buffer address, and the event type field specifies type of aal0 event. the following event types are defined: bit(s) name description 0x08=0001000 aal0 cell event this event specifies that an aal0 (non-fifo mode) cell was received. the event information contains a pointer to the cell. 0x09=0001001 non-user data cell event this event specifies that a non-user data cell was received and the crc-10 was good if checking was enabled. the event information contains a pointer to the cell. 0x0a=0001010 non-user data cell with bad crc-10 event this event specifies that a non-user data cell was received and the crc-10 was bad. the event information contains either a pointer to the cell if receiving bad frames, or a pointer to the lcd on which this cell was received. 0x0b=0001011 cell with bad hec event this event specifies that a cell was received with a bad hec. the event informa- tion contains a pointer to the cell. 0x0c=0001100 cell with vp/vc out of range event this event specifies that a cell was received with a vp/vc that was out of range. the event information contains a pointer to the cell. 0x0d=0001101 cell with vc index equal zero this event specifies that a cell was received with a vc index equal zero. the event information contains a pointer to the cell.
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 372 of 676 pnr25.chapt05.01 august 14, 2000 lc events for lc events, the event specifies a lc, and the event type field specifies what happened on the lc. the following event types are defined: abr events the following events are used for abr processing and are routed to the receive queue specified in the abr event routing register. bit(s) name description 0x10=0010000 aal0 cell was dropped due to lack of pools buffers this event specifies that a aal0 (non-fifo mode) cell was received, but was dis- carded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x11=0010001 aal5 cell was dropped due to lack of pools buffers this event specifies that the first aal5 cell for a packet was received, but was dis- carded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x12=0010010 non-user data cell was dropped due to lack of pools buffers this event specifies that a non-user data cell was received, but was discarded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x17=0010111 reserved reserved 0x18=0011000 lc total user cells rx counter overflow this event specifies that the tuc rx counter in the lcd has overflowed. the event information contains a pointer to the lcd. 0x19=0011001 lc total user cells clp=0 rx counter overflow this event specifies that the tuc w/clp=0 rx counter in the lcd has overflowed. the event information contains a pointer to the lcd. 0x1a=0011010 lc total user cells tx counter overflow this event specifies that the tuc tx counter in the lcd has overflowed. the event information contains a pointer to the lcd. 0x1b=0011011 lc total user cells clp=0 tx counter overflow this event specifies that the tuc w/clp=0 tx counter in the lcd has overflowed. the event information contains a pointer to the lcd. bit(s) name description 0x2c=0101100 adtf event this event specifies that the adtf timer expired. the event information contains a pointer to the lcd. 0x2d=0101101 crm event this event specifies that the crm count has been exceeded. the event informa- tion contains a pointer to the lcd. 0x2e=0101110 ccr = 0 event this event specifies that ccr = 0. the event information contains a pointer to the lcd. 0x2f=0101111 rm cell rx-ed this event specifies that a rm cell was received. the event information contains a pointer to the receive buffer.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 373 of 676 miscellaneous events bit(s) name description 0x1c=0011100 thresh 1 event - down this event specifies that a memory management threshold was crossed down- wards. the event information contains the lcd address. 0x1d=0011101 thresh 1 event - up this event specifies that a memory management threshold was crossed upwards. the event information contains the lcd address. 0x1e=0011110 thresh 2 event - down this event specifies that a memory management threshold was crossed down- wards. the event information contains the lcd address. 0x1f=0011111 thresh 2 event - up this event specifies that a memory management threshold was crossed upwards. the event information contains the lcd address. 0x20=0100000 transmit complete this event specifies that a packet/cell was successfully transmitted. the event information contains a pointer to the buffer transmitted. 0x21=0100001 transmit complete buffer freed this event specifies that a packet/cell was successfully transmitted and the buffer was freed back to pools. the event information contains a pointer to the buffer transmitted. 0x22=0100010 transmit bad this event specifies that a packet was to be transmitted, but the buffer was marked as bad, so was canceled. this is caused by getting a page fault when dmaing into the transmit packet buffer. the event information contains a pointer to the bad buffer. 0x23=0100011 connection closed this event specifies that all packets for the given lcd have been transmitted. the event information contains the lcd address. 0x24=0100100 tx dma complete (into IBM3206K0424) this event specifies that a tx dma completed successfully. the event information depends on how the dma was set up. event-identifier 0x64 is an alias. 0x25=0100101 rx dma complete (out of IBM3206K0424) this event specifies that an rx dma completed successfully. the event informa- tion depends on how the dma was set up. event-identifier 0x65 is an alias. 0x26=0100110 tx dma complete with error (into IBM3206K0424) this event specifies that a tx dma had errors. the event information depends on how the dma was set up. event-identifier 0x66 is an alias. 0x27=0100111 rx dma complete with error (out of IBM3206K0424) this event specifies that an rx dma had errors. the event information depends on how the dma was set up. event-identifier 0x67 is an alias. 0x28=0101000 tx dma complete with virtual error this event specifies that a tx dma had a virtual error. the remainder of the dma descriptor was cancelled. the event information contains the dma descriptor address. event-identifier 0x68 is an alias. 0x29=0101001 dma desc has zero address this event specifies that a dma descriptor source destination address was zero. the remainder of the dma descriptor was cancelled. the event information con- tains the dma descriptor address. event-identifier 0x69 is an alias. 0x2a=0101010 transmit-buffer allocated 0x30=0110000 user defined 0x31=0110001 user defined 0x32=0110010 user defined 0x33=0110011 user defined 0x34=0110100 user defined 0x35=0110101 user defined 0x36=0110110 user defined 0x37=0110111 user defined
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 374 of 676 pnr25.chapt05.01 august 14, 2000 0x38=0111000 virtual memory resource event this event specifies that an aal5 cell was received, but could not be written into the buffer because a virtual memory boundary was crossed and a buffer was not available to fill in the next segment. this can also happen if the cell crosses a boundary that would make the buffer larger than the virtual buffer size. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x39=0111001 buffer overflow event this event specifies that an aal5 cell was received, but could not be written into the buffer because it would exceed the real buffer size. the event information con- tains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x3a=0111010 no dma desc for aal7 packet event this event specifies that an aal7 (aal5 with cut through) packet was completed, but no dma descriptors were available to dma the packet header. the event infor- mation contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x3b=0111011 dma cancelled for aal7 packet due to error event this event specifies that a dma descriptor enqueued with a cut-through operation was cancelled because an error condition was detected with the packet (crc, length,...). the event information contains the system descriptor address that was cancelled. 0x3c=0111100 no pages available for aal5 scatter packet this event specifies that an aal5 packet completed with no errors, but there was a lack of scatter buffers to complete the scatter dma. the user must interrogate the partial dma list in the packet header to recover the system pages. once this is done, the packet should be freed. the user can alternately treat this as a good packet and complete the packet processing by setting up additional dmas to move the remaining data to system pages. the event information contains the IBM3206K0424 buffer address. 0x3d=0111101 IBM3206K0424 counter overflow event this event specifies that a counter overflow event has been raised. the event information specifies which counter overflowed. multiple counter overflows can be specified with a single event. the following is the definition of the event informa- tion: bit 27 gpdma write dma byte count overflow bit 26 gpdma read dma byte count overflow bit 25 rxque timestamp counter overflow bit 24 pcint performance counter 1 overflow bit 23 pcint performance counter 2 overflow 0x3e=0111110 pools status event this event specifies that a pools status event has been raised. the event infor- mation contains the status. see buffer pool management (pools) on page 247 for the definition. 0x5e=1011110 timestamp event this event specifies that a timestamp event has been placed ahead of next event. the event information contains the timestamp. 0x5f=1011111 64-bit timestamp event this event specifies that a timestamp event has been placed ahead of next event. the most significant word in the event-information field contains the full 32-bit timestamp. miscellaneous events (continued) bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 375 of 676 the receive queues are maintained by rxque with the following operations being available to software: dequeue - remove the entry at the head of the queue enqueue - add arbitrate entry at the tail of the queue the following figure shows how events in a receive queue link to other data structures including lc control blocks, packet buffers, and cell buffers. frame-based events bit(s) name description 0x40=1000000 frame event (good frame) 0x41=1000001 frame event (error) 0x42=1000010 frame event (protocol error) 0x43=1000011 reserved (dropped - lack of buff- ers) 0x44=1000100 reserved 0x45=1000101 reserved 0x46=1000110 reserved 0x47=1000111 reserved pcore events bit(s) name description 0x50=1010000 pcore event 0x51=1010001 pcore event 0x52=1010010 pcore event 0x53=1010011 pcore event 0x54=1010100 pcore event 0x55=1010101 pcore event 0x56=1010110 pcore event 0x57=1010111 pcore event 0x58=1011000 reasm counter-overflow event this specifies that reasm raised counter-overflow event. the event information specifies which counter overflowed. 0x59=1011001 segbf counter-overflow event this specifies that segbf raised counter-overflow event. the event information specifies which counter overflowed. system-receive-queue events bit(s) name description 0x5c=1011100 system-receive-queue start-of-buffer event 0x5d=1011101 system-receive-queue end-of-buffer event
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 376 of 676 pnr25.chapt05.01 august 14, 2000 general queue, event, and data structure linkage status 1c raw packet 1c info raw cell header data packet header data event event event event event event 1c cb head ta i l
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 377 of 676 rxque structure each queue has a number of registers that define the queue and its behavior: rxque initialization to set up a receive queue, at least two pieces of information are needed. the first is the receive queue ? s set of properties, and the second is its base address. the following restrictions should be taken into account when setting up a queue: the properties register must be set up before the lower-bound and next-lower-bound registers can be set up. the lower bound and next lower bound must be at least 1k aligned. the low order 10 bits of these regis- ters are not writable, so the minimum physical size of a receive queue is 1024 bytes (256 32-bit entries). the alignment should correspond to the size specified in the properties register. the head and tail pointers are initialized when the lower bound register is written. these registers are only writable for diagnostic purposes. the threshold is level sensitive, so as long as the queue length is greater than or equal to the threshold, the appropriate status bit is driven. all registers, except the threshold and next-lower-bound registers, can only be written in diagnostic mode and are intended to only be written once when they are set up. lower bound pointer to starting address of queue's buffer properties indicates the queue's size, type, and behavior head pointer pointer to head of queue tail pointer pointer to the next free entry in queue - points to head if queue is full or empty queue length current length of the queue threshold length threshold used to generate interrupts next lower bound pointer to starting address of a system receive queue's next buffer
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 378 of 676 pnr25.chapt05.01 august 14, 2000 rxque event routing events are routed to a receive queue based on the current event type and mode of the chip. events fall into these categories: normal events error events counter events transmit complete events dma events (tx/rx) abr events pools status events see event summary and routing information on page 367 to see how the different events are categorized. all events other than normal, dma, and error events are routed using the corresponding rxque event routing registers. normal events are always routed to the receive queue specified in the receive portion of the lcd. dmaqs specifies the route for all dma events. error events are special, in that they are routed based on the values of the "receive bad frame mode ? bit and the "always route error events" mode bit in rxque control register. if the ? always route error events ? bit is on, then the error events are always routed to the error queue. otherwise, if the receive bad frame mode is on, then the error events are routed to the receive queue specified in the receive portion of the lcd just like a normal event would be. when receive bad frames is off, then the error events are routed to the error queue.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 379 of 676 rxque normal operation this section describes how to use the receive queues (rxq) and the rxq operations. the receive queue contains events for the end user to process. these events are obtained by the user by executing the rxq deq operation. the user can be notified of new events by setting up the threshold and inter- rupt enable registers appropriately. otherwise, the rxq length register can be polled to check for events. the deq operation is executed by reading the deq register address for the appropriate rxq. the event at the head of the queue is returned and the event is removed from the queue. some events have a packet/cell buffer associated with it. this buffer is owned by the user, and it is the users responsibility to free this buffer. the following pseudo code illustrates how an rxq could be processed: rxque queue full operation when a receive queue is full (length is equal to maximum length), the appropriate status bit is set. when a queue is full, all subsequent events are flushed until room is available in the receive queue. if a buffer was associated with the event and the rxque-properties-register bit disable auto-free is not set, then that buffer is freed back to pools. when an event is dropped, the event dropped status bit is set and the event data that was dropped can be found in rxque last event dropped register. the rxque last event dropped register will not be changed until the event dropped status bit is cleared. it is not good to let a receive queue become full. rxque dequeue event loop // rxq was polled or int ocurred to get here event = rxque->deq; // read an event from rxq if (event neq 0) { // need to check for null event eventtype = event & 0x7f; // calc event type event = event & ~(0x7f); // calc lc or buffer ptr switch (eventtype) { case(event1): processsimpleevent1(event); break; case(event2): processsimpleevent2(event); break; case(eventx): processsimpleeventx(event); break; } }
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 380 of 676 pnr25.chapt05.01 august 14, 2000 rxque event timestamping when timestamp mode is set in the rxque control register, events are timestamped. when timestamping is enabled, a timestamp event is placed in the corresponding rxq followed by the actual event. the event information of the timestamp event carries the timestamp. the timestamp is determined from the rxque timestamp register, rxque timestamp pre-scaler register, and the rxque timestamp shift register. if the corresponding rxq is full, both events are dropped. it is possible to lose only the timestamp event or lose the actual event depending on the length of the queue and the timing of the dequeue operations. rxque system receive queues to set up a system receive queue, set the "diagnostic-mode" bit in the rxque control register. next, set the system receive queue bit in the rxque properties register. load the upper bound and size of event fields, as well. after this, allocate two identical buffers in system memory. let each buffer be large enough to contain n events (the upper bound field prescribes the value n) and initialize both to all zeros. write one buffer ? s starting address into the rxque lower bound register (lobr), and write the other ? s starting address into the rxque next lower bound register (nlbr). finally, reset the diagnostic mode bit in the rxque control register. system-receive-queue setup is complete. the first event enqueued to a system receive queue causes rxque to begin filling the buffer which lobr references. rxque fills the buffer ? s first entry with a "system-receive-queue start-of-buffer" event whose information is the value ? 0 ? . after this, rxque fills the buffer's second entry with the enqueued event and writes the value ? 2 ? into the rxque length register (lenr). the second event enqueued to the system receive queue causes rxque to fill the buffer's third entry and write the value ? 3 ? into lenr. the third event enqueued to the system receive queue causes rxque to fill the buffer's fourth entry and write the value ? 4 ? into lenr. this continues until lenr contains the value ? n-1 ? . at that time, rxque fills the buffer's nth entry with a system-receive-queue end-of-buffer event whose information is the value in nlbr. after this, rxque begins filling the buffer which nlbr references. rxque fills its first entry with a "system-receive-queue start-of-buffer" event whose information is the value in lobr. after this, rxque copies the contents of nlbr into lobr and writes the value ? 1 ? into lenr. finally, rxque writes the value ? 0 ? into nlbr. subse- quent events enqueued to the system receive queue f ill the buffer which lobr references. to prevent the system receive queue from becoming full, write a non-zero value into nlbr. the system receive queue becomes full when the value in lenr becomes ? n-1 ? while nlbr contains the value ? 0 ? . at that time, rxque fills the buffer's nth entry with a system-receive-queue end-of-buffer event whose information is the value ? 0 ? . rxque writes the value n into lenr and preserves the contents of lobr while dropping subsequent enqueued events. to restart the system receive queue from the "full" state, write a non-zero value into nlbr. after restarting, the next event enqueued to the system receive queue causes rxque to begin filling the buffer which nlbr references. rxque fills the buffer's first entry with a system-receive-queue start-of-buffer event whose information is the value preserved in lobr. rxque fills the buffer's second entry with the enqueued event. after this, rxque copies the contents of nlbr into lobr and writes the value ? 2 ? into lenr. finally, rxque writes the value ? 0 ? into nlbr. subsequent events enqueued to the system receive queue f ill the buffer which lobr references. to prevent the system receive queue from becoming full, write a non-zero value into nlbr. the rxque queues' status register bit "threshold exceeded" indicates that the value in lenr is greater than or equal to the value in the rxque threshold register while nlbr contains the value ? 0 ? . to reset this
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 381 of 676 status bit, write a non-zero value into nlbr. events enqueued to a system receive queue may not be dequeued via the rxque dequeue register. to dequeue from a system receive queue, poll system memory directly. a buffer ? s entry is filled if its value is non-zero. rxque synchronizes its internal-register operations with the initiation, rather than completion, of its system-memory operations. therefore, the state of system memory lags the state of rxque.
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 382 of 676 pnr25.chapt05.01 august 14, 2000 13.1: rxque lower bound registers these registers specify the lower bound of the corresponding receive queue data structure. the head and tail of the receive queue are initialized when this register is written. when the receive queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the receive queue as a circu- lar buffer. when this register is written, the corresponding receive queue is essentially reset. this is because the head, tail, and length of the queue are all reset. the length of the rxque lower bound register is 64 bits if all three conditions, below, are met; otherwise, the length is 32 bits. system receive-queue in the rxque properties register is set. system-memory select in the rxque properties register indicates "pci memory." enable master 64-bit addressing in the pcint 64bit control register is set. length 32 or 64 bits type read/write address queue 0 xxxx 1800 queue 1 xxxx 1840 queue 2 xxxx 1880 queue 3 xxxx 18c0 queue 4 xxxx 1900 queue 5 xxxx 1940 queue 6 xxxx 1980 queue 7 xxxx 19c0 queue 8 xxxx 1a00 queue 9 xxxx 1a40 queue 10 xxxx 1a80 queue 11 xxxx 1ac0 queue 12 xxxx 1b00 queue 13 xxxx 1b40 queue 14 xxxx 1b80 queue 15 xxxx 1bc0 power on value x'0000000000000000' restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. the lower bound registers must be at least 1k aligned (low order 10 bits not writable). the alignment should also correspond to the size specified in the upper bound register. for example, it should be 4k aligned if the upper bound specifies 4k size.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 383 of 676 13.2: rxque properties registers these registers specify the properties of the corresponding receive queue. length 32 bits type read/write address queue 0 xxxx 1808 queue 1 xxxx 1848 queue 2 xxxx 1888 queue 3 xxxx 18c8 queue 4 xxxx 1908 queue 5 xxxx 1948 queue 6 xxxx 1988 queue 7 xxxx 19c8 queue 8 xxxx 1a08 queue 9 xxxx 1a48 queue 10 xxxx 1a88 queue 11 xxxx 1ac8 queue 12 xxxx 1b08 queue 13 xxxx 1b48 queue 14 xxxx 1b88 queue 15 xxxx 1bc8 power on value x ? 00010001 ? restrictions bits 11-0 may only be written when the diagnostic bit has been set in the control register. there are no restrictions for bits 32-12.
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 384 of 676 pnr25.chapt05.01 august 14, 2000 reserved status-multiplexer control disable auto-free disable bcach advice disable timestamps queue direction reserved system-memory select system receive queue size of event reserved upper bound 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-18 reserved reserved. 17-16 status-multiplexer control 00 select ? full/empty ? 01 select ? threshold exceeded ? (power-on value) 10 select ? head valid ? 11 reserved 15 disable auto-free inhibits freeing of packet-buffers when the receive queue is full. 14 disable bcach advice when set, the bcach advice is disabled for this queue. this is necessary in order to use a queue as a general purpose container for user data. 13 disable timestamps when set, timestamps are disabled for this queue. this is necessary in order to run cut through modes. 12 queue direction when set, the direction of the queue is assumed to be reversed. this only affects the full condition and the threshold exceeded condition. when this bit is set, the polarity of these status signals changes. thus, the full condition becomes an empty condition, and the two threshold conditions trigger when the length of the queue is less than the corresponding threshold instead of greater than or equal. this mode is mainly used for queues that relay information from the system to the IBM3206K0424. also, event enqueues to a queue that is reversed do not start the event latency timer (since no new event for system has arrived). 11 reserved reserved 10 system-memory select this is valid only when bit 9 (system receive queue) is set. 0 pci memory (power-on value) 1 on-chip memory 9 system receive queue 8 size of event 0 32 bits (power-on value) 1 64 bits 7-4 reserved reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 385 of 676 3-0 upper bound this specifies the encoded upper bound of the corresponding receive queue data structure. the actual upper bound is calculated by adding the decoded queue size to the lower bound. when the receive queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the receive queue as a circular buffer. 0000 reserved 0001 256 entries (power-on value) 0010 512 entries 0011 1024 entries 0100 2k entries 0101 4k entries 0110 8k entries 0111 16k entries 1000 32k entries 1001 64k entries 101- reserved 11-- reserved bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 386 of 676 pnr25.chapt05.01 august 14, 2000 13.3: rxque head pointer registers these registers point to the head element of the corresponding receive queue. during normal operations, these registers do not need to be read or written, as they are used by the IBM3206K0424 to implement the receive queues. these registers are initialized when the lower bound register for the corresponding receive queue is written. length 32 bits type read/write address queue 0 xxxx 1810 queue 1 xxxx 1850 queue 2 xxxx 1890 queue 3 xxxx 18d0 queue 4 xxxx 1910 queue 5 xxxx 1950 queue 6 xxxx 1990 queue 7 xxxx 19d0 queue 8 xxxx 1a10 queue 9 xxxx 1a50 queue 10 xxxx 1a90 queue 11 xxxx 1ad0 queue 12 xxxx 1b10 queue 13 xxxx 1b50 queue 14 xxxx 1b90 queue 15 xxxx 1bd0 power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. the head pointer registers are four-byte aligned (low order two bits not writable). bits 31-19 are calculated internally, and are not writable.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 387 of 676 13.4: rxque tail pointer registers these registers point to the next free element of the corresponding receive queue. during normal operations, these registers do not need to be read or written, as they are used by the IBM3206K0424 to implement the receive queues. these registers are initialized when the lower bound register for the corresponding receive queue is written. length 32 bits type read/write address queue 0 xxxx 1814 queue 1 xxxx 1854 queue 2 xxxx 1894 queue 3 xxxx 18d4 queue 4 xxxx 1914 queue 5 xxxx 1954 queue 6 xxxx 1994 queue 7 xxxx 19d4 queue 8 xxxx 1a14 queue 9 xxxx 1a54 queue 10 xxxx 1a94 queue 11 xxxx 1ad4 queue 12 xxxx 1b14 queue 13 xxxx 1b54 queue 14 xxxx 1b94 queue 15 xxxx 1bd4 power on value x ? 00000000 ? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. the tail pointer registers are four-byte aligned (low order two bits not writable). bits 31-19 are calculated internally, and are not writable.
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 388 of 676 pnr25.chapt05.01 august 14, 2000 13.5: rxque length registers these registers specify the length (number of valid entries) of the corresponding receive queue. they can be used to query the status of a receive queue. this register is cleared when the corresponding lower bound is written. length 17 bits type read address queue 0 xxxx 1818 queue 1 xxxx 1858 queue 2 xxxx 1898 queue 3 xxxx 18d8 queue 4 xxxx 1918 queue 5 xxxx 1958 queue 6 xxxx 1998 queue 7 xxxx 19d8 queue 8 xxxx 1a18 queue 9 xxxx 1a58 queue 10 xxxx 1a98 queue 11 xxxx 1ad8 queue 12 xxxx 1b18 queue 13 xxxx 1b58 queue 14 xxxx 1b98 queue 15 xxxx 1bd8 power on value x ? 00000 ? restrictions these registers can only be written in diagnostic mode.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 389 of 676 13.6: rxque threshold registers these registers specify a queue length threshold at which the corresponding status bit is generated. these registers should be set equal to the number of queue entries that should cause status to be generated. for example, if the value was set to five, then no interrupt would be generated until five or more events were queued on the corresponding receive queue. the threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. when this register is set to ? 0 ? , no thresholding is done. when the direction bit is set for a receive queue, the threshold has the opposite polarity. for example, as long as there are more events in the queue than specified in the threshold register, no status would be raised. length 17 bits type read/write address queue 0 xxxx 181c queue 1 xxxx 185c queue 2 xxxx 189c queue 3 xxxx 18dc queue 4 xxxx 191c queue 5 xxxx 195c queue 6 xxxx 199c queue 7 xxxx 19dc queue 8 xxxx 1a1c queue 9 xxxx 1a5c queue 10 xxxx 1a9c queue 11 xxxx 1adc queue 12 xxxx 1b1c queue 13 xxxx 1b5c queue 14 xxxx 1b9c queue 15 xxxx 1bdc power on value x ? 00000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 390 of 676 pnr25.chapt05.01 august 14, 2000 13.7: rxque dequeue registers these registers are used to retrieve the event at the head of the corresponding receive queue. these regis- ters are used to retrieve the event at the head of the corresponding receive queue. the length of an rxque dequeue register is 64 bits if size of event is set in its corresponding rxque properties register; otherwise, the length is 32 bits. length 32 or 64 bits type read address queue 0 xxxx 1820 queue 1 xxxx 1860 queue 2 xxxx 18a0 queue 3 xxxx 18e0 queue 4 xxxx 1920 queue 5 xxxx 1960 queue 6 xxxx 19a0 queue 7 xxxx 19e0 queue 8 xxxx 1a20 queue 9 xxxx 1a60 queue 10 xxxx 1aa0 queue 11 xxxx 1ae0 queue 12 xxxx 1b20 queue 13 xxxx 1b60 queue 14 xxxx 1ba0 queue 15 xxxx 1be0 power on value x ? 00000000 ? restrictions this is a read only register, and all writes will be ignored. events are only returned when the diagnostic bit is reset in the control register, otherwise zero will be returned.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 391 of 676 13.8: rxque enqueue registers these registers are used to enqueue user events at the tail of the corresponding receive queue. the length of a rxque enqueue register is 64 bits if size of event is set in its corresponding rxque properties register; otherwise, the length is 32 bits. length 32 or 64 bits type read/write queue 0 xxxx 1828 queue 1 xxxx 1868 queue 2 xxxx 18a8 queue 3 xxxx 18e8 queue 4 xxxx 1928 queue 5 xxxx 1968 queue 6 xxxx 19a8 queue 7 xxxx 19e8 queue 8 xxxx 1a28 queue 9 xxxx 1a68 queue 10 xxxx 1aa8 queue 11 xxxx 1ae8 queue 12 xxxx 1b28 queue 13 xxxx 1b68 queue 14 xxxx 1ba8 queue 15 xxxx 1be8 power on value x ? 00000000 ? restrictions all reads result in zero. rxque should be enabled to do this.
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 392 of 676 pnr25.chapt05.01 august 14, 2000 13.9: rxque next lower bound registers these registers specify the next lower bound of the corresponding system receive queue data structure. see rxque system receive queues on page 380 for instruction about managing system receive queues. the length of the rxque next lower bound register is the same as the length of the rxque lower bound register. see rxque lower bound registers on page 382 for conditions which determine the length. length 32 or 64 bits type read/write queue 0 xxxx 1830 queue 1 xxxx 1870 queue 2 xxxx 18b0 queue 3 xxxx 18f0 queue 4 xxxx 1930 queue 5 xxxx 1970 queue 6 xxxx 19b0 queue 7 xxxx 19f0 queue 8 xxxx 1a30 queue 9 xxxx 1a70 queue 10 xxxx 1ab0 queue 11 xxxx 1af0 queue 12 xxxx 1b30 queue 13 xxxx 1b70 queue 14 xxxx 1bb0 queue 15 xxxx 1bf0 power on value x ? 0000000000000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 393 of 676 13.10: rxque last event dropped register this register contains the last event that was dropped. it holds its value until the event dropped status bit is cleared. the length of the rxque last event dropped register is 64 bits if size of dropped event is set in the rxque status register; otherwise, the length is 32 bits. 13.11: rxque timestamp register used to specify the current timestamp measured using the timestamp pre-scaler ticks. it counts based on the value in the rxque timestamp pre-scaler register. it can be read or written at any time. it is cleared when the pre-scaler register is written. 13.12: rxque timestamp pre-scaler register used to specify the time interval of each timestamp timer tick. this register determines the number of 15 ns intervals between timestamp timer ticks. the value in the register plus one is the number of 15 ns intervals between timestamp timer ticks. so, the default value of ? 0 ? means that the timestamp timer ticks every 15 ns. if a value of four is placed in this register, the timestamp timer ticks every 75 ns (5 x 15 ns). length 32 or 64 bits type read/write address xxxx 1c10 power on value x'0000000000000000' restrictions none length 32 bits type read/write address xxxx 1c30 power on value x ? 00000000 ? restrictions none length 16 bits type read/write address xxxx 1c38 power on value x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 394 of 676 pnr25.chapt05.01 august 14, 2000 13.13: rxque timestamp shift register this register determines the number of bits that the timestamps are shifted. for example, if a value of ? 0 ? is placed in this register, then the timestamp is not shifted, and the low order seven bits are lost. if a value of ? 2 ? is placed in this register, then the timestamps are shifted two places and only the low order five bits of the timestamp are lost. this allows the user to control what portion of the timestamp is lost due to the low order event bits. 13.14: rxque event routing registers used to specify which receive queue different types of events should be routed to. these registers contain the receive queue that different types of events should be routed to. see event summary and routing infor- mation on page 367 for event type mappings. length 3 bits type read/write address xxxx 1c3c power on value x ? 00000002 ? restrictions none length 3 bits type read/write address event tx complete xxxx 1c40 event counter overflow xxxx 1c44 event error xxxx 1c48 event pools status xxxx 1c54 event abr xxxx 1c58 power on value x ? 00000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 395 of 676 13.15: rxque event latency timer register used to specify the event latency time interval. this register is specified in 15 ns intervals. when a new event is placed on an rxq, the event latency timer is started (if not already started). when this timer expires, the event latency timer expired status bit is set, and the timer is stopped. the status bit must be reset before the timer is started again. every time the status register (or prioritized status) is accessed, the timer is stopped. if this register is written while the timer is running, the new value takes effect immediately. if this register is set to ? 0 ? , the latency timer does not run. length 32 bits type read/write address xxxx 1c20 power on value x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 396 of 676 pnr25.chapt05.01 august 14, 2000 13.16: rxque queues status register indicates the status for all receive queues. length 64 bits type read only address xxxx 1d40 power on value x ? 0000000000000000 ? restrictions this is a read only register queue 15 queue 14 queue 13 queue 12 queue 11 queue 10 queue 9 queue 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 22 32 queue 7 queue 6 queue 5 queue 4 queue 3 queue 2 queue 1 queue 0 bit(s) name description 63-60 statue-nibble for queue 15 for each 4-bit range, bit encoding is as follows: 3 reserved reserved 2 head valid this is set when the head is valid for the queue. if this bit is set, then a deque operation should complete successfully. 1 threshold exceeded this is set when the queue-length register equals or exceeds the value in the queue-threshold register. 0 queue full/empty this is set when the queue-length register is equal to the queue-maximum-length register. when the direction of the queue is reversed, this bit is set when the queue is empty. 59-56 statue-nibble for queue 14 55-52 statue-nibble for queue 13 51-48 statue-nibble for queue 12 47-44 statue-nibble for queue 11 43-40 statue-nibble for queue 10 39-36 statue-nibble for queue 9 35-32 statue-nibble for queue 8 31-28 statue-nibble for queue 7 27-24 statue-nibble for queue 6 23-20 statue-nibble for queue 5 19-16 statue-nibble for queue 4 15-12 statue-nibble for queue 3 11-8 statue-nibble for queue 2 7-4 statue-nibble for queue1 3-0 statue-nibble for queue 0
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 397 of 676 13.17: rxque interrupt enable registers used to specify which status register bits should be used to generate interrupts. each mask register is used to drive a different rxque status bit in intst. the different masks and status bits allow two rxque interrupts on both the interrupt a and b pins. see note on set/clear type registers on page 93 for more details on addressing. see rxque status and enabled status registers on page 398 for the bit descriptions. length 32 bits type clear/set address enable 1 xxxx 1a80 and c84 enable 2 xxxx 1c88 and c8c power on value enable 1 - 2 x ? 00000000 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 398 of 676 pnr25.chapt05.01 august 14, 2000 13.18: rxque status and enabled status registers this register contains the status bits used to relay rxque status information. the enabled version of these registers provides a version of the status register that is masked with the corresponding interrupt enable register. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set (none) read only (enable 1 - 2) address none xxxx 1ca0 and ca4 enable 1 1cb0 enable 2 xxxx 1cb4 power on value none and enable 1 - 2 x ? 00000000 ? restrictions only bits 26 down to 23 are writable. the rxque enabled status registers are read only. general purpose timer status int 1 status or pcore normal int status int 2 status or pcore critical int status reserved reserved event latency timer expired event dropped size of dropped event reserved any queue ? s head valid any queue ? s threshold exceeded any queue full/empty status-multiplexer output for queues 15-0 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 general purpose timer status this is a mirror of the general purpose timer status bit in interrupt status. 30 int 1 status or pcore normal int status when read from the pci bus, this bit indicates if there is status other than rxque sta- tus and general purpose timer status in the [tbd] using [tbd] as a mask. when read from the pcore polling interface, the mask used is the [tbd]. 29 int 2 status or pcore critical int status when read from the pci bus, this bit indicates if there is status other than rxque sta- tus and general purpose timer status in the [tbd] using [tbd] as a mask. when read from the pcore polling interface, the mask used is the [tbd]. 28-27 reserved reserved 26 sequence-error in 64-bit regis- ter-access reserved 25 event latency timer expired when this bit is set, the event latency timer has expired. this indicates that new events are waiting to be processed on some queue(s) and the queue has not been processed for a period equal to the latency timer. this bit must be reset to re-enable the event latency timer. 24 event dropped when this bit is set, at least one event has been dropped. rxque last event dropped register contains the event that was dropped.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 399 of 676 23 size of dropped event 0 32 bits 1 64 bits this bit does not generate interrupts. 22-19 reserved reserved 18 any queue ? s head valid 17 any queue ? s threshold exceeded 16 any queue full/empty 15-0 15-0: status-multiplexer output for queues 15-0 reports either "head valid," "threshold exceeded," or "queue full/empty" according to the setting of the status-multiplexer-control field in the rxque properties register. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 400 of 676 pnr25.chapt05.01 august 14, 2000 13.19: rxque control register used to set rxque modes. see note on set/clear type registers on page 93 for more details on address- ing. this register contains the mode bits that specify how rxque is to operate. length 32 bits type clear/set address xxxx 1c00 and c04 power on value x ? 00000300 ? restrictions none reset fifo reserved assume 64-bit pci assume 32-bit pci enable swap words on pci enable swap bytes on pci always route error events enable chip overflow events memory select inhibit enqueues timestamp mode receive bad frames bcach advice diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reset fifo when this bit is set, the internal fifo is flushed, and this bit is reset. the result is this bit will always be read as a ? 0 ? . this bit can only be set in diagnostic mode. 30-12 reserved reserved. 11 assume 64-bit pci 10 assume 32-bit pci 9 enable swap words on pci this bit is automatically set at power-on. 8 enable swap bytes on pci this bit is automatically set at power-on. 7 always route error events when this bit is set, all error events are routed to the error queue even if rx bad frames (bit2) is turned on. when cleared, error events are only routed to the error queue if rx bad frames is turned off. this bit allows the user to keep bad frames in time sequence with good frames or to route them to the error queue. the clear state of this bit is code compatible with previous versions of the processor. 6 enable chip overflow events when set, the chip level counter overflow events are surfaced. 5 memory select when this bit is set, rxque will use packet memory instead of control memory to store the event queues. 4 inhibit enqueues when this bit is set, the enq state machine will not accept any new enq requests. this should be used in extreme cases as it holds off all enqueues indefinitely. 3timestamp mode when this bit is set, timestamp events are inserted before each real event. the times- tamps correspond to when the event happened on chip. when this bit is off, times- tamps can still be read from the timestamp register. the timestamps would correspond to when the event was dequeued in this scenario.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 receive queues (rxque) page 401 of 676 debugging register access this section is a very brief documentation of access that has been put in for the internal registers of rxque. these addresses need not be written or read during normal operations. 13.20: rxque rxq state machine variable register main state variable for rxque processing state machine. 13.21: rxque rxq enq state machine variable register main state variable for rxque processing state machine. 2 receive bad frames when this bit is set, bad frame events (all error events), will be received in the normal rxq defined in the lcd. all buffers are not freed, and the packet address is raised in the event data. when this bit is reset, bad frame events are routed to the rxq specified by the error event receive queue register. all packet based events will carry the lc address in the event data instead of the packet address. all buffers are freed back to pools. note: this bit should only be changed sparingly because it changes the way packets are freed and what is surfaced in an event (lcd vs. frame ptr). it should really only be changed when the receive side is inactive. 1 bcach advice this bit, when set, allows rxque to give bcach cache fill advice based on events that are dequeued. 0 diagnostic mode when this bit is set or when the chip is disabled, the rxque entity is in diagnostic mode and primitive execution is disabled. length 4 bits type read/write address xxxx 1e80 power on value x ? 00000000 ? restrictions none length 3 bits type read/write address xxxx 1e84 power on value x ? 00000000 ? restrictions none bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary receive queues (rxque) page 402 of 676 pnr25.chapt05.01 august 14, 2000 13.22: rxque enq fifo head ptr register used to maintain the enqueue fifo. points to the head fifo entry in the fifo array. the msb bit is used to determine if the head is chasing the tail, and is inverted each time the head pointer wraps. 13.23: rxque enq fifo tail ptr register used to maintain the enqueue fifo. points to the next free fifo entry in the fifo array. the msb bit is used to determine if the head is chasing the tail, and is inverted each time the tail pointer wraps. 13.24: rxque enq fifo array holds events waiting to be placed on an rxq. array is organized as a 16x36 array. to access the upper four bits of each word (holds the receive queue number for event), the array word number should be used as the address. to access the low order 32 bits (the event portion), the array word number times two plus four should be used. for example, address zero accesses the receive queue portion of array word zero, and address four accesses the event portion of the array word zero. note: the most significant bit is not used. only the three bits are needed for the receive queue number. length 5 bits type read/write address xxxx 1e88 power on value x ? 00000000 ? restrictions can only be written in diagnostic mode. length 5 bits type read/write address xxxx 1e8c power on value x ? 00000000 ? restrictions can only be written in diagnostic mode. length 16 words x 36 bits type read/write address xxxx 1f00-ff8 power on value x ? 00000000 ? restrictions can only be read/written in diagnostic mode. when read in non-diagnostic mode, zero is returned.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 403 of 676 phy level interfaces entity 14: the phy interface (linkc) functional description linkc provides the interface between the IBM3206K0424 and either an atm phy device or, when the inter- nal framer is selected, a serializer/deserializer device. linkc is composed of three pieces. linkx, which contains all the registers described below, is clocked with the same clock as other parts of the chip. linkt, the transmit logic, is clocked on the transmit clock, which is selected via the clock control register (described in clock control register (nibble aligned) on page 516). linkr, the receive logic, is clocked on the receive clock, which is also selectable via the clock control register. transmit and receive transfers are synchronized via their respective interface transfer clock. the data path size is 8- or 16-bits wide and is selectable through bit 3 of the control register. the phy devices that the IBM3206K0424 interfaces to are: pmc sierra pm5346 suni lite for sonet sts-3c 155.52 mb/s utopia 8 or 16 bit interface pmc sierra pos-phy new features added to linkc are: multi-drop utopia support pmc sierra pos-phy interface support multi-drop when the IBM3206K0424 is in multi-drop utopia mode, it supports four external phy devices. each port is associated with a configuration. four configurations are provided so up to four different types of phys can be connected to the IBM3206K0424. this allows the user to mix cell and pos-phy devices on the transmit and/or receive interface. the multi drop phy devices supported are utopia level 2 (cell based) and pmc sierra pos-phy (packet/frame based). the IBM3206K0424 will select which phy device will transfer data next by polling each of the devices to determine which phys can transfer data. a round-robin switching scheme is used to determine which phy has the priority if more then one wants to transmit/receive data. the IBM3206K0424 will switch to a new drop when a cell has been received/transmitted (for a cell-based phy) or when 64 bytes or eop has been received/transmitted (for pos-phy phys). the transmit and receive sides of link are separately configurable for multi-drop mode (bits 1 and 0 of the global control register). pos-phy the pos-phy interface complies with the pmc sierra pos-phy level 2 specification. the IBM3206K0424 polls each pos-phy device to determine its status on both the receive and transmit side. it looks to switch to a different port when 64 bytes or eop (end of packet) have been transferred between the pos-phy and itself. the IBM3206K0424 does not support direct status indication or byte-level transfers. therefore, the phy must be programmed to always be able to send/receive at least 64 bytes of information. the rmod signal will only be looked at when reop is b'1'; at all other times it will be ignored. pos-phy devices should be configured so that they will only signal they are ready for a transfer if they have 64 bytes free in their receive buffer and 64 bytes or eop in their transmit fifo.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 404 of 676 pnr25.chapt05.01 august 14, 2000 moving cells to and from the IBM3206K0424 14.1: linkc global control register this register contains the information which controls the operation of linkc. these controls affect all config- urations. see note on set/clear type registers on page 93 for more details on addressing. interface data payload cell cycles for eight-bit bus cycles for 16-bit bus utopia cell 48 52 52 26 utopia cell 48 53 53 27 utopia cell 48 54 54 27 utopia cell 48 55 55 28 utopia cell 48 56 56 28 length 32 bits type clear/set address xxxx 0b30 and 34 power on value x ? c0000344 ? restrictions none enable linkc reserved allow rx side to stall ignore rx empty signal ignore tx full signal always transfer cell reserved transmit phy watchdog timer receive phy watchdog timer enable transmit side watchdog timer enable receive side watchdog timer disable phy bus drivers reserved serdes external loopback mode utopia cell length overrride standard utopia cell length loopback mode enable transmit multi-drop enable receive multi-drop 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 enable linkc this bit, when set to ? 1 ? will enable linkc. the default for this bit is ? 1 ? . 30 reserved reserved. 29 allow rx side to stall when this bit is set, the rx side is allowed to stall. this means that the IBM3206K0424 is allowed to park on a port until the port has data for the IBM3206K0424. this bit should be set if you are talking to a single drop pos-phy device that doesn't have address pins and the IBM3206K0424 is being run in multi-drop mode. 28 ignore rx empty signal when this bit is set the empty signal will be ignored and it is always assumed the phy has data. the default for this bit is ? 0 ? . 27 ignore tx full signal when this bit is set the full signal will be ignored and it is always assumed the phy has room. the default for this bit is ? 0 ? .
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 405 of 676 26 always transfer cell when this bit is set to ? 1 ? , the tca (transmit cell available) will be ignored until the cur- rent transfer ends. this mode is recommended when talking to a single drop utopia device. the default for this bit is ? 0 ? . 25-21 reserved reserved 23-20 transmit phy watchdog timer these four bits are the cycles the transmit side (linkt) will wait before switching to another phy. if the timer times out, a status bit in linkc interrupt/status register will be set for the offending phy. 19-16 receive phy watchdog timer these four bits are the cycles the receive side (linkr) will wait before switching to another phy. if the timer times out, a status bit in linkc interrupt/status register will be set for the offending phy. 15 enable transmit side watchdog timer this bit, when set to ? 1 ? , causes linkt to timeout if the phy has started to take data but is now unable to take data for the number of cycles determined by the transmit phy watchdog timer (bits 23-20). the timer is only valid if the transmit side is in multi-drop mode. 14 enable receive side watchdog timer this bit, when set to ? 1 ? , causes linkr to timeout if the phy is receiving data and is unable to provide data for the number of cycles determined by the receive phy watchdog timer (bits 19-16). the timer is only valid if the receive side of linkc is in multi-drop mode and the phy is a utopia device. 13 disable phy bus drivers this bit, when set to ? 1 ? , tri-states the drivers of the phy bus. when set to ? 0 ? , the driv- ers are enabled. 12 reserved reserved 11 serdes external loopback mode when this bit is set, the receive side serdes input will be routed to the transmit side serdes output. 10-4 utopia cell length these seven bits will define what the utopia cell length (in bytes) will be if the override standard utopia cell length bit (bit 3) is set to ? 1 ? . the upper limit of this register is 64 and the lower limit is one. the default value of these bits is x'0110100'. 3 override standard utopia cell length when this bit is set to ? 1 ? , the standard utopia cell length (52 or 53 bytes) will be replaced by the value in bits 10-4. this bit will have no affect on phys that aren't uto- pia and it will disable the hec generation for any utopia phy. 2 loop back mode this bit set to ? 1 ? places the IBM3206K0424 in an internal loop back mode. the phy interface will be disabled. the clocks to linkt and linkr should be set to the same source in the clock control register. this bit is flushed to a ? 1 ? after por. for loop- back to work in multi-drop mode the transmit and receive configurations must be the same. when a configuration is set up for utopia cell-based transmission the receive and transmit sides should be identical in all ways. these include odd/even parity, data path length, 52-byte cell mode, null cell generation, and hec generation of null cells. the additional header bytes should be set to '00' when in loopback mode. please see the table legal loopback configurations on page 406 . 1 enable transmit multi-drop setting this bit will put the transmit side into multi-drop mode. in multi-drop mode the IBM3206K0424 will support four configurations and four unique ports. this bit should not be set if the transmit side is connected to the internal sonet framer. configura- tion 0 transmit control register will control the transmit interface. if this bit is not set, the IBM3206K0424 is in single drop mode. 0 enable receive multi-drop setting this bit will put the receive side into multi-drop mode. in multi-drop mode, the IBM3206K0424 will support four configurations and four unique phy ports. this bit should not be set if the receive side is connected to the internal sonet framer. con- figuration 0 receive control register will control the receive interface. if this bit is not set, the IBM3206K0424 receive side is in single drop mode. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 406 of 676 pnr25.chapt05.01 august 14, 2000 legal loopback configurations tx config 0 rx config 0 tx config 1 rx config 1 tx config 2 rx config 2 tx config 3 rx config 3 sonet sonet not used not used not used not used not used not used utopia cell utopia cell not used not used not used not used not used not used not used not used utopia cell utopia cell not used not used not used not used not used not used not used not used utopia cell utopia cell not used not used not used not used not used not used not used not used utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy not used not used not used not used not used not used not used not used pos-phy pos-phy not used not used not used not used not used not used not used not used pos-phy pos-phy not used not used not used not used not used not used not used not used pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell utopia cell pos-phy pos-phy
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 407 of 676 14.2: linkc configuration 0 transmit & receive control register this register contains the information which controls the operation of configuration 0 on the transmit and receive. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b50 and 0b54 power on value x ? 78016e00 ? phy transmit device even/odd parity selection phy data path size reserved # of additional header bytes modify byte alignment in 16-bit phy mode pmc pm5346 suni lite/utopia: 52 byte cell disable hec generation on transmitted cells parity on all 16 bits phy receive device enable parity checking disable hec generation on transmitted cells phy data path size 16 bit parity reserved byte cell unassigned/idle cell reception disable limited hec checking ignore gfc in null/idle cell determination enable xon/xoff drive renb inactive when not receiving gate rsoc with rca receive extra header byte 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-29 phy transmit device bits 31, 30, and 29 indicates to which phy the IBM3206K0424 ? s transmit config 0 will be interfacing. if the configuration ? s port address is all ones, then the configuration is unused and the value above bits doesn ? t matter. ? 000 ? reserved ? 001 ? pmc pos-phy (frame-based utopia) ? 010 ? reserved ? 011 ? pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) ? 100 ? reserved ? 101 ? internal sonet(sts-3c)/sdh(stm-1) framer with serdes (serial inter- face) ? 111 ? reserved 28 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. par- ity will always be generated when the IBM3206K0424 is transmitting data. if the phy doesn ? t check parity, then don ? t connect the lines. 27 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fytdat(1 -13) to be used for the 16-bit external tx phy device, while a ? 0 ? will allow fyt- dat(15-13) to be used for the rx hdlc controller. this implies that it is not possible to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. 26-19 reserved reserved.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 408 of 676 pnr25.chapt05.01 august 14, 2000 21-20 number of additional header bytes these bits indicate the number of additional header bytes that will be read from seg- buf and added to the beginning of each cell as each is transmitted to the phy. the bytes are meant to be used for additional routing information. these control bits have no affect in ibm 25 mb/s phy mode, and should be set to ? 0 ? s when in internal sonet/sdh framer mode. if used in conjunction with 52-byte mode, the byte normally containing the cell hec will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. if 16-bit phy mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. as a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (lsb is normally padded with zeros so msb gets truncated). bit 3 of this register is therefore provided to adjust the align- ment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. 19 modify byte alignment in 16-bit phy mode when set to ? 1 ? , this bit changes the default byte alignment in 16-bit phy mode if this register also contains a non-zero value in bits 21-20. see the description of those bits for further details. 18-16 bits 18-16 only have meaning if a pmc pm5346 suni lite/utopia (bits 31-29 = "011") is selected. if any other device is chosen, these bits will be ignored. 18 52 byte cell when set, the cell sent to the phy will be 52 bytes. no hec byte will be sent. 17 disable hec generation on transmitted cells if bit 17 is set to ? 1 ? , x'00' will be placed in the hec byte of utopia cells. if bit 17 is set to ? 0 ? , then the value of linkc transmitted hec control byte will be sent. if bit 18 is set to ? 1 ? , then no hec will be sent and this bit will be ignored. 16 parity on all 16 bits when set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. when set to ? 0 ? , the IBM3206K0424 will produce two parity bits, one across generation and the lower half of the 16 bits (parity bit 0) and one against the upper (parity bit 1). the default for this bit is ? 1 ? . 15-13 phy receive device these bits indicate to which phy the IBM3206K0424 ? s receive config 0 will be inter- facing. if the configuration's port address is all ? 1 ? s, then the configuration is unused and the value of the above bits doesn't matter. '000' reserved '001' pmc pos-phy (frame-based utopia) '010 ? reserved '011' pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) '100' reserved '101' internal sonet (sts-3c)/sdh(stm-1) framer with serdes (serial interface) '111' reserved 12 enable parity checking when set, this bit will enable checking of parity on data from the receive path. the default is parity checking is disabled. the upper bit of the transmit parity is not valid when the internal sonet/sdh framer has been selected as the receive phy device. the upper bit of the receive parity is also not valid when the internal sonet/sdh framer has been selected as the transmit phy device. this is only a concern if a com- bination of the internal framer and an external phy is being used and that external phy has a 16-bit data interface. in this case, parity cannot be checked/generated on the upper byte. 11 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. 10 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero will allow fytdat(15-13) to be used for the rx hdlc controller. this implies that it is not possi- ble to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. 9 16 bit parity when this bit is set to ? 1 ? in 16-bit mode, parity will be calculated across all 16 bits and checked against fyrpar(1). when in 8-bit mode with bit 9 set to ? 0 ? , the parity will be compared against fyrpar(1). this bit has no affect if receive device is pos-phy. the default setting of this bit is ? 1 ? . bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 409 of 676 8 reserved reserved 7-0 bits 7-0 only have meaning if a pmc pm5346 suni lite/utopia (bits 15-13 = "011") is selected. otherwise, they are ignored. bits 2-0 are used to make adjustments to the utopia interface for compatibility with the suni-phd phy. 7byte cell when set, the cell received from the phy will be 52 bytes. no hec byte will be received. 6-5 reserved reserved 6 unassigned/idle cell reception when set to ? 1 ? , this bit will enable unassigned/idle cell reception. this should be set to ? 0 ? when using the internal sonet framer. 5 disable limited hec checking on received idle/unassigned cells if bit 5 is set to ? 1 ? , the receive logic will ignore the hec byte of the header of idle and unassigned cells. idle is defined as a header of x'00000001' and unassigned is defined as a header of x'0000000n' where n is 'xxx0'. if bit 6 is set to enable unassigned/idle cell reception, all cells will be passed to reasm regardless of how this bit is set. if bit 6 is set to disable unassigned/idle cell reception and this bit is set to ? 0 ? , the hec byte of cells with an apparent idle header will be completely checked before deciding whether or not to pass the cell to reasm. if a cell appears to have an unassigned header, hec bits 7, 6, and 0 will be checked because they are a constant, regardless of the value of bits 3, 2, and 1 of the header. if other hec bits are bad, reasm will detect the hec error and discard the cell. if there is a correctable hec error and the cell is indeed unassigned, an out of range error will occur in reasm. 4 ignore gfc in null/idle cell deter- mination bit 4, when set, will cause the receive logic to ignore the first four bits of the atm header in determining whether a cell being received is a null or idle cell. 3 enable xon/xoff bit 3, when set, will allow the xon/xoff bit of the header of a received cell to sus- pend/continue transmission from the IBM3206K0424's transmit logic for all ports asso- ciated with config 0. 2 drive renb inactive when not receiving when set to ? 1 ? , this bit forces the receive logic to deactivate renb when in the idle state. 1 gate rsoc with rca when set to ? 1 ? , this bit forces the receive logic to see both rsoc and rca before considering rsoc valid. 0 receive extra header byte when set to ? 1 ? , this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. the extra byte is discarded. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 410 of 676 pnr25.chapt05.01 august 14, 2000 14.3: linkc configuration 1 transmit & receive control register this register contains the information which controls the operation of configuration 1 on the transmit and receive. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b58 and 0b5c power on value x ? 78016e00 ? phy transmit device even/odd parity selection phy data path size reserved # of additional header bytes modify byte alignment in 16-bit phy mode pmc pm5346 suni lite/utopia: 52 byte cell disable hec generation on transmitted cells parity on all 16 bits phy receive device enable parity checking disable hec generation on transmitted cells phy data path size 16 bit parity reserved byte cell unassigned/idle cell reception disable limited hec checking ignore gfc in null/idle cell determination enable xon/xoff drive renb inactive when not receiving gate rsoc with rca receive extra header byte 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-29 phy transmit device bits 31, 30, and 29 indicates to which phy the IBM3206K0424 ? s transmit config 1 will be interfacing. if the configuration ? s port address is all ones, then the configuration is unused and the value of the above bits doesn ? t matter. ? 000 ? reserved ? 001 ? pmc pos-phy (frame based utopia) ? 010 ? reserved ? 011 ? pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) ? 100 ? reserved ? 101 ? reserved ? 111 ? reserved 28 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. par- ity will always be generated when the IBM3206K0424 is transmitting data. if the phy doesn ? t check parity, then don ? t connect the lines. 27 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero will allow fytdat(15-13) to be used for the rx hdlc controller. this implies that it is not possi- ble to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. 26-19 reserved reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 411 of 676 18-16 these bits only have meaning if a pmc pm5346 suni lite/utopia (bits 31-29 = "011") is selected. if any other device is chosen these bits will be ignored. 21-20 the value of bits 21-20 indicates the number of additional header bytes that will be read from segbuf and added to the beginning of each cell as each is transmitted to the phy. the bytes are meant to be used for additional routing information. these con- trol bits have no affect in ibm 25 mb/s phy mode, and should be set to ? 0 ? s when in internal sonet/sdh framer mode. if used in conjunction with 52-byte mode, the byte normally containing the cell hec will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. if 16-bit phy mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. as a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (lsb is normally padded with zeros so msb gets truncated). bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. 19 modify byte alignment in 16-bit phy mode when set to ? 1 ? , this bit changes the default byte alignment in 16-bit phy mode if this register also contains a non-zero value in bits 21-20. see the description of those bits for further details. 18 52 byte cell when set, the cell sent to the phy will be 52 bytes. no hec byte will be sent. 17 disable hec generation on transmitted cells if bit 17 is set to ? 1 ? , x'00' will be placed in the hec byte of utopia cells. if bit 17 is set to ? 0 ? , the value of linkc transmitted hec control byte will be sent. if bit 18 is set to ? 1 ? , then no hec will be sent and this bit will be ignored. 16 parity on all 16 bits when set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. when set to ? 0 ? , the IBM3206K0424 produces two parity bits, one across generation and the lower half of the 16 bits (parity bit zero) and one against the upper (parity bit 1). the default for this bit is ? 1 ? . 15-13 phy receive device bits 15, 14, and 13 indicate which phy the IBM3206K0424 ? s receive config 1 will be interfacing. if the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' reserved '001' pmc pos-phy (frame based utopia) '010' reserved '011' pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) '100' reserved '101' reserved '111' reserved 12 enable parity checking when set, this bit enables checking of parity on data from the receive path. the default parity checking is disabled. the upper bit of the transmit parity is not valid when the internal sonet/sdh framer has been selected as the receive phy device. the upper bit of the receive parity is also not valid when the internal sonet/sdh framer has been selected as the transmit phy device. this is only a concern if a combination of the internal framer and an external phy is being used and that external phy has a 16-bit data interface. in this case, parity cannot be checked/generated on the upper byte. 11 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. 10 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy is eight bits. this bit has no affect on the internal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero will allow fytdat(15-13) to be used for the rx hdlc controller. this implies that it is not possi- ble to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. 9 16 bit parity when this bit is set to ? 1 ? and it is in 16-bit mode, that parity will be calculated across all 16 bits and checked against fyrpar(1). when in eight-bit mode with bit 9 set to ? 0 ? , the parity will be compared against fyrpar(1). this bit has no affect if the receive device is pos-phy. the default setting of this bit is ? 1 ? . bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 412 of 676 pnr25.chapt05.01 august 14, 2000 8 reserved reserved 7-0 bits 7-0 only have meaning if a pmc pm5346 suni lite/utopia (bits 15-13 = "011") is selected. otherwise, these bits will be ignored. bits 2-0 are used to make adjustments to the utopia interface for compatibility with the suni-phd phy. 7 52 byte cell when set, the cell received from the phy is 52 bytes. no hec byte will be received. 6-5 reserved reserved 6 unassigned/idle cell reception when set to ? 1 ? , this bit will enable unassigned/idle cell reception. this should be set to ? 0 ? when using the internal sonet framer. 5 disable limited hec checking on received idle/unassigned cells if bit 5 is set to ? 1 ? , the receive logic will ignore the hec byte of the header of idle and unassigned cells. idle is defined as a header of x'00000001' and unassigned is defined as a header of x'0000000n' where n is 'xxx0'. if bit 6 is set to enable unassigned/idle cell reception, all cells are passed to reasm regardless of how this bit is set. if bit 6 is set to disable unassigned/idle cell reception and this bit is set to ? 0 ? , the hec byte of cells with an apparent idle header will be com- pletely checked before deciding whether or not to pass the cell to reasm. if a cell appears to have an unassigned header, hec bits seven, six, and zero will be checked because they are a constant regardless of the value of bits 3-1 of the header. if other hec bits are bad, reasm will detect the hec error and discard the cell. if there is a correctable hec error and the cell is indeed unassigned, an out of range error will occur in reasm. 4 ignore gfc in null/idle cell deter- mination bit 4, when set, will cause the receive logic to ignore the first four bits of the atm header in determining whether a cell being received is a null or idle cell. 3 enable xon/xoff bit 3, when set, will allow the xon/xoff bit of the header of a received cell to sus- pend/continue transmission from the IBM3206K0424's transmit logic for all ports asso- ciated with config 1. 2 drive renb inactive when not receiving when set to ? 1 ? , this bit forces the receive logic to deactivate renb when in the idle state. 1 gate rsoc with rca when set to ? 1 ? , this bit forces the receive logic to see both rsoc and rca before considering rsoc valid. 0 receive extra header byte when set to ? 1 ? , this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. the extra byte is discarded. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 413 of 676 14.4: linkc configuration 2 transmit & receive control register this register contains the information which controls the operation of configuration 2 on the transmit and receive. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b60 and 0b64 power on value x ? 78016e00 ? restrictions phy transmit device even/odd parity selection phy data path size reserved # of additional header bytes modify byte alignment in 16-bit phy mode pmc pm5346 suni lite/utopia: 52 byte cell disable hec generation on transmitted cells parity on all 16 bits phy receive device enable parity checking disable hec generation on transmitted cells phy data path size 16 bit parity reserved byte cell unassigned/idle cell reception disable limited hec checking ignore gfc in null/idle cell determination enable xon/xoff drive renb inactive when not receiving gate rsoc with rca receive extra header byte 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-29 phy transmit device bits 31, 30, and 29 indicate which phy the IBM3206K0424 ? s transmit config 2 will be interfacing. if the configuration ? s port address is all ones then the configuration is unused and the value above bits doesn ? t matter. ? 000 ? reserved ? 001 ? pmc pos-phy (frame based utopia) ? 010 ? reserved ? 011 ? pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) ? 100 ? reserved ? 101 ? reserved ? 111 ? reserved 28 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. par- ity will always be generated when the IBM3206K0424 is transmitting data. if the phy doesn ? t check parity then don ? t connect the lines. 27 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit allows fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero allows fyt- dat(15-13) to be used for the rx hdlc controller. this implies that it is not possible to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 414 of 676 pnr25.chapt05.01 august 14, 2000 26-19 reserved reserved 18-16 these bits only have meaning if a pmc pm5346 suni lite/utopia (bits 31-29 = "011") is selected. if any other device is chosen these bits will be ignored. 21-20 the value of bits 21-20 indicate the number of additional header bytes that will be read from segbuf and added to the beginning of each cell as each is transmitted to the phy. the bytes are meant to be used for additional routing information. these control bits have no affect in ibm 25 mb/s phy mode, and should be set to ? 0 ? s when in inter- nal sonet/sdh framer mode. if used in conjunction with 52-byte mode, the byte normally containing the cell hec will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. if 16-bit phy mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. as a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (lsb is normally padded with zeros so msb gets truncated). bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. 19 modify byte alignment in 16-bit phy mode when set to ? 1 ? , this bit changes the default byte alignment in 16-bit phy mode if this register also contains a non-zero value in bits 21-20. see the description of those bits for further details. 18 52 byte cell when set, the cell sent to the phy is 52 bytes. no hec byte will be sent. 17 disable hec generation on transmitted cells if bit 17 is set to ? 1 ? , x'00' will be placed in the hec byte of utopia cells. if bit17 is set to ? 0 ? , the value of linkc transmitted hec control byte will be sent. if bit18 is set to ? 1 ? , then no hec is sent and this bit will be ignored. 16 parity on all 16 bits when set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. when set to ? 0 ? , the IBM3206K0424 will produce two parity bits, one across generation and the lower half of the 16 bits (parity bit zero) and one against the upper (parity bit 1). the default for this bit is ? 1 ? . 15-13 phy receive device bits 15, 14, and 13 indicate which phy the IBM3206K0424 ? s receive config 2 will be interfacing. if the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' reserved '001' pmc pos-phy (frame based utopia) '010' reserved '011' pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) '100' reserved '101' reserved '111' reserved 12 enable parity checking when set, this bit will enable checking of parity on data from the receive path. the default parity checking is disabled. the upper bit of the transmit parity is not valid when the internal sonet/sdh framer has been selected as the receive phy device. the upper bit of the receive parity is also not valid when the internal sonet/sdh framer has been selected as the transmit phy device. this is only a concern if a combination of the internal framer and an external phy is being used and that external phy has a 16-bit data interface. in this case, parity cannot be checked/generated on the upper byte. 11 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. 10 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero allows fyt- dat(15-13) to be used for the rx hdlc controller. this implies that it is not possible to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 415 of 676 9 16 bit parity when this bit is set to ? 1 ? and it is in 16-bit mode, that parity will be calculated across all 16 bits and check against fyrpar(1). when in eight-bit mode with bit 9 set to ? 0 ? , the parity will be compared against fyrpar(1). this bit has no affect if receive device is pos-phy. the default setting of this bit is ? 1 ? . 8 reserved reserved 7-0 these bits only have meaning if a pmc pm5346 suni lite/utopia (bits 15-13 = "011") is selected. if any other device is chosen, these bits are ignored. bits two through zero are used to make adjustments to the utopia interface for compatibility with the suni-phd phy. 7 52 byte cell when set, the cell received from the phy is 52 bytes. no hec byte is received. 6-4 reserved reserved 6 unassigned/idle cell reception when set to ? 1 ? , this bit will enable unassigned/idle cell reception. this should be set to ? 0 ? when using the internal sonet framer. 5 disable limited hec checking on received idle/unassigned cells if bit 5 is set to ? 1 ? , the receive logic will ignore the hec byte of the header of idle and unassigned cells. idle is defined as a header of x'00000001' and unassigned is defined as a header of x'0000000n' where n is 'xxx0'. if bit 6 is set to enable unassigned/idle cell reception, all cells are passed to reasm regardless of how this bit is set. if bit 6 is set to disable unassigned/idle cell reception and this bit is set to ? 0 ? , the hec byte of cells with an apparent idle header will be com- pletely checked before deciding whether or not to pass the cell to reasm. if a cell appears to have an unassigned header, hec bits seven, six, and zero will be checked because they are a constant regardless of the value of bits 3-1 of the header. if other hec bits are bad, reasm will detect the hec error and discard the cell. if there is a correctable hec error and the cell is indeed unassigned, an out of range error will occur in reasm. 4 ignore gfc in null/idle cell deter- mination bit 4, when set, causes the receive logic to ignore the first four bits of the atm header in determining whether a cell being received is a null or idle cell. 3 enable xon/xoff bit 3, when set, allows the xon/xoff bit of the header of a received cell to sus- pend/continue transmission from the IBM3206K0424's transmit logic for all ports asso- ciated with config 2. 2 drive renb inactive when not receiving when set to ? 1 ? , this bit forces the receive logic to deactivate renb when in the idle state. 1 gate rsoc with rca when set to ? 1 ? , this bit forces the receive logic to see both rsoc and rca before considering rsoc valid. 0 receive extra header byte when set to ? 1 ? , this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. the extra byte is discarded. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 416 of 676 pnr25.chapt05.01 august 14, 2000 14.5: linkc configuration 3 transmit & receive control register this register contains the information which controls the operation of configuration 3 on the transmit and receive. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b68 and 0b6c power on value x ? 78016e00 ? restrictions phy transmit device even/odd parity selection phy data path size reserved # of additional header bytes modify byte alignment in 16-bit phy mode pmc pm5346 suni lite/utopia: 52 byte cell disable hec generation on transmitted cells parity on all 16 bits phy receive device enable parity checking disable hec generation on transmitted cells phy data path size 16 bit parity reserved byte cell unassigned/idle cell reception disable limited hec checking ignore gfc in null/idle cell determination enable xon/xoff drive renb inactive when not receiving gate rsoc with rca receive extra header byte 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-29 phy transmit device bits 31, 30, and 29 indicate to which phy the IBM3206K0424 ? s transmit config 3 will be interfacing. if the configuration ? s port address is all ones then the configuration is unused and the value of the above bits doesn ? t matter. ? 000 ? reserved ? 001 ? pmc pos-phy (frame based utopia) ? 010 ? reserved ? 011 ? pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) ? 100 ? reserved ? 101 ? reserved ? 111 ? reserved 28 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. par- ity will always be generated when the IBM3206K0424 is transmitting data. if the phy doesn ? t check parity then don ? t connect the lines. 27 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero will allow fytdat(15-13) to be used for the rx hdlc controller. this implies that it is not possi- ble to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 417 of 676 26-19 reserved reserved 21-20 the value of bits 21-20 indicate the number of additional header bytes that will be read from segbuf and added to the beginning of each cell as each is transmitted to the phy. the bytes are meant to be used for additional routing information. these control bits have no affect in ibm 25 mb/s phy mode, and should be set to ? 0 ? s when in inter- nal sonet/sdh framer mode. if used in conjunction with 52-byte mode, the byte nor- mally containing the cell hec will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. if 16-bit phy mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. as a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (lsb is normally padded with zeros so msb gets truncated). bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. 19 modify byte alignment in 16-bit phy mode when set to ? 1 ? , this bit changes the default byte alignment in 16-bit phy mode if this register also contains a non-zero value in bits 21-20. see the description of those bits for further details. 18-16 these bits only have meaning if a pmc pm5346 suni lite/utopia (bits 31-29 = "011") is selected. if any other device is chosen these bits will be ignored. 18 52 byte cell when set, the cell sent to the phy is 52 bytes. no hec byte will be sent. 17 disable hec generation on transmitted cells if bit 17 is set to ? 1 ? , x'00' will be placed in the hec byte of utopia cells. if bit 17 is set to ? 0 ? , the value of linkc transmitted hec control byte will be sent. if bit 18 is set to ? 1 ? , no hec is sent and this bit will be ignored. 16 parity on all 16 bits when set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. when set, the IBM3206K0424 produces two parity bits, one across generation and the lower half of the 16 bits (parity bit 0) and one against the upper (parity bit 1). the default for this bit is ? 1 ? . 15-13 phy receive device bits 15, 14, and 13 indicate to which phy the IBM3206K0424's receive config 3 will be interfacing. if the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' reserved '001' pmc pos-phy (frame based utopia) '010' reserved '011' pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) '100' reserved '101' reserved '111' reserved 12 enable parity checking when set, this bit enables checking of parity on data from the receive path. the default parity checking is disabled. the upper bit of the transmit parity is not valid when the internal sonet/sdh framer has been selected as the receive phy device. the upper bit of the receive parity is also not valid when the internal sonet/sdh framer has been selected as the transmit phy device. this is only a concern if a combination of the internal framer and an external phy is being used and that external phy has a 16-bit data interface. in this case, parity cannot be checked/generated on the upper byte. 11 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. 10 phy data path size this bit, when set to ? 0 ? , selects a 16-bit wide data path to the phy device. when set to ? 1 ? , the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the tx phy device. in this case, a ? 1 ? on this bit will allow fyt- dat(15-13) to be used for the 16-bit external tx phy device, while a zero will allow fytdat(15-13) to be used for the rx hdlc controller. this implies that it is not possi- ble to use the internal rx framer, the rx hdlc interface, and an external 16-bit tx framer at the same time. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 418 of 676 pnr25.chapt05.01 august 14, 2000 9 16 bit parity when this bit is set to ? 1 ? and it is in 16-bit mode, that parity will be calculated across all 16 bits and checked against fyrpar(1). when in eight-bit mode with bit 9 set to ? 0 ? , the parity is compared against fyrpar(1). this bit has no affect if receive device is pos-phy. the default setting of this bit is ? 1 ? . 8 reserved reserved 7-0 these bits only have meaning if a pmc pm5346 suni lite/utopia (bits 15-13 = "011") is selected. if any other device is chosen, these bits are ignored. bits 2-0 are used to make adjustments to the utopia interface for compatibility with the suni-phd phy. 7 52 byte cell when set, the cell received from the phy is 52 bytes. no hec byte will be received. 6-4 reserved reserved 6 unassigned/idle cell reception when set to ? 1 ? , this bit will enable unassigned/idle cell reception. this should be set to ? 0 ? when using the internal sonet framer. 5 disable limited hec checking on received idle/unassigned cells if bit 5 is set to ? 1 ? , the receive logic will ignore the hec byte of the header of idle and unassigned cells. idle is defined as a header of x'00000001' and unassigned is defined as a header of x'0000000n' where n is b'xxx0'. if bit 6 is set to enable unassigned/idle cell reception, all cells are passed to reasm regardless of how this bit is set. if bit 6 is set to disable unassigned/idle cell reception and this bit is set to ? 0 ? , the hec byte of cells with an apparent idle header will be com- pletely checked before deciding whether or not to pass the cell to reasm. if a cell appears to have an unassigned header, hec bits 7, 6, and 0 are checked because they are a constant regardless of the value of bits 3-1 of the header. if other hec bits are bad, reasm detects the hec error and discards the cell. if there is a correctable hec error and the cell is indeed unassigned, an out of range error occurs in reasm. 4 ignore gfc in null/idle cell deter- mination bit 4, when set, causes the receive logic to ignore the first four bits of the atm header in determining whether a cell being received is a null or idle cell. 3 enable xon/xoff bit 3, when set, allows the xon/xoff bit of the header of a received cell to sus- pend/continue transmission from the IBM3206K0424's transmit logic for all ports asso- ciated with config 3. 2 drive renb inactive when not receiving when set to ? 1 ? , this bit forces the receive logic to deactivate renb when in the idle state. 1 gate rsoc with rca when set to ? 1 ? , this bit forces the receive logic to see both rsoc and rca before considering rsoc valid. 0 receive extra header byte when set to ? 1 ? , this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. the extra byte is discarded. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 419 of 676 14.6: linkc map transmit configurations to port addresses this register contains the port address for each of the transmit configurations. if the port address is b"11111" then the configuration is unused. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b70 and 0b74 power on value x ? 1f1f1f1f ? restrictions none reserved port address for configuration 3 reserved port address for configuration 2 reserved port address for configuration 1 reserved port address for configuration 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-29 reserved 28-24 port address for configuration 3. 23-21 reserved 20-16 port address for configuration 2. 15-13 reserved 12-8 port address for configuration 1. 7-5 reserved 4-0 port address for configuration 0.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 420 of 676 pnr25.chapt05.01 august 14, 2000 14.7: linkc map receive configurations to port addresses this register contains the port address for each of the receive configurations. if the port address is "11111" then the configuration is unused. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b80 and 0b84 power on value x ? 1f1f1f1f ? restrictions none reserved port address for configuration 3 reserved port address for configuration 2 reserved port address for configuration 1 reserved port address for configuration 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-29 reserved. 28-24 port address for configuration 3. 23-21 reserved 20-16 port address for configuration 2. 15-13 reserved 12-8 port address for configuration 1. 7-5 reserved 4-0 port address for configuration 0.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 421 of 676 14.8: linkc transmitted hec control byte when the IBM3206K0424 is transmitting to a 53-byte utopia phy the hec byte (byte five of the atm header) will be sent as x ? 00 ? , if bit 17 of the transmitting configuration is a ? 1 ? . otherwise the value of the linkc trans- mitted hec control byte register will be sent. length 8 bits type read/write address xxxx 0b04 power on value x'00' restrictions none hec byte value 76543210 bit(s) description 7-0 value of the hec byte to be sent when talking to a 53-byte utopia phy.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 422 of 676 pnr25.chapt05.01 august 14, 2000 14.9: linkc interrupt/status register this register reports the status of linkc. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 0b10 and 14 power on value x ? 00 ? restrictions none c3: two sop without an eop c3: null cell c3: upper byte parity error c3: lower byte parity error c3: receive phy stalled c3: transmit phy stalled reserved c2: two sop without an eop c2: null cell c2: upper byte parity error c2: lower byte parity error c2: receive phy stalled c2: transmit phy stalled reserved c1: two sop without an eop c1: null cell c1: upper byte parity error c1: lower byte parity error c1: receive phy stalled c1: transmit phy stalled reserved c0: two sop without an eop c0: null cell c0: upper byte parity error c0: lower byte parity error c0: receive phy stalled c0: transmit phy stalled reasm fifo overrun no carrier detect from phy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 indicates that config 3 has seen two sop in a 64-byte boundary without an eop. multiple sop outside the 64-byte boundary will be passed up, and it ? s up to the higher levels to deal with this case. 30 indicates that config 3 has received a null cell. 29 indicates a parity error on the upper byte of receive data from the config 3 phy. 28 indicates a parity error on the lower byte of receive data from the config 3 phy. 27 indicates config 3 ? s receive phy has stalled out. 26 indicates config 3 ? s transmit phy has stalled out. 25-24 reserved 23 indicates that config 2 has seen two sop in a 64-byte boundary without an eop. multiple sop outside the 64-byte boundary will be passed up, and it ? s up to the higher levels to deal with this case. 22 indicates that config 2 has received a null cell. 21 indicates a parity error on the upper byte of receive data from the config 2 phy. 20 indicates a parity error on the lower byte of receive data from the config 2 phy. 19 indicates config 2 ? s receive phy has stalled out. 18 indicates config 2 ? s transmit phy has stalled out. 17-16 reserved 15 indicates that config 1 has seen two sop in a 64-byte boundary without an eop. multiple sop outside the 64 byte boundary will be passed up, and it ? s up to the higher levels to deal with this case. 14 indicates that config 1 has received a null cell. 13 indicates a parity error on the upper byte of receive data from the config 1 phy.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 423 of 676 12 indicates a parity error on the lower byte of receive data from the config 1 phy. 11 indicates config 1 ? s receive phy has stalled out. 10 indicates config 1 ? s transmit phy has stalled out. 9-8 reserved 7 indicates that config 0 has seen two sop in a 64-byte boundary without an eop. multiple sop outside the 64 byte boundary will be passed up, and it ? s up to the higher levels to deal with this case. 6 indicates that config 0 has received a null cell. 5 indicates a parity error on the upper byte of receive data from the config 0 phy. 4 indicates a parity error on the lower byte of receive data from the config 0 phy. 3 indicates config 0 ? s receive phy has stalled out. 2 indicates config 0 ? s transmit phy has stalled out. 1 reasm fifo has been overrun. 0 no carrier detect from the phy. bit(s) description
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 424 of 676 pnr25.chapt05.01 august 14, 2000 14.10: linkc interrupt enable register this register enables the linkc interrupt to intst. when a bit is set in this register and the corresponding bit is set in the interrupt status register, the linkc interrupt will be driven. see note on set/clear type regis- ters on page 93 for more details on addressing. see the linkc interrupt/status register on page 422 for the bitwise description of this register. 14.11: linkc prioritized interrupts used to access the prioritized encoding of linkc interrupts. reading this location will give a decimal number that is the prioritized encoding of bits 7-0 in comet/pakit status register (seven being the most significant bit) assuming the corresponding enable bit is on. length 8 bits type clear/set address xxxx 0b18 and 1c power on value x ? 00 ? restrictions none length 8 bits type read address xxxx 0b2c power on value x ? 00 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 425 of 676 14.12: linkc transmit state machine register this register indicates the state of the transmit sequencer. 14.13: linkc receive state machine register this register indicates the state of the receiver sequencer. length 6 bits type read/write address xxxx 0b24 power on value x ? 0 ? restrictions none unassigned transmit 543210 bit(s) description 5-3 unassigned cell state machine. 2-0 transmit state machine. length 2 bits type read/write address xxxx 0b28 power on value x ? 0 ? restrictions none bit(s) description 1-0 receive state machine.
IBM3206K0424 ibm processor for network resources preliminary the phy interface (linkc) page 426 of 676 pnr25.chapt05.01 august 14, 2000 14.14: linkc lan address register if using an ibm built adapter that utilizes crisco, this register contains the rom level in bits 63-48 and the lan address of the adapter in bits 47-0. the lower address selects bits 63-32 and the higher address selects bits 31-0. 14.15: linkc canonical lan address register this register contains the same data as the linkc lan address register except each byte is bit reversed. this allows the user to obtain the lan address in canonical format. length 64 bits type write/read address xxxx 0b38 and 3c power on value x ? aaaa5 5555555aaaa ? restrictions none length 64 bits type read address xxxx 0b08 and 0c power on value x ? 5555aaaaaaaa5555 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 the phy interface (linkc) page 427 of 676 14.16: linkc passed tx data register the bits in this register are passed over phy transmit data i/o 15-8 when using an eight bit wide phy data bus. length 8 bits type read/write address xxxx 0b40 power on value x ? 00 ? restrictions none bit(s) name description 7-0 passed to fytdat(15 down to 8) pass to i/o line fytdat(15 down to 8), except in the case of the internal sonet/sdh framer. when the internal sonet/sdh framer is selected as the rx phy device, sig- nals fytdat(15 down to 13) are used as the rx hdlc interface, unless a 16-bit wide external tx phy is also selected, then they are used as data lines.
IBM3206K0424 ibm processor for network resources preliminary nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 428 of 676 pnr25.chapt05.01 august 14, 2000 entity 15: nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data this entity controls the signals of the npbus. the phy registers are accessible to the processor by way of the address space of the IBM3206K0424. in addition, the operation of the front end is affected by the npbus status register. this entity also contains the crisco processor which can initialize chip registers at boot time by reading a data stream from eprom which specifies the address of registers and data values to which the registers are to be initialized. in general, the data stream consists of a series of single-byte instruction operation codes, followed by an address and data values. 15.1: npbus control register this register is used to report phy level hardware errors and interrupts. see note on set/clear type regis- ters on page 93 for more details on addressing. length 29 bits type clear/set address xxxx 2000 and 004 power on value x ? 0002010 ? restrictions none enable phy addr/data multiplexing status led 4 toggle status led 3 toggle status led 2 toggle status led 1 toggle status led 4 flashing status led 3 flashing status led 2 flashing status led 1 flashing status led 4 on status led 3 on status led 2 on status led 1 on +utp/-stp interface select disable driving the np address over the enstate(47 - 32) pins enable carrier detect led enable phy data bus parity detection invert interrupt inputs and phy reset access internal sonet framer register space phy bus interface type enable hardware error to disable phy reboot serial/parallel eprom remove internal sonet framer from reset state force a phy logic reset enable the front end pb0phy2 control external eprom type reserved 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 28 enable phy addr/data multiplex- ing this bit set to ? 1 ? will enable the ale1, ale2, and ale3 control lines for phy and par- allel eprom accesses so that additional address bytes can be latched for up to 24meg of addressing. since there is an access speed penalty for this, the default is a ? 0 ? for this function. 27 status led 4 toggle when this bit is set, the state of bit 19 of this register will be toggled by repeatedly set- ting bit 19.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 429 of 676 26 status led 3 toggle when this bit is set, the state of bit 18 of this register will be toggled by repeatedly set- ting bit 18. 25 status led 2 toggle when this bit is set, the state of bit 17 of this register will be toggled by repeatedly set- ting bit 17. 24 status led 1 toggle when this bit is set, the state of bit 16 of this register will be toggled by repeatedly set- ting bit 16. 23 status led 4 flashing when set to ? 1 ? , this bit will flash status indicator led 4. bit 19 of the register will over- ride this bit. 22 status led 3 flashing when set to ? 1 ? , this bit will flash status indicator led 3. bit 18 of the register will over- ride this bit. 21 status led 2 flashing when set to ? 1 ? , this bit will flash status indicator led 2. bit 17 of the register will over- ride this bit. 20 status led 1 flashing when set to ? 1 ? , this bit will flash status indicator led 1. bit 16 of the register will over- ride this bit. 19 status led 4 on when set to ? 1 ? , this bit will turn on status indicator led 4. 18 status led 3 on when set to ? 1 ? , this bit will turn on status indicator led 3. 17 status led 2 on when set to ? 1 ? , this bit will turn on status indicator led 2. 16 status led 1 on when set to ? 1 ? , this bit will turn on status indicator led 1. 15 +utp/-stp interface select this bit controls a chip output pin to switch high or low and can be used to select differ- ent phy interfaces, etc. when this bit is off, or a logical ? 0 ? , the chip output is high, or a logical ? 1 ? . 14 disable driving the np address over the enstate(47 - 32) pins for debug reasons, the driven of the address for eprom and phy fetches can be turned off with this bit. 13 enable carrier detect led when set to ? 1 ? , this bit allow indicator led 1 to reflect the status of carrier detect. this is a chip input. 12 enable phy data bus parity detection when set to ? 1 ? , if a parity error occurs on the phy data bus during a phy register access, bit 1 of the npbus status register will be set. 11 enable 16 data bit mode for phy reg accesses when this bit is ? 1 ? , the upper eight bits of a 16-bit phy data (bits 15-8) bus will be transferred over 47- 40 bits of the enstate chip i/o bus. 10 access internal sonet framer register space in memory mapped mode when this bit is ? 0 ? , the external phy register space can be accessed through phy 1 registers or phy 2 registers. also, the sonet framer register space can be accessed through the eprom access registers, npbus eprom address/command register and npbus eprom data register. by providing the byte framer address (see sonet framer core (framr chiplet address mapping) on page 525) in the npbus eprom address/command register, the byte data can be read or written from the npbus eprom data register. when this bit is set to ? 1 ? , the internal sonet framer registers can be accessed (see sonet framer core (framr chiplet address mapping) on page 525). the full offset range for this access is x'2100' to x'2fff'. 9 phy bus interface type when this bit is ? 0 ? , phy access speed is 200 ns (suni-like interface). when a ? 1 ? , access requires an acknowledge input response. this is to support a utopia-like micro-processor interface. 8 enable hardware error to disable phy allows bit 4 (master enable) of the intst control register to reset bit 4 of this register (disables front end logic). this function assumes that bit 4 of the intst control reg- ister has already been enabled and that either a hardware or software event has turned the bit off. 7 reboot serial/parallel eprom this bit will restart the external serial or parallel eprom initialization code. 6 remove internal sonet framer from reset state this bit powers up to a zero and keeps the internal sonet framer in reset mode. set- ting this bit to a 1 will enable normal operation. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 430 of 676 pnr25.chapt05.01 august 14, 2000 5do phy reset force a phy logic reset. before any software reset, turn this bit on and off for the phy specified amount of time. if the ibm atm-tc (25 mbps endec) is used, this bit will power-up to an active reset (since the input to the endec is positive reset). this bit must then be turned off for normal operation. 4 enable enable the front end. when this bit is ? 0 ? , no data will be transmitted to or received from the phys or the IBM3206K0424. see bit 8 for more information on control of this bit. 3-2 pb0phy2 control encoded control for the pb0phy2 output pin. the enabled of pibselo overrides these bits and is controlled by pcint cascade control register. x ? 0 ? enable pb0phy2 pin x ? 1 ? enable pbdatap pin and its detection of valid parity. x ? 2 ? enable mpmdsel pin x ? 3 ? reserved 1 external eprom type this bit will set at reset time as to what type of eprom is detected. when set, a serial eprom has been detected. when a ? 0 ? , parallel eprom is assumed (or none at all). this will also indicate from what type of device a pci rom access will retrieve vpd data. 0 reduce serial eprom clock when set to ? 1 ? , this bit is used for speeding up sim time for the serial eprom. it will change the time period for the serial eprom clock from 10 s to 85 ns. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 431 of 676 15.2: npbus status register this register is used to report phy level hardware errors and interrupts. see note on set/clear type regis- ters on page 93 for more details on addressing. length 7 bits type clear/set address xxxx 2028 and 02c power on value x ? x1 ? , where x is determined by which type of crisco ipl eprom is used restrictions none parallel eprom access complete serial eprom access failed serial eprom access complete internal sonet framer interrupt interrupt phy1 phy data bus parity error crisco execution complete 6543210 bit(s) name description 6 parallel eprom access complete the requested action to the parallel eprom has been completed. (see npbus eprom address/command register on page 433). 5 serial eprom access failed the requested action to the serial eprom has missed an acknowledge sequence while trying to complete the action. (see npbus eprom address/command register on page 433). 4 serial eprom access complete the requested action to the serial eprom has been completed. (see npbus eprom address/command register on page 433). 3 internal sonet framer interrupt the internal framer has signaled an interrupt. 2 interrupt phy1 this bit indicates that an interrupt occurred on phy 1. 1 phy data bus parity error when set to ? 1 ? , a data parity was detected over the phy data eight-bit bus. parity checked is odd. 0 crisco execution complete external serial/parallel eprom initialization has run and is completed.
IBM3206K0424 ibm processor for network resources preliminary nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 432 of 676 pnr25.chapt05.01 august 14, 2000 15.3: npbus interrupt enable register this register is used to mask bits from the npbus status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit in the npbus status register are set, the npbus status bit will be set in intst interrupt source. see note on set/clear type registers on page 93 for more details on addressing. see npbus status register on page 431 for the bit descriptions. length 6 bits type clear/set address xxxx 2008 and 00c power on value x ? 00 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 433 of 676 15.4: npbus eprom address/command register used to accessed a maximum of 2k external serial eprom or 16 meg of parallel eprom or the sonet framer core. this register is used access bytes from the external eprom or the sonet framer core. length 32 bits type read/write address xxxx 2010 power on value x ? 00000100 ? restrictions none reserved framer access: not read/write execute sonet framer access execute parallel eprom access more bytes to read/write serial eprom not read/write execute serial eprom access eprom/extended phy address 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-30 reserved reserved. 29 framer access: not read/write this bit set to ? 1 ? will cause a write function to the sonet framer core. this bit set to ? 0 ? will cause a read function to the sonet framer core. 28 execute sonet framer access this bit will start a read or write function to the sonet framer core. this bit will auto reset after the command is issued. 27 execute parallel eprom access this bit will start a read or write function to the parallel eprom. this bit will auto reset after the command is issued. 26 more bytes to read/write serial eprom this bit set to ? 1 ? will help speed up sequential accesses to the serial eprom. if writ- ing, there is a limit as to how many bytes can be written before the serial eprom write buffer is full. typical range is from two to eight bytes, depending on the device. 25 not read/write this bit set to ? 1 ? will cause a write function to the serial/parallel eprom. this bit set to ? 0 ? will cause a read function to the serial/parallel eprom. 24 execute serial eprom access this bit will start a read or write function to the serial eprom. this bit will auto reset after the command is issued. 23-0 eprom/extended phy address this holds the address field that will be used to address the serial/parallel eprom. it is also where the 15 - 8 address bits will be held if addressing a phy with more addressability than eight bits.
IBM3206K0424 ibm processor for network resources preliminary nodal processor bus interface (npbus)/crisco processor for register initialization from eprom data page 434 of 676 pnr25.chapt05.01 august 14, 2000 15.5: npbus eprom data register used to accessed a maximum of 2k external serial eprom or 16 meg of parallel eprom. 15.6: phy 1 registers this address range provides access to the phy 1 hardware. the details of the registers can be found in the specific publication for the phy hardware. 15.7: phy 2 registers this address range provides access to the phy 2 hardware. it should be noted that not all applications of IBM3206K0424 will use this access port. the details of the registers can be found in the specific publication for the phy hardware. length 32 bits type read/write address xxxx 2018 power on value x ? 00000000 ? restrictions none reserved read data reserved write data 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-24 reserved reserved. 23-16 read data holds the data that was read back from the serial/parallel eprom. 15-8 reserved reserved. 7-0 write data holds the data that is destined to be written to the serial/parallel eprom. length 256 doublewords (only lowest eight bits valid) type read/write address xxxx 2400 - 7ff power on value reference the phy-specific publication. restrictions reference the phy-specific publication. length 256 doublewords (only lowest eight bits valid) type read/write address xxxx 2800 - bff power on value reference the phy-specific publication. restrictions reference the phy-specific publication.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 on-chip checksum and dram test support (chksm) page 435 of 676 hardware protocol assist entities entity 16: on-chip checksum and dram test support (chksm) functional description the chksm entity has two functions: first, it is capable of initializing and/or testing packet and control memory; second, it can perform tcp checksums (two ? s complement, 16-bit sum with "end-around-carry"). 16.1: chksm base address register the chksm base address register indicates the starting address of a test operation or checksum calcula- tion. the base address can be set up with any alignment and valid address. this register increments with each read or write to memory. on a test mode error, the register holds the address of the 64-bit word which was read in error. length 32 bits type read/write address xxxx 0a00 power on value x ? 00000000 ? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register on page 440)
IBM3206K0424 ibm processor for network resources preliminary on-chip checksum and dram test support (chksm) page 436 of 676 pnr25.chapt05.01 august 14, 2000 16.2: chksm read/write count register the chksm read/write count register indicates the count of remaining bytes of a checksum operation. this register keeps track of how many bytes remain in the current checksum operation and is decremented with each read or write operation. any length can be set in the 30 lower significant bits. the upper two bits of this register can be written when starting a checksum operation instead of writing the control register. length 32 bits type read/write address xxxx 0a04 power on value x ? 00000000 ? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register on page 440) st-ck cl-ip remaining bytes 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 st-ck start a checksum operation. when this bit is written, bits 0 and 1 in the control register are set, and a check- sum operation is started. this should only be done when the rest of the control register bits are already set up. (that is, memory select, invert checksum,...) 30 cl-ip when this bit is written, it will clear the chksm tcp/ip checksum data register. this is the same as writing a ? 1 ? to bit 6 of the chksm control register.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 on-chip checksum and dram test support (chksm) page 437 of 676 16.3: chksm tcp/ip checksum data register the chksm tcp/ip checksum data register collects the 16-bit, two ? s complement, end-around-carry sum of the bytes. the source data is zero padded if it starts/ends on an odd byte boundary. the chksm tcp/ip checksum data register collects the 16-bit, two ? s complement, end-around-carry sum of the bytes. it can be seeded with an initial value. if it is not cleared before running a checksum, the previous value will act as a seed. this register can be cleared when starting a checksum operation by writing the clip bit in the chksm control register or by writing upper bits of chksm read/write count register. see chksm control register on page 440) for description of how to get/set current checksum alignment. 16.4: chksm ripple base register this register is used as base of a ripple pattern when in test mode. this register forms the base for a ripple pattern. each consecutive byte will be incremented by one or eight in the pattern. the ripple mode must be set in the control register to use this feature. the value of this register will change during the test operation. if a write and compare operation are being performed, this register needs to be setup again for the second operation. length 16 bits type read/write address normal sum xxxx 0a08 inverted sum xxxx 0a0c swapped sum xxxx 0a34 inverted swapped sum xxxx 0a38 power on value x ? 0000 ? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register on page 440) length 8 bits type read/write address xxxx 0a14 power on value x ? 00 ? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register on page 440)
IBM3206K0424 ibm processor for network resources preliminary on-chip checksum and dram test support (chksm) page 438 of 676 pnr25.chapt05.01 august 14, 2000 16.5: chksm ripple limit register this register is used to determine when the ripple base register overflows to zero. this register forms the compare value for the ripple base register. when the value of the ripple base register is greater than or equal to this register, the base register will overflow to zero. for example, when this register is set to four, the ripple base register would count from zero through four if counting by one. when set to 0x00, no overflows to zero occur. for example, when the ripple value is 0xff, and you are count- ing by eight, the next value would still be seven. if counting by one, then the next value would be zero. this register should be written before the ripple base. 16.6: chksm interrupt enable register used to specify which status register bits should be used to generate interrupts. see note on set/clear type registers on page 93 for more details on addressing. see chksm control register on page 440) for the bit descriptions. length 8 bits type read/write address xxxx 0a10 power on value x ? ff ? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register on page 440) length 12 bits type clear/set address xxxx 0a20 and 24 power on value x ? ffe ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 on-chip checksum and dram test support (chksm) page 439 of 676 16.7: chksm status register used to relay chksm status information. see note on set/clear type registers on page 93 for more details on addressing. length 12 bits type clear/set address xxxx 0a18 and 1c power on value x ? 01 ? restrictions the count zero bit is not writable. tex -- test error in byte 7-0 lck -- comet lock te1 -- test error msw te0 -- test error lsw cz -- count zero 11109876543210 bit(s) name description 11-4 tex -- test error in byte 7-0 when these bits are set, the checksum has determined that a read comparison error was encountered in the corresponding byte. byte 0 is bits 63 - 56 in a 64-bit long word. 3 lck -- comet lock when this bit is set, the checksum has determined that comit has ceased operation for some reason, or a virtual error was detected. 2 te1 -- test error msw when this bit is set, checksum has determined that a read comparison error was encountered in the most significant 32-bit word. 1 te0 -- test error lsw when this bit is set, the checksum has determined that a read comparison error was encountered in the least significant 32-bit word. 0 cz -- count zero this bit is set when the terminal count of an operation is reached.
IBM3206K0424 ibm processor for network resources preliminary on-chip checksum and dram test support (chksm) page 440 of 676 pnr25.chapt05.01 august 14, 2000 16.8: chksm control register the various bits in this register control the mode in which the checksum entity operates. see note on set/clear type registers on page 93 for more details on addressing. length 13 bits type clear/set address xxxx 0a28 and 2c power on value x ? 00 ? restrictions none cl-ff -- clear to all ones ex-al -- expose alignment hi-lo -- hi lo word sw-sum -- swap checksum in-sum -- invert checksum rp-add -- ripple addend cl-ip -- clear ip rp -- ripple ms -- memory select rw -- r/-w test mode tm -- test mode et -- enable tcp checksum updates ee -- enable entity chksm 1211109876543210 bit(s) name description 12 cl-ff -- clear to all ones when this bit is set, the chksm tcp/ip checksum data register is set to 0xffff when it is cleared. when this bit is cleared, the chksm tcp/ip checksum data register is set to ? 0 ? . this option should be used if the tcp/ip checksum should never be set to ? 0 ? (0xffff is ? 0 ? also). 11 ex-al -- expose alignment when this bit is set, the internal checksum alignment is exposed for reading/writing. for writes, bit 16 of the write data is used to set the internal alignment. for reads, the alignment is exposed in bit 16 or bit 0 depending on the value of the hi-lo bit in this register. this can be useful if doing non-consecutive multiple part check sums (need to preserve alignment between chunks). when this bit is cleared, the internal checksum aliment is not exposed. it is always cleared when the cl-ip bit in this register is set. normally, the internal alignment is calculated and maintained across consecutive check sums. 10 hi-lo -- hi lo word when this bit is set, the checksum data register data is placed in the most significant 16 bits of the 32-bit value read. when this bit is cleared, the checksum data register data is placed in the least significant 16 bits of the 32-bit value read. this bit does not affect how writes to the checksum data register occur; the data from the least signifi- cant 16 bits is always used. 9 sw-sum -- swap checksum when this bit is set, the checksum data register data is byte-swapped when read. when this bit is cleared, the checksum data register data is read normally. there are also new checksum data register addresses that can be read that do the same thing as this control bit. this bit is depreciated. 8 in-sum -- invert checksum when this bit is set, the checksum data register data is inverted when read. when this bit is cleared, the checksum data register data is read normally. there are also new checksum data register addresses that can be read that do the same thing as this control bit. this bit is depreciated.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 on-chip checksum and dram test support (chksm) page 441 of 676 debugging register access 16.9: chksm internal state internal state of checksum. note: this register should not be written unless specifically directed to do so by ibm technical support. 7 rp-add -- ripple addend when this bit is set, the ripple base register counts up by one. when this bit is cleared, the ripple base register counts up by eight. 6 cl-ip -- clear ip when this bit is written, it will clear the chksm tcp/ip checksum data register and itself. the result of this will be that this bit will never be read as a ? 1 ? . the internal align- ment is also cleared. 5 rp -- ripple when this bit is set, a ripple pattern will be used in both the read and write test modes. the ripple pattern is used instead of the constant test pattern. when this bit is reset, the constant test pattern is used for the test mode data. 4 ms -- memory select when this bit is set, all chksm memory accesses are to the control memory. when this bit is cleared, all chksm memory accesses are to the packet memory. 3 rw -- r/-w test mode when this bit is set, the entity will take the data that is read and compare it to the test/ripple pattern. when this bit is reset, the checksum entity will write data using the test/ripple pattern to the dram. 2 tm -- test mode when this bit is set, the entity will take the data that is read and compare it to the test/ripple pattern, or will write data using the test/ripple pattern to the dram depend- ing on the setting of the rw bit. in both cases, the reading or writing will continue until either an error is encountered or the chksm read/write count register counts down to ? 0 ? . when this bit is reset, the checksum entity will operate as described by the other bits. test and chksm modes are mutually exclusive, and test mode takes precedence. 1 et -- enable tcp checksum updates when this bit is set, the entity will collect the tcp checksum in the chksm tcp/ip checksum data register. when this bit is reset, the chksm tcp/ip checksum data register will not be changed by data that is read from the dram. test and chksm modes are mutually exclusive, and test mode takes precedence. 0 ee -- enable entity chksm when this bit is set, the entity will run as specified. when this bit is reset, the entity will not run. length 3 bits type read/write address xxxx 0a3c power on value x ? 00000000 ? restrictions none bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary on-chip checksum and dram test support (chksm) page 442 of 676 pnr25.chapt05.01 august 14, 2000 software use of chksm this section outlines some ways chksm can be set up and used. test mode possible patterns in test mode, a 64-bit pattern is written/compared to/with memory. there are several different patterns that can be used: constant test pattern when in test mode, and the rp bit is cleared, the chksm ripple base regis- ter is replicated eight times to form a 64-bit pattern. ripple pattern with increment of 1 when in test mode and the rp bit is set and rp-add is set and chksm ripple limit register is set to ? 0 ? , a 64-bit pattern is generated using the chksm ripple base register as a base. for example, if the chksm ripple base register is set to ? 1 ? , the following pattern is generated: 0102030405060708 0203040506070809 030405060708090a 0405060708090a0b ripple pattern with increment of 8 when in test mode and the rp bit is set and rp-add is cleared and chksm ripple limit register is set to ? 0 ? , a 64-bit pattern is generated using the chksm ripple base register as a base. for example, if the chksm ripple base register is set to ? 1 ? , the following pattern is generated: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 191a1b1c1d1e1f20 ripple pattern with ripple limit each of the above ripple patterns can also make use of the chksm ripple limit register. by setting this register, the user can control when the ripple pattern rolls over to zero. for example, when the chksm ripple limit regis- ter is set to three in increments by one mode the ripple pattern looks like: 0102030405060708 0203040506070809 030405060708090a 0001020304050607 0102030405060708 0203040506070809 030405060708090a similarly, when the chksm ripple limit register is set to ten, in incre- ment-by-eight mode, the ripple pattern looks like: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 0001020304050607
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 on-chip checksum and dram test support (chksm) page 443 of 676 initializing packet/control memory the following list shows the steps to use chksm to initialize packet or control memory: make sure chksm is in diagnostic mode, and other mode bits are reset set the start address by writing the base address set up the read/write count with number of bytes to initialize set up the test pattern register (ripple pattern register) with pattern to use set up the control register to enable test mode, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized now busy wait until operation is done (or set up interrupt enable register and wait for interrupt) testing packet/control memory the following list shows the steps to use chksm to test packet or control memory: first initialize memory with a pattern using above sequence make sure chksm is in diagnostic mode, and other mode bits are reset set the start address by writing the base address set up the read/write count with number of bytes to test (same as initialization value) the test pattern register (ripple pattern register) already contains the pattern set up the control register to enable test mode, turn on rw bit, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized now busy wait until operation is done (or set up interrupt enable register and wait for interrupt) when done, check the status register for any errors using ripple pattern generation/checking in packet/control memory the procedures to use the ripple pattern generation and checking are the same as using test write/read modes. the only difference is that the use ripple pattern mode bit must be set and the ripple pattern base register must be set up. running a tcp/ip checksum in packet/control memory the following list shows the steps to use chksm to generate/verify a tcp/ip checksum: make sure chksm is in diagnostic mode (not enabled) set the start address by writing the base address set up the read/write count with number of bytes to run checksum over, and set the upper two bits of the read/write count register. writing these upper two bits assumes other mode bits are set correctly (that is, memory bank select). now busy wait until operation is done (or set up interrupt enable register and wait for interrupt)
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 444 of 676 pnr25.chapt05.01 august 14, 2000 entity 17: processor core (pcore) pcore contains the on board processor and its local subsystems. the primary intent is to run available bit rate(abr) control software and user application code such as protocol termination/assist code. dcr interface the device control register (dcr) interface is a special processor bus to access local registers. these include serial port registers and various other registers. interrupt controller this logic manages the interrupts that are passed on to the cobra core. there are two levels of interrupt for the core: critical interrupts and normal interrupts. interrupts can be taken from both on chip and off chip sources. pcore has a variety of interrupt source and enable registers. bridge-address translation cobra core can access a variety of memory subsystems. facilities are provided that allow multiple subsystem accesses. processor address space is translated into target memory system addresses. for the most part, this allows the processor to be unaware of target memory address space considerations while running mainline code. ocm sram ocm is provided for the use of the processor. typical access time to the ocm is a single cycle, the same as for cache. address translation facilities have been added to make more efficient use of this memory via additional and extended bat registers. control memory control memory can be accessed by the processor. this memory may be mapped into the processor space in a number of different ways. packet memory packet memory can be accessed by the processor. this memory may be mapped into the processor space in a number of different ways. packet memory space also includes the virtual memory space of the IBM3206K0424. pci master interface-external the processor can access the pci bus through this interface. parts of pci space are mapped into processor space. there are a number of different ways that this can be mapped into processor space. processor register space this access mode of the pci master interface allows access to the internal IBM3206K0424 registers. this access is handled internally and does not affect the external pci bus.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 445 of 676 address translation examples tbd cobra structure cobra core data side lsu dmmu dcach ppocm (d-side)
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 446 of 676 pnr25.chapt05.01 august 14, 2000 cobra core "glossy" description the cobra core is a 32-bit powerpc risc embedded controller. it is fully compatible with the powerpc user instruction set architecture. details about the exact instruction set are described below. the cobra core has a powerpc instruction execution complex, separate 32k instruction and data caches, separate instruction and data 604-style mmus (not supported this pass), and 401-style interrupts, timers and debug facilities. the cobra core has a direct connection to 96k of on-chip memory which can be used for both instruction and data storage, as well as interfaces to the IBM3206K0424 ? s pci and register buses and both of the IBM3206K0424 ? s memory controllers. the dcr bus provides fastand private access to specific perfor- mance-sensitive registers. features instruction execution compatible with powerpc user instruction set architecture (uisa) separate branch, condition register, integer, and load/store units for super-scalar execution support for limited out-of-order execution dispatches/executes up to 2/4 instructions per clock cycle four stage pipeline allowing single cycle execution for most instructions 32x32-bit general purpose registers (gprs) single cycle loads and stores byte, halfword, word, and string accesses to any byte alignment supported in hardware hardware multiply and divide (multiply up to 10 cycles, divide up to 32 cycles) no fpu hardware - fpu instructions result in interrupts cobra core instruction side ppocm (i-side) bpu immu icach
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 447 of 676 timers 32-bit decrementer 64-bit time base programmable and fixed interval timers watchdog timer cobra core exceptions two priority levels - normal - uses srr0/1 (603) - critical - uses srr2/3 (401 extension) exception types - system reset (boot vector) - machine check - data storage interrupt - instruction storage interrupt - external - alignment - trap - invalid opcode - privilege violation - floating point unavailable - decrementer -system call -trace - system management (603) - programmable interval timer (401) - fixed interval timer (401) - watch dog timer (401) - critical interrupt (401) - debug interrupt (401)
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 448 of 676 pnr25.chapt05.01 august 14, 2000 optional architecture extensions programmable boot address (system interrupt vector) interrupt enhancements - individually re-locatable interrupts - individually programmable interrupt level (normal/critical) caches 32-byte cache lines (eight words/line) four-way set associative write back 32k instruction and data caches memory management real flat address mode supported interrupt controller two interrupt levels external to cobra: normal and critical three-way interrupts - from IBM3206K0424 to cobra - from cobra to pci - from pci to cobra debug support powerpc jtag debugger support (401 riscwatch) 401 debug instructions serial port debugger support pci debug access to jtag debug facilities interfaces on-chip memory 96k of on-chip memory can be used simultaneously by instruction and data accesses ocm basic dma controller provides bulk data moves to/from ocm IBM3206K0424 registers read/write access to the IBM3206K0424 register bus some critical registers are mapped to cobra core dcr register space pci bus read/write master access to pci bus currently no actual streaming/bursting supported pseudo bursting supported (multiple back to back single transfers) interrupt sink no arbitration supported (we are not a complete bridge) comet/pakit memory able to use both memory controllers for both instruction and data accesses
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 449 of 676 performance 133 mhz operating frequency performance estimates unavailable instruction set instruction set (with 401 as a base) supports all 401 instructions with the following additions/subtractions: added from 603 - mfsr, mfsrin, mtsr, mtsrin, tlbie, tlbld, tlbli, tlbsync ( note : virtual memory not supported this pass) - mftb (for 603 style time base support) removed from 401 - dcread, icread (replaced with spr access to the caches) - changed mfspr, mtspr (to accommodate new sprs) instruction set (with 603 as a base) supports all 603 instructions with the following additions/subtractions added from 401 - dccci, icbt, iccci, mfdcr, mtdcr, rfci, wrtee, wrteei removed from 603 - fxxxxx, lfxxx, stfxxx, mffxxx (floating point instructions), - eciwx, ecowx (powerpc i/o addressing not supported - only memory space addressing) - changed mfspr, mtspr (to accommodate new sprs) cobra instruction overview cobra core supports all of the instructions in either the powerpc 603 user's manual (mpr603umu-01,mpc603um/ad) or the power pc 401 core user's manual (v0.07 1/28/978) with the following changes. if an instruction does not exist in both user's manuals, it is described below.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 450 of 676 pnr25.chapt05.01 august 14, 2000 cobra facilities overview the following registers are patterned after the registers in either the powerpc 603 user ? s manual (mpr603umu-01,mpc603um/ad) or the power pc 401 core user ? s manual (v0.07 1/28/978). differences between the two implementations and the cobra core implementations are detailed below. the registers are split into these functional groupings: machine control/status registers, branch control registers, debug control registers, special purpose facilities, interrupt and exception registers, timer registers, cache control registers, and translation control registers. source key: both - same bit definitions as 603 and 401 401 - same bit definitions as 401 603 - same bit definitions as 603 ppc - same bit definitions as general power pc architecture cobra - cobra configuration cobra instruction changes instruction(s) source description dccci, icbt, iccci 401 added for cache management mfdcr, mtdcr 401 added for dcr bus support rfci, wrtee, wrteei 401 added for 40x interrupt support mfsr, mfsrin, mtsr, mtsrin 603 added for 60x mmu support (not supported this pass) mftb 603 added for 60x style time base support tlbie 603 added for 60x mmu support (not supported this pass) tlbsync 603 added for 60x compatibility, acts as a no-op mfbus, mtbus cobra core added - see appendix: new instructions dcread, icread 401 removed - cache layout is different dcba 405 not supported - 405 only instruction tlbre, tlbsx(.), tlbwe 405 removed - 40x style mmu not supported eciwx, ecowx 603 removed - only memory space addressing supported fxxxxx 603 removed floating point support lfd, lfdu, lfdux, lfdx, lfs, lfsu, lfsux, lfsx 603 removed floating point support mffs, mffsb0, mffsb1, mffsf, mffsfi 603 removed floating point support stfd, stfdu, stfdux, stfdx, stfiwx, stfs, stfsu, stfsux, stfsx 603 removed floating point support tlbld, tlbli 603 removed - 603 style mmu support, may add next pass
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 451 of 676 machine control/status registers register name spr number source por value notes cr na both x ? 00 00 00 00 ? hid0 1023 cobra x ? 00 00 00 fc ? ear 282 603 not supported, writes ignored, reads as zeros. msr na cobra x ? 00 00 00 40 ? xer 1 both x ? 00 00 00 00 ? mchk-on 688/689 cobra x ? 00 00 00 00 ? machine check enable - set bits off/ set bits on pvr 287 cobra x ? 10 10 00 00 ? branch control registers register name spr number source por value notes ctr 9 both x ? 00 00 00 00 ? lr 8 both x ? 00 00 00 00 ? debug register name spr number source por value notes dabr 1013 ppc not implemented, use dac1 dac1 1014 401 x ? 00 00 00 00 ? dbcr 1010 401 x ? 00 00 00 00 ? dbdr 1011 401 x ? 00 00 00 00 ? dbsr 1008 401 x ? 00 00 00 00 ? iabr 1010 603 not implemented, use iac1 iac1 1012 401 x ? 00 00 00 00 ? special purpose facilities register name spr number source por value notes sprg0 272 both x ? 00 00 00 00 ? sprg1 273 both x ? 00 00 00 00 ? sprg2 274 both x ? 00 00 00 00 ? sprg3 275 both x ? 00 00 00 00 ? sprg4-7 276-279 cobra x ? 00 00 00 00 ? read/write sprg4-7 68-71 cobra x ? 00 00 00 00 ? read only
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 452 of 676 pnr25.chapt05.01 august 14, 2000 interrupt and exception registers register name spr number source por value notes dar 19 603 x ? 00 00 00 00 ? dear 19 401 same as dar with different address dsisr 18 603 x ? 00 00 00 00 ? esr 980 401 x ? 00 00 00 00 ? only mci, pil, ppr, ptr, dst, and pfeu bits implemented evpr 982 401 x ? 00 00 00 00 ? srr0 26 both x ? 00 00 00 00 ? srr1 27 both x ? 00 00 00 00 ? when hid0(27) = 0 (603 mode), upper 16 bits act as status; the lower 16 bits are set from the msr. when hid0(27) = 1 (401 mode), all bits are set from the msr. srr2 990 401 x ? 00 00 00 00 ? behaves like srr0; used for critical level interrupts. srr3 991 401 x ? 00 00 00 00 ? behaves like srr; used for critical level interrupts. timer registers register name spr number source por value notes dec 22 603 x ? ff ff ff ff ? pit 987 401 x ? 00 00 00 00 ? tbhi 988 401 x ? 00 00 00 00 ? upper half of 64-bit time base register. r/w, privileged spr. tblo 989 401 x ? 00 00 00 00 ? lower half of 64-bit time base register. r/w, privileged spr. tbhu 972 401 x ? 00 00 00 00 ? upper half of 64-bit time base register. r-only, non-privileged spr. tblu 973 401 x ? 00 00 00 00 ? lower half of 64-bit time base register. r-only, non-privileged spr. tbl 284 603 x ? 00 00 00 00 ? same as tblo, but write only tbu 285 603 x ? 00 00 00 00 ? same as tbhi, but write only tbl 268 603 x ? 00 00 00 00 ? tbr (not spr) same as tblu tbu 269 603 x ? 00 00 00 00 ? tbr (not spr) same as tbhu tcr 986 401 x ? 00 00 00 00 ? tsr 984 401 x ? 00 00 00 00 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 453 of 676 cache control registers register name spr number source por value notes dccr 1018 401 x ? 00 00 00 00 ? dlcr 917 cobra x ? 00 00 00 00 ? bits 0-15 correspond to target tags 0-15, enabling auto data cache line locking dtwf 919 cobra x ? 00 00 00 00 ? bits 0-15 correspond to target tags 0-15, enabling target word first data cache fills iccr 1019 401 x ? 00 00 00 00 ? ilcr 916 cobra x ? 00 00 00 00 ? bits 0-15 correspond to target tags 0-15, enabling auto instruction cache line lock- ing itwf 918 cobra x ? 00 00 00 00 ? bits 0-15 correspond to target tags 0-15, enabling target word first instruction cache fills cdcbr 983 401 not implemented dcwr 954 401 not implemented icdbdr 979 401 not implemented translation registers register name spr number source por value notes sdr1 25 603 x ? 00 00 00 00 ? not supported - translation disabled this pass sgr 53 401 x ? 00 00 00 00 ? has no affect this pass. all storage is non-guarded. sler 55 401 not supported - writes ignored, reads as ? 0 ? stt0 912 cobra x'00 00 00 00' when ir=0 or dr=0, these registers are used to assign target tags to instruction or data memory accesses. the mapping is stt0(0:3) = 0x00000000 - 0x07ffffff through stt3(28:31) = 0xf8000000 - 0xffffffff. stt1 913 cobra x'00 00 00 00' stt2 914 cobra x'00 00 00 00' stt3 915 cobra x'00 00 00 00' sr0-15 na 603 x'00 00 00 00' not supported - translation disabled this pass dbat0u 536 603 x'00 00 00 00' not supported - translation disabled this pass dbat0l 537 603 x'00 00 00 00' not supported - translation disabled this pass dbat1u 538 603 x'00 00 00 00' not supported - translation disabled this pass dbat1l 539 603 x'00 00 00 00' not supported - translation disabled this pass dbat2u 540 603 x'00 00 00 00' not supported - translation disabled this pass dbat2l 541 603 x'00 00 00 00' not supported - translation disabled this pass dbat3u 542 603 x'00 00 00 00' not supported - translation disabled this pass dbat3l 543 603 x'00 00 00 00' not supported - translation disabled this pass dbat4u 568 cobra x'00 00 00 00' not supported - translation disabled this pass dbat4l 569 cobra x'00 00 00 00' not supported - translation disabled this pass dbat5u 570 cobra x'00 00 00 00' not supported - translation disabled this pass dbat5l 571 cobra x'00 00 00 00' not supported - translation disabled this pass
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 454 of 676 pnr25.chapt05.01 august 14, 2000 dbat6u 572 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass dbat6l 573 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass dbat7u 574 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass dbat7l 575 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat0u 528 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat0l 528 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat1u 530 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat1l 531 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat2u 532 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat2l 533 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat3u 534 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat3l 535 603 x ? 00 00 00 00 ? not supported - translation disabled this pass ibat4u 560 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat4l 561 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat5u 562 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat5l 563 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat6u 564 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat6l 565 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat7u 566 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass ibat7l 567 cobra x ? 00 00 00 00 ? not supported - translation disabled this pass exception vector override registers register name spr number source por value notes evc-off 700 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evc-on 701 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evov-off 702 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evov-on 703 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-mc 720 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-dsi 721 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-isi 722 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-ex1 723 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-aln 724 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-inv 725 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-prv 726 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-trp 727 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-fpu 728 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. translation registers (continued) register name spr number source por value notes
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 455 of 676 cobra specific register definitions for most of the registers named above, either a 40x or 60x spec will give the bit definition. there are a few registers which are different enough that they are described in detail below. evr-dec 729 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-sc 730 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-trc 731 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-smi 732 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-pit 733 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-fit 734 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-wdt 735 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-ex2 752 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. evr-dbg 753 cobra x ? 00 00 00 00 ? see cobra core exceptions on page 447. internal debug access address map unit debug bus address range bpu internals x ? 000 ? - x ? 07f ? reg internals x ? 080 ? - x ? 0ff ? lsu internals x ? 100 ? - x ? 17f ? fxu internals x ? 180 ? - x ? 1bf ? icache internals x ? 1c0 ? - x ? 1ff ? immu internals x ? 200 ? - x ? 2bf ? dcache internals x ? 2c0 ? - x ? 2ff ? dmmu internals x ? 300 ? - x ? 3bf ? reserved x ? 3c0 ? - x ? 3ff ? exception vector override registers (continued) register name spr number source por value notes
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 456 of 676 pnr25.chapt05.01 august 14, 2000 17.1: hardware implementation detail 0 register (hid0) enables caches and controls architecture specific functionality. this register controls whether cobra core acts as a 40x or 60x series processor and allows the different features of each architecture to be individually selected. length 32 bits type read/write address 1023 power on reset value x ? 00 00 00 fc ? (40x mode) x ? 80 00 00 00 ? - alternative value (60x mode suggested value) restrictions no-op touch instructions reserved disable decrementer disable decrementer srr1/3 style ip/evpr override debug mode select we enable reserved data cache enable instruction cache enable disable instruction/cr-logical-op pairing disable instruction/branch pairing disable conditional dispatch disable instruction pipelining allow data machine checks to be imprecise reserved enable checkstop on machine check 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 no-op touch instructions 0 = touch instructions work; 1 = touch instructions disabled 30 reserved reserved 29 disable decrementer when ? 0 ? , the decrementer register is a free running countdown register which causes a decrementer interrupt when it decrements through ? 0 ? . when ? 1 ? , the decrementer register does not decrement. 28 disable alignment interrupts on lmw/stmw when ? 0 ? , lmw/stmw instructions to non-word aligned addresses cause alignment inter- rupts (60x mode). when ? 1 ? , lmw/stmw instructions never cause alignment interrupts (40x mode). 27 srr1/3 style when ? 0 ? , interrupts cause srr1/3 to receive interrupt codes in bits 0:15, and msr con- tents in bits 16:31. likewise, rfi/rfci restore bits 16:31 of srr1/3 to the msr. when ? 1 ? , interrupts cause srr1/3 to receive msr contents in bits 0:31. likewise, rfi/rfci restore bits 0:31 of srr1/3 to the msr. status is stored in esr register regardless.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 457 of 676 26 ip/evpr override when ? 1 ? , evpr contents are used as the upper 16 bits of the exception vector, regardless of the value of msr(ip). when ? 0 ? , msr(ip) determines the upper 16 bits of the exception vector. hid0(ipo=26) msr(ip=25) exception vector 0 0 0x0000vvvv 0 1 0xfff0vvvv 1 - 0xeeeevvvv note: eeee = evpr register contents, vvvv = exception vector offset (for example, 0700) 25 debug mode select a ? 0 ? enables the be and se bits of the msr to function as a 60x, a ? 1 ? enables the msr(de) bit as a 40x. note : all 40x debug facilities (iac, dac, etc.) are disabled when in 60x mode. 24 we enable enables the msr(we) bit to cause a 40x style we. 0 = disabled, 1 = enabled 23-18 reserved reserved 17 data cache enable 0 = disable, 1 = enable 16 instruction cache enable 0 = disable, 1 = enable 15 disable instruction/cr-logical-op pairing 1 = disable, 0 = enable 14 disable instruction/branch pairing 1 = disable, 0 = enable 13 disable conditional dispatch 1 = disable, 0 = enable 12 disable instruction pipelining 1 = disable, 0 = enable 11 allow data machine checks to be imprecise setting this to ? 1 ? will result in a very small performance gain, at the expense of accu- racy in the srr0/2 of a machine check. 10-1 reserved reserved 0 enable checkstop on machine check when ? 1 ? , a machine check which occurs when msr(me)=0 will cause the hardware to freeze, maintaining much of the state of the machine. when ? 0 ? , the processor will attempt to continue execution when a machine check occurs when msr(me)=0. when msr(me)=1 and a machine check occurs, a machine check exception is taken regard- less of the setting of this bit. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 458 of 676 pnr25.chapt05.01 august 14, 2000 17.2: machine state register (msr) controls the run time state of the cobra core. length 32 bits type read/write address accessible via the mtmsr/mfmsr instructions power on reset value x ? 00 00 00 40 ? restrictions none reserved 603 ri reserved reserved 603 dr 603 ir ip reserved reserved 603 be / 401 de 603 se reserved 603/401 me 603/401 fp 603/401 pr 603/401 ee reserved 401 ce 401 we reserved 313029282726252423222120191817161514131211109876543210 bit(s) name description 31 reserved unimplemented (603/401 le). cobra core doesn ? t support little endian execution. 30 603 ri recoverable interrupt. this bit is cleared when an exception is taken. 29 reserved reserved 28 reserved reserved 27 603 dr translation is not supported. do not set this bit. 26 603 ir translation is not supported. do not set this bit. 25 ip in combination with hid0(ipo = 26), this bit determines the upper 16 bits of an excep- tion vector. see hardware implementation detail 0 register (hid0) on page 456 for full details. 24 reserved reserved 23 reserved unimplemented (603 fe1). cobra core doesn ? t support floating point. 22 603 be / 401 de if hid0(25) = 0 this is 603 be otherwise it is 401 de. 21 603 se if hid0(25) = 0 this is 603 se otherwise it is a read/write bit with no affect. 20 reserved unimplemented (603 fe0). cobra core doesn ? t support floating point. 19 603/401 me enables machine check exceptions. if this bit is ? 1 ? , a machine check will cause a machine check exception to occur. if this bit is ? 0 ? , a machine check will cause cobra core to halt execution (if hid0(0) = 1), or the machine check will be ignored (if hid0(0) = 0). 18 603/401 fp if fp=0, all floating point instructions cause a floating point disabled interrupts. if fp=1, all floating point instructions cause illegal instruction interrupts. 17 603/401 pr privilege instruction restricted. if this bit is ? 1 ? , attempting to execute a privileged (supervisor) instruction will result in a privilege violation exception. if this bit is ? 0 ? , all instructions may be executed normally. 16 603/401 ee external interrupt enable. used to mask off non-critical level exceptions. 15 reserved unimplemented (603 ile) cobra core doesn't support little endian execution.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 459 of 676 14 401 ce enables critical level exceptions. critical level exceptions are higher priority than nor- mal exceptions. any exception can be assigned critical level in cobra core. this bit can only mask off exceptions programmed to be critical level through other cobra core facilities. by default, no exception is critical level. note: the 60x doesn ? t have the concept of critical level exceptions. the 40x has both critical level exceptions and a critical interrupt. the critical interrupt is just a second external interrupt. in the 40x, specific exceptions were hard wired to be critical level, and the rest were hard wired to be normal level. 13 401 we if hid0(24) = 0, this is a r/w bit with no affect (603 pow), otherwise it is the (401 we) bit. when this bit is set, the processor halts operation until this bit is cleared (via an interrupt). 12-0 reserved reserved bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 460 of 676 pnr25.chapt05.01 august 14, 2000 17.3: exception status register (esr) when an exception occurs, this register is updated to indicate which condition caused the exception. if an exception vector can only be reached by one exception, this register is cleared. length 32 bits type read/write spr address 980 power on reset value x ? 00 00 00 00 ? restrictions none reserved pfeu program reserved dst data storage reserved ptr program ppr program pil program reserved mci 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-14 reserved reserved 13 pfeu program floating point enabled, but instruction unimplemented exception. 12-9 reserved reserved 8 dst data storage a store instruction or (dcbz/dcbi) caused the data exception. 7 reserved reserved 6 ptr program program - trap instruction exception 5 ppr program program - privileged instruction exception 4 pil program program - illegal instruction exception 3-1 reserved reserved 0 mci machine check - instruction
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 461 of 676 17.4: machine check enable register (mchk) when an exception occurs, this register is updated to indicate which condition caused the exception. if an exception vector can only be reached by one exception, this register is cleared. length 32 bits type clear/set spr address 688/689 power on reset value x ? 00 00 00 00 ? restrictions none reported spr multiple ack returned machine check reported spr multiple data returned machine check reserved reported lsu no valid instruction machine check reserved reported data machine check reported instruction machine check reserved enable spr multiple ack returned machine check enable spr multiple data returned machine check reserved enable lsu no valid instruction machine check reserved enable data machine check enable instruction machine check reserved 313029282726252423222120191817161514131211109876543210 bit(s) name 31 reported spr multiple ack returned machine check 30 reported spr multiple data returned machine check 29 reserved 28 reported lsu no valid instruction machine check 27-25 reserved 24 reported data machine check 23 reported instruction machine check 22-16 reserved 15 enable spr multiple ack returned machine check 14 enable spr multiple data returned machine check 13 reserved 12 enable lsu no valid instruction machine check 11-9 reserved
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 462 of 676 pnr25.chapt05.01 august 14, 2000 8 enable data machine check 7 enable instruction machine check 6-0 reserved bit(s) name
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 463 of 676 pcore register definitions 17.5: pcore control register the pcore control register provides control information about pcore operations. this is the pcore control register. it is used to control operation. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 4000 and 004 power on reset value x ? 00 0e 40 09 ? restrictions caution must be used when asserting some of the bits during operation. reserved clear instruction cache clear data cache spr state machine abort control memory access priority high on latency timer max crossing control memory access priority high on write fifo full control memory access priority high packet memory access priority high on latency timer max crossing packet memory access priority high on write fifo full packet memory access priority high lock arbit on error pci master write around fifo disable packet memory write around fifo disable control memory write around fifo disable reserved jtag hold most recent error status cobra hold most recent event status auto ack on hang or error detected fdma virtual memory error normal/critical interrupt dcache virtual memory error normal/critical interrupt memory lock normal/critical interrupt 64 bit dcr primitives target access dead man timer master disable serial port receive interrupt priority serial port transmit interrupt priority pci master wait on writes enable boot time system reset exception disable lock pcore on error cobra core run state diagnostic/operational mode 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-30 reserved reserved 29 clear instruction cache this bit will cause the instruction cache to clear itself to a known state. it will also cause the processor to be in stop state when this happens. it will be cleared when the cache has finished. 28 clear data cache this bit will cause the data cache to clear itself to a known state. it will also cause the processor to be in stop state when this happens. it will be cleared when the cache has finished. 27 spr state machine abort this bit will put the spr access machine into a reset state, so it should be used by set- ting and then clearing.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 464 of 676 pnr25.chapt05.01 august 14, 2000 26 control memory access priority high on latency timer max crossing when set, control memory accesses will switch to high priority when the control mem- ory latency counter crosses the high priority crossover register value. 25 control memory access priority high on write fifo full when set, control memory accesses will switch to high priority when the control mem- ory write around fifo is full. 24 control memory access priority high when set, control memory accesses will be at high priority always. 23 packet memory access priority high on latency timer max crossing when set, packet memory memory accesses will switch to high priority when the packet memory latency counter crosses the high priority crossover register value. 22 packet memory access priority high on write fifo full when set, packet memory accesses will switch to high priority when the packet mem- ory write around fifo is full. 21 packet memory access priority high when set, packet memory accesses will be at high priority always. 20 lock arbit on error when set to ? 1 ? , will cause a lock command to be issued to arbit to halt the memory subsystem. 19 pci master write around fifo disable disables the write around buffer for pci master. when enabled, write data from either the icach or dcach is buffer through this fifo on writes. 18 packet memory write around fifo disable disables the write around buffer for packet memory. when enabled, write data from either the icach or dcach is buffer through this fifo on writes. 17 control memory write around fifo disable enables the write around buffer for control memory. when enabled write data from either the icach or dcach is buffer through this fifo on writes. 16-15 reserved reserved 15 disable xfer abort on pseudo core reset when this bit is written to ? 1 ? , transfer aborts on pseudo resets are disabled; when ? 0 ? , the core master state machines will be put into idle. 14 jtag hold most recent error sta- tus when this bit is written to ? 0 ? , the jtag error status register will free run. when set to ? 1 ? it will hold the most recent error status. 13 cobra hold most recent event status when this bit is written to ? 1 ? , cobra core hold it most recent internal event status. when set to ? 0 ? it will free run. 12 auto ack on hang or error detected when this bit is written to ? 0 ? , pcore will not auto ack on hang or error. this may leave the processor in a totally stuck state. however corrupted information may be stopped from entering the processor. when set to ? 1 ? and hang or error conditions manifest reads may return garbage and write data may be lost but the processor should not be stopped cold. 11 fdma virtual memory error nor- mal/critical interrupt when this bit is written to ? 0 ? , pcore will treat an IBM3206K0424 virtual memory write error as a critical interrupt. when it is ? 1 ? , this condition will be treated as a normal inter- rupt. 10 dcache virtual memory error nor- mal/critical interrupt when this bit is written to ? 0 ? , pcore will treat an IBM3206K0424 virtual memory write error as a critical interrupt. when it is ? 1 ? , this condition will be treated as a normal inter- rupt. 9 memory lock normal/critical interrupt when this bit is written to ? 0 ? , pcore will treat memory locked as a critical interrupt. when it is ? 1 ? , this condition will be treated as a normal interrupt. 8 64 bit dcr primitives when set, the three dcr primitives work in 64-bit mode. in this mode, the first access to the primitive register is to the upper 32 bits. the second reference is to the lower 32 bits. the second access triggers the completion of the operation at the destination. 7 target access dead man timer master disable when set, this will disable all of the target access dead man timers: pci master, control memory, packet memory, IBM3206K0424 registers and dcr. 6 serial port receive interrupt prior- ity when set, this will cause a the receive interrupt to be a critical interrupt. when not set, it is a regular interrupt. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 465 of 676 5 serial port transmit interrupt pri- ority when set, this will cause a the transmit interrupt to be a critical interrupt. when not set, it is a regular interrupt. 4 pci master wait on writes enable when set, this will cause the pci access machine to wait until the data is actually con- firmed written to the device. normally, this bit is set to off since it decreases perfor- mance when enabled. 3 boot time system reset excep- tion when set, this bit will issue a system boot reset exception to the cobra core proces- sor. it is reset by the cobra core processor after it has received the system reset exception. 2 disable lock pcore on error when this bit is set and an error occurs and the corresponding lock enable bit is set pcore will lock. this state is equivalent to being in diagnostic mode. 1 cobra core run state when set, this will place the cobra core into run state. when not set, the processor will quiesce and hold at idle. 0 diagnostic/operational mode when set, pcore is in diagnostic mode. when cleared, pcore is in operational mode. when in diagnostic mode, state machines are held in idle. if they are already active, when they next go to idle they will hold there. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 466 of 676 pnr25.chapt05.01 august 14, 2000 17.6: pcore reset control register the pcore reset control register provides control information about pcore reset operations. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 4000 and 004 power on reset value x ? 00 0e 00 09 ? restrictions caution must be used when asserting some of the bits during operation. reserved enable pseudo core resets for cobra core reset enable pseudo core resets for jtag core resets enable pseudo core resets for watch dog timer core resets disable all cobra core resets disable all jtag resets disable all watch dog timer resets 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-6 reserved reserved 5 enable pseudo core resets for cobra core reset when this bit is written to ? 0 ? , cobra core resets are converted to chip resets. when this bit is written ? 1 ? , a pseudo core reset is issued instead. 4 enable pseudo core resets for jtag core resets when this bit is written to ? 0 ? , cobra core resets are converted to chip resets. when this bit is written ? 1 ? , a pseudo core reset is issued instead. 3 enable pseudo core resets for watch dog timer core resets when this bit is written to ? 0 ? , cobra core watch dog timer core resets are converted to chip resets. when this bit is written ? 1 ? , a pseudo core reset is issued instead. 2 disable all cobra core resets when this bit is written to ? 1 ? , all cobra core resets are disabled. 1 disable all jtag resets when this bit is written to ? 1 ? , jtag resets are disabled. 0 disable all watch dog timer resets when this bit is written to ? 1 ? , watch dog timer resets are disabled.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 467 of 676 17.7: pcore status register the pcore status register provides status information about pcore operations. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address xxxx 4008 and 00c power on reset value x ? 00 00 80 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved data side machine check instruction side machine check condition detected data side machine check issued instruction side machine packet memory virtual ocm interrupt proxy dcr bus primitive hang serial port xmit interrupt serial port receive interrupt packet memory hang condition econtrol memory hang condition register hang condition pci master hang condition pcore locked 313029282726252423222120191817161514131211109876543210 bit(s) name description 31-14 reserved reserved 13 data side machine check condition detected a data side machine check condition was detected but not necessarily sent to the cobra core. 12 instruction side machine check condition detected an instruction side machine check condition was detected but not necessarily sent to the cobra core. 11 data side machine check issued a machine check has been issued to the cobra core due to a data side pcore error. 10 instruction side machine check issued a machine check has been issued to the cobra core due to an instruction side pcore error. 9 packet memory virtual write failure when this is set, a virtual write has failed to virtual memory. either a nak was returned during the write or while holding for error checking after the write. in either case, it indi- cates the required storage to complete the operation was not available. 8 ocm interrupt proxy when set, ocm is indicating an interrupt condition. 7 dcr bus primitive hang condition one of the dcr primitive accesses has timed out. 6 serial port xmit interrupt when the serial port surfaces a xmit interrupt it will be reflected here. 5 serial port receive interrupt when the serial port surfaces a receive interrupt, it will be reflected here.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 468 of 676 pnr25.chapt05.01 august 14, 2000 17.8: pcore user status register the pcore user status register provides user-defined status information about pcore software opera- tions. see note on set/clear type registers on page 93 for more details on addressing. 4 packet memory hang condition packet memory interface dead man timer has expired. 3 control memory hang condition control memory interface dead man timer has expired. 2 register hang condition register interface dead man timer has expired. 1 pci master hang condition pci master interface dead man timer has expired. 0 pcore locked this bit is set when locking is enabled; an error has occurred and the lock mask bit is set that matches the error. length 32 bits type clear/set dcr address x ? 200 and 201 ? power on reset value x ? 00 00 00 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. user defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 user defined reserved bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 469 of 676 17.9: pcore cobra core external status register the pcore cobra core external status register provides cobra core-defined status information about pcore. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set dcr address x ? 202 and 203 ? power on reset value x ? 00 00 00 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved fdma packet memory virtual write error critical interrupt fdma packet memory virtual write error normal interrupt data side packet memory virtual write error critical interrupt data side packet memory virtual write error normal interrupt memory controller locked critical interrupt memory controller locked non-critical interrupt serial port receive critical interrupt serial port receive non-critical interrupt serial port transmit critical interrupt serial port transmit non-critical interrupt internal critical interrupt internal non-critical interrupt external critical interrupt external non-critical interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-14 reserved reserved 13 fdma packet memory virtual write error critical interrupt this occurs when the packet memory controller returns an error on a packet virtual memory write and the fdma-side is accessing and this condition is set as critical. 12 fdma packet memory virtual write error normal interrupt this occurs when the packet memory controller returns an error on a packet virtual memory write and the fdma-side is accessing this condition is set as normal. 11 data side packet memory virtual write error critical interrupt this occurs when the packet memory controller returns an error on a packet virtual memory write and the d-side is accessing and this condition is set as critical. 10 data side packet memory virtual write error normal interrupt this occurs when the packet memory controller returns an error on a packet virtual memory write and the d-side is accessing this condition is set as normal. 9 memory controller locked critical interrupt this occurs when the memory controller is locked and this condition is set as critical. 8 memory controller locked non-critical interrupt this occurs when the memory controller is locked and this condition is set as non-criti- cal.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 470 of 676 pnr25.chapt05.01 august 14, 2000 7 serial port receive critical inter- rupt this occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. 6 serial port receive non-critical interrupt this occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. 5 serial port transmit critical inter- rupt this occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. 4 serial port transmit non-critical interrupt this occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. 3 internal critical interrupt this occurs when a bit in the IBM3206K0424 primary status register is set and the cor- responding critical interrupt enable is on. 2 internal non-critical interrupt this occurs when a bit in the IBM3206K0424 primary status register is set and the cor- responding non-critical interrupt enable is on. 1 external critical interrupt this occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. 0 external non-critical interrupt this occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 471 of 676 17.10: pcore cobra core external machine check status register the pcore cobra core external machine check status register provides cobra core machine check status information about pcore. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set dcr address x ? 25c and 25d ? power on reset value x ? 00 00 00 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. pci master access error control memory locked packet memory locked fdma packet virtual memory error fdma pci master error fdma control memory locked error fdma packet memory locked error reserved dcr register error fdma packet memory locked error data packet virtual memory error data pci master error data control memory locked error data packet memory locked error reserved instruction illegal tag access instruction pci master error instruction control memory locked error instruction packet memory locked error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 pci master access error this occurs when the pci master machine returns an error and no requestor currently owns the machine. 30 control memory locked this occurs when packet memory is in a locked state. 29 packet memory locked this occurs when packet memory is in a locked state. 28 fdma packet virtual memory error this occurs when packet memory indicates a write error during access of a virtual buffer. 27 fdma pci master error this occurs when a pci master access has an error returned while the data path is accessing it. 26 fdma control memory locked error this occurs when control memory locks while the data path is actively accessing it. 25 fdma packet memory locked error this occurs when packet memory locks while the data path is actively accessing it. 25-21 reserved reserved. 21 dcr register error this occurs when a fatal error, typically a hang, occurs on a dcr register timeout. 20 fdma packet memory locked error this occurs when packet memory locks while the data path is actively accessing it. 20 data register error this occurs when a fatal error, typically a hang, occurs on an IBM3206K0424register timeout.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 472 of 676 pnr25.chapt05.01 august 14, 2000 19 data packet virtual memory error this occurs when packet memory indicates a write error during access of a virtual buffer. 18 data pci master error this occurs when a pci master access has an error returned while the data path is accessing it. 17 data control memory locked error this occurs when control memory locks while the data path is actively accessing it. 16 data packet memory locked error this occurs when packet memory locks while the data path is actively accessing it. 15-4 reserved reserved. 3 instruction illegal tag access this occurs when the instruction side specifies the register space or ocm for the instruction source via the icache. since there are no physical connections, these accesses can not occur. 2 instruction pci master error this occurs when pci master access has an error returned while the instruction path is accessing it. 1 instruction control memory locked error this occurs when control memory locks while the instruction path is actively accessing it. 0 instruction packet memory locked error this occurs when packet memory locks while the instruction path is actively accessing it. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 473 of 676 17.11: pcore jtag debug control register the pcore jtag debug control register enables the jtag port or a pci interface processor debugger to control the processor core. length 32 bits type read/write address xxxx 4200 power on reset value x ? 00 00 00 00 ? restrictions none stop processor block folding single step reset control unconditional debug event freeze timers while stopped reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 stop processor this bit forces the processor to halt execution. 30 block folding the processor normally dispatches two instructions at a time. setting this bit forces instruction dispatches to be serialized. 29 single step setting this bit when the processor is stopped causes the processor to execute one or two instructions depending on the value of bit 30. this bit automatically clears itself after one cycle. 28-27 reset control these bits potentially generate one of three resets depending on their value. they automatically reset to b ? 00 ? after one cycle. the bits decode as follows: ? 00 ? no reset ? 01 ? core reset ? 10 ? chip reset ? 11 ? system reset 26 unconditional debug event this bit generates an interrupt to the processor. it automatically resets to b ? 0 ? after one cycle. 25 freeze timers while stopped this bit freezes the state of all timers in the core if the processor is stopped. 24-0 reserved reserved.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 474 of 676 pnr25.chapt05.01 august 14, 2000 17.12: pcore jtag debug status register the pcore jtag debug status register returns core status. length 32 bits type read only address xxxx 4204 power on reset value x ? 00 00 00 00 ? restrictions none reserved instruction side interrupt data side tlb miss instruction side tlb miss reserved protection error alignment error illegal/privileged/trap instruction exception system call return from interrupt instruction return from critical interrupt instruction instruction side machine check processor wait state instruction stuff overrun processor stopped 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-14 reserved reserved. 13 instruction side interrupt 12 data side tlb miss 11 instruction side tlb miss 10 reserved reserved. 9 protection error 8 alignment error 7 illegal/privileged/trap instruction exception 6system call 5 return from interrupt instruction 4 return from critical interrupt instruction 3 instruction side machine check 2 processor wait state the processor is in a wait state. 1 instruction stuff overrun the debug port has attempted to insert an instruction into the processor via the jtag instruction stuff buffer (jisb) and it was not accepted by the pro- cessor. the instruction must be reloaded into the jisb. 0 processor stopped
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 475 of 676 17.13: pcore jtag instruction stuff buffer the pcore jtag instruction stuff buffer is used to insert an instruction into the processor for execution. length 32 bits type read/write address xxxx 4208 power on reset value x ? 00 00 00 00 ? restrictions none user defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 instruction instruction to be passed from the jtag/pci debug interface to the core gprs.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 476 of 676 pnr25.chapt05.01 august 14, 2000 17.14: pcore jtag debug data register the pcore jtag debug data register enables passing data between the jtag/pci debug port and the general purpose registers of the processor core. length 32 bits type read/write address xxx 420c dcr address tbd power on reset value x ? 00 00 00 00 ? restrictions none user defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 data data to be passed to/from the jtag/pci debug interface to the core gprs.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 477 of 676 17.15: pcore cobra core boot address the pcore cobra core boot address provides cobra core its boot time address. this is the pcore register. it is used to provide the address that is used to fetch the first instruction. length 32 bits type read/write dcr address xxxx 4018 power on reset value x ? ff f0 01 00 ? restrictions none boot address disable evpr/ip override hid/msr on boot reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-2 boot address this is the address the processor will use at boot time. 1 disable evpr/ip override hid/msr on boot override msr settings on system reset exception to use all of the pcore cobra core boot address. 0 reserved reserved.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 478 of 676 pnr25.chapt05.01 august 14, 2000 17.16: pcore cobra core access priority control register the pcore cobra core access priority control register provides cobra core defined status information about pcore. it is used to control the order and priority of access to the various memory subsystems that the cobra core has access to. it is to be set up at initialization time an not dynamically changed. length 28 bits type read/write dcr address xxxx 401c power on reset value x ? 01 e4 e4 e4 ? restrictions for each controller accessed, the values cannot be duplicated. that is, all the prior- ities to a given target subsystem must be unique. reserved icache register access priority dcache register access priority fdma - packet memory access priority dcache - packet memory access priority icache - packet memory access priority write around fifo - packet memory access priority fdma - control memory access priority dcache - control memory access priority icache - control memory access priority write around fifo - control memory access priority fdma - pci master access priority dcache - pci master access priority icache - pci master access priority write around fifo - pci master access priority 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 27-26 reserved reserved 25 icache register access priority this sets the priority into the IBM3206K0424 register port. zero is low prior- ity; one is high priority. 24 dcache register access priority this sets the priority into the IBM3206K0424 register port. zero is low prior- ity; one is high priority. 23-22 fdma - packet memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 21-20 dcache - packet memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 19-18 icache - packet memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 17-16 write around fifo - packet memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 15-14 fdma - control memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 479 of 676 13-12 dcache - control memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 11-10 icache - control memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 9-8 write around fifo - control memory access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 7-6 fdma - pci master access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 5-4 dcache - pci master access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 3-2 icache - pci master access priority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority. 1-0 write around fifo - pci master access pri- ority this sets the priority of access to packet memory. zero is the lowest priority; three is the highest priority bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 480 of 676 pnr25.chapt05.01 august 14, 2000 17.17: pcore transaction dead man timer value registers these registers are used to load timers that count to zero from the value loaded in this register. the maximum wait for an i/o transaction is about 2ms when this is set to x ? ffff ? . the value of this register is written into the corresponding timer after the transaction is initiated with the target. it continues to then count down until the target responds or zero is reached in the timer. when the timer reaches zero, a status bit is set and action can be taken from there. length 16 bits type read/write address pci master dead man timer value xxxx 4020 IBM3206K0424 register dead man timer value xxxx 4024 control memory dead man timer value xxxx 4028 packet memory dead man timer value xxxx 402c dcr primitive access dead man timer value xxxx 40f8 power on reset value x ? ffff ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 481 of 676 17.18: pcore high priority access timer value registers these registers are used to load timers that count to zero from the value loaded in this register. the maximum wait for an i/o transaction is about 2ms when this is set to x ? ffff ? . the value of this register is written into the corresponding timer after the transaction is initiated with the target. it will continue to then count down until the target responds or zero is reached in the timer. when the timer reaches zero, a status bit is set and action can be taken from there. 17.19: pcore transaction dead man timer register these timers are used to time transactions that are valid but the target does not respond right away. the timer counts on a 7.5 ns time base. the maximum wait for an i/o transaction is about 2ms when the timer counts down from x ? ffff ? . this timer counts down to zero from the values set in the value register. when zero is reached, the transaction is considered broken and the request will be acknowledged back to the requestor. 17.20: pcore IBM3206K0424 shadow status register this register is used to shadow the intst interrupt source. the purpose of this register is to allow polling for IBM3206K0424 interrupts without having to use the pci bus. length 16 bits type read/write address control memory dead man timer value tbd packet memory dead man timer value tbs power on reset value x ? ffff ? restrictions none length 16 bits type read address pci master dead man timer value xxxx 40e0 IBM3206K0424 register dead man timer value xxxx 40e4 control memory dead man timer value xxxx 40e8 packet memory dead man timer value xxxx 40ec dcr primitive access dead man timer value xxxx 40f0 power on reset value x ? ffff ? restrictions none length 32 bits type read dcr address x ? 208 ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 482 of 676 pnr25.chapt05.01 august 14, 2000 17.21: pcore IBM3206K0424 packet last write with error address this register is used to shadow the intst interrupt source. the purpose of this register is to store the address associated with the previous virtual write error. 17.22: pcore IBM3206K0424 rxque master status register this register is used to shadow the rxque master status register. the purpose of this register is to allow fast access to rxque ? s master status register without having to use the regular register interface. 17.23: pcore IBM3206K0424 rxque enabled status register 1 this register is used to shadow the rxque enabled status register 1. the purpose of this register is to allow fast read access of the rxque enabled status register 1 without having to use the normal IBM3206K0424 register interface. length 32 bits type read address x ? 260 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read dcr address x ? 20f ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read dcr address x ? 250 ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 483 of 676 17.24: pcore IBM3206K0424 rxque enabled status register 2 this register is used to shadow the rxque enabled status register 1. the purpose of this register is to allow fast read access of the rxque enabled status register 2 without having to use the normal IBM3206K0424 register interface. 17.25: pcore IBM3206K0424 rxque upper queues status register this register is used to shadow the rxque upper queues status register. the purpose of this register is to allow fast read access of the rxque upper queues status register without having to use the normal IBM3206K0424 register interface. 17.26: pcore IBM3206K0424 rxque lower queues status register this register is used to shadow the rxque lower queues status register. the purpose of this register is to allow fast read access of the rxque lower queues status register without having to use the normal IBM3206K0424 register interface. length 32 bits type read address x ? 251 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read dcr address x ? 252 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read dcr address x ? 253 ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 484 of 676 pnr25.chapt05.01 august 14, 2000 17.27: pcore dmaqs master status register this register is used to shadow the dmaqs master status register. the purpose of this register is to allow fast read access of the dmaqs master status register without having to use the normal IBM3206K0424 register interface. 17.28: pcore dmaqs enabled status register this register is used to shadow the dmaqs master status register. the purpose of this register is to allow fast read access of the dmaqs master status register without having to use the normal IBM3206K0424 register interface. 17.29: pcore rxque queue length registers the pcore rxque queue length registers provide event enqueue queue lengths to the cobra core. reads from this address will return event queue lengths from rxque. length 32 bits type read address x ? 257 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read address x ? 25b ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type read/write address x ? 220 ? - x ? 22f ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 485 of 676 17.30: pcore dmaqs queue length registers the pcore dmaqs queue length registers provide dmaqs queue lengths to the cobra core. reads from this address will return dmaqs queue lengths from dmaqs. 17.31: pcore interrupt enable register this register is used to enable bits from the pcore status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit(s) in the pcore status register are set, the pcore interrupt to pcint will be enabled. see note on set/clear type registers on page 93 for more details on addressing. see pcore status register on page 467 for the bit descriptions. 17.32: pcore user interrupt enable this register is used to enable an interrupt based on bits from the corresponding pcore user status regis- ter and potentially generate interrupts to the control processor. when both a bit in this register and the corre- sponding bit(s) in the [tbd] register are set, the pcore status bit(s) will be set in the corresponding pcore user status register. see note on set/clear type registers on page 93 for more details on addressing. see pcore user status register on page 468 for the bit descriptions. length 32 bits type read/write address x ? 254 ? - x ? 256 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type clear/set address xxxx 4010 and 014 power on reset value x ? 00 00 80 00 ? restrictions none length 32 bits type clear/set address x ? 204 and 205 ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 486 of 676 pnr25.chapt05.01 august 14, 2000 17.33: pcore cobra core interrupt enable register this register is used to enable bits from the pcore cobra core external status register and generate inter- rupts to the cobra core processor. when both a bit in this register and the corresponding bit(s) in the pcore cobra core external status register are set, the cobra core interrupt to the cobra core core will be enabled. see note on set/clear type registers on page 93 for more details on addressing. see pcore status regis- ter on page 467 for the bit descriptions. 17.34: pcore cobra core external machine check enable register this register is used to enable bits from the pcore cobra core external machine check status register and generate machine checks to the cobra core processor. when both a bit in this register and the corre- sponding bit(s) in the pcore cobra core external machine check status register are set, the requisite cobra core machine check to the cobra core core will be enabled. see note on set/clear type registers on page 93 for more details on addressing. see pcore status register on page 467 for the bit descriptions. 17.35: pcore error lock enable register the pcore error lock enable register provides the ability to halt pcore when the corresponding status bit in the status register is set and locking is enabled. when a bit in this register corresponds to a bit that is set in the status register, the state machines in pcore will be held in idle state until the lock is disabled. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type clear/set address x ? 206 ? - x ? 207 ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type clear/set address x ? 25e ? - x ? 25f ? power on reset value x ? 00 00 00 00 ? restrictions none length 32 bits type clear/set address xxxx 4030 and 034 power on reset value x ? 00 00 fe 9f ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 487 of 676 17.36: pcore user error lock enable register the pcore user error lock enable register provides the ability to halt pcore when the corresponding status bit in the user status register is set and locking is enabled. when a bit in this register corresponds to a bit that is set in the status register, the state machines in pcore will be held in idle state until the lock is disabled. see note on set/clear type registers on page 93 for more details on addressing. 17.37: pcore rxque event interface enqueue register the pcore rxque event interface enqueue register provides event enqueue interface for the cobra core. writes to this address will enqueue an event to an rxque queue. 17.38: pcore dmaqs dma enqueue register the pcore dmaqs dma enqueue register provides dmaqs enqueue interface for the cobra core. writes to this address will enqueue an event to an rxque queue. length 32 bits type clear/set address xxxx 4038 and 03c power on reset value x ? ff ff ff ff ? restrictions none length 32 bits type read/write address x ? 230 - x ? 23f ? power on reset value x'00 00 00 00' restrictions none bit(s) name description 31-7 event data user defined event data 6-0 event signature tbd processor event signature length 32 bits type read/write address x ? 258 - x ? 25a ? power on reset value x'00 00 00 00' restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 488 of 676 pnr25.chapt05.01 august 14, 2000 17.39: pcore rxque event interface deque register the pcore rxque event interface deque register provides event deque interface for the cobra core. reads from this address return an event. 17.40: pcore cobra spr read data access register the pcore cobra spr read data access register stores the data from the requested cobra facility on a read. these are message passing facilities. they are used for inter-device communication. these facilities, with their control register bits, allow for either interrupt or polling-based message passing from the cobra core to a pci bus device. 17.41: pcore cobra spr write data access register this register stores the data from the pcirequested cobra facility on a read. these are message passing facilities. they are used for inter-device communication. these facilities with their control register bits, allow for either interrupt or polling-based message passing from the cobra core to a pci bus device. length 32 bits type read address x ? 240 - x ? 24f ? power on reset value x'00 00 00 00' restrictions none length 32 bits type read only address xxxx 4040 power on reset value x'00 00 00 00' restrictions none length 32 bits type write only address xxxx 40f4 power on reset value x'00 00 00 00' restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 489 of 676 17.42: pcore cobra spr access address register this is the pcore spr access address register. it is used to access the internal facilities in cobra. this includes spr/dcr and debug facilities. the address is for a facility and represents a four-byte access. length 32 bits type read/write address xxxx 4044 power on reset value x ? 80 00 00 00 ? restrictions none address type reserved address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-30 address type these bits describe the address type. ? 00 ? reserved ? 01 ? spr access ? 10 ? dcr access ? 11 ? register/debug access 29-10 reserved reserved 9-0 address address of target register.
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 490 of 676 pnr25.chapt05.01 august 14, 2000 17.43: pcore address translation offset address facilities the pcore address translation offset address facilities provides the offset that is added to the cobra real address to create the target subsystem address. when an address is issued from the cobra core core it is accompanied by four target translation bits. the translation bits indicate which translation facility is to be used to translate the processor "real" physical address into a target system actual address. this grouping provides for the offset addresses for each target memory system. the offset is added to the cobra real address to create the target system address. the following is a list of targets, each with their own translation facilities. pcore address translation offset address facilities: ? 0000 ? ocm (translation provided for in the mmus) ? 0001 ? packet memory view 0 ? 0010 ? packet memory view 1 ? 0011 ? packet memory view 2 ? 0100 ? IBM3206K0424 registers ? 0101 ? control memory view 0 ? 0110 ? control memory view 1 ? 0111 ? control memory view 2 ? 1000 ? pci master access (non IBM3206K0424) view 0 ? 1001 ? pci master access (non IBM3206K0424) view 1 ? 1010 ? pci master access (non IBM3206K0424) view 2 ? 1011 ? pci master access (non IBM3206K0424) view 3 ? 1100 ? control/packet view 0 ? 1101 ? control/packet view 1 ? 1110 ? control/packet view 2 ? 1111 ? control/packet view 3 length 32 bits type read/write address packet memory offset view 0 xxxx 4048 packet memory offset view 1 xxxx 404c packet memory offset view 2 xxxx 4050 IBM3206K0424 registers offset view 0 xxxx 4054 control memory offset view 0 xxxx 4058 control memory offset view 1 xxxx 405c control memory offset view 2 xxxx 4060 pci master offset view 0 xxxx 4064 pci master offset view 1 xxxx 4068
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 491 of 676 17.44: pcore pci 64 bit address translation facilities the pcore pci 64 bit address translation facilities provide the upper thirty-two bits of address in 64-bit addressing mode. when an access is issued to the pci master interface in 64-bit addressing mode, these registers are used to create the upper 32 bits of the 64-bit address. pci master offset view 2 xxxx 406c ? pratbaa./pci master offset view 3 ? pratbba./control/packet memory offset view 0 ? pratbca./control/packet memory offset view 1 ? pratbda./control/packet memory offset view 2 ? pratbea./control/packet memory offset view 3 power on reset value x'00000000' restrictions none length 32 bits type read/write address/storage unit upper 32 address bits pci master view 0 xxxx 4084 upper 32 address bits pci master view 1 xxxx 4088 upper 32 address bits pci master view 2 xxxx 408c upper 32 address bits pci master view 3 xxxx 4090 power on reset value x'00000000' restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 492 of 676 pnr25.chapt05.01 august 14, 2000 17.45: pcore pci master target tag controls the pcore pci master target tag controls contains the control for each pci tag/view. this register contains bits for each of the four pci master views. length 32 bits type read/write dcr address xxxx 40fc power on reset value x ? 06 06 06 06 ? restrictions none user defined swap bytes view 3 swap words view 3 assume 64 bit xfer view 3 assume 32 bit xfer view 3 transfer type view 3 reserved swap bytes view 2 swap words view 2 assume 64 bit xfer view 2 assume 32 bit xfer view 2 transfer type view 2 reserved swap bytes view 1 swap words view 1 assume 64 bit xfer view 1 assume 32 bit xfer view 1 transfer type view 1 reserved swap bytes view 0 swap words view 0 assume 64 bit xfer view 0 assume 32 bit xfer view 0 transfer type view 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-30 reserved reserved 29 swap bytes view 3 when set, this bit tells the pci master logic to do byte swapping. 28 swap words view 3 when set, this bit tells the pci master to do word swapping. 27 assume 64 bit xfer view 3 when set, this bit tells the pci master logic to assume a 64-bit data access. 26 assume 32 bit xfer view 3 when set, this bit tells the pci master logic to assume a 32-bit data access. 25-24 transfer type view 3 these bits indicate the transaction type. ? 00 ? config cycle ? 01 ? i/o cycle ? 1- ? memory cycle 23-22 reserved reserved 21 swap bytes view 2 when set, this bit tells the pci master logic to do byte swapping. 20 swap words view 2 when set, this bit tells the pci master to do word swapping. 19 assume 64 bit xfer view 2 when set, this bit tells the pci master logic to assume a 64-bit data access. 18 assume 32 bit xfer view 2 when set, this bit tells the pci master logic to assume a 32-bit data access. 17-16 transfer type view 2 these bits indicate the transaction type. ? 00 ? config cycle ? 01 ? i/o cycle ? 1- ? memory cycle 15-14 reserved reserved 13 swap bytes view 1 when set, this bit tells the pci master logic to do byte swapping. 12 swap words view 1 when set, this bit tells the pci master to do word swapping. 11 assume 64 bit xfer view 1 when set, this bit tells the pci master logic to assume a 64 bit data access.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 493 of 676 10 assume 32 bit xfer view 1 when set, this bit tells the pci master logic to assume a 32 bit data access 9-8 transfer type view 1 these bits indicate the transaction type. ? 00 ? config cycle ? 01 ? i/o cycle ? 1- ? memory cycle 7-6 reserved reserved 5 swap bytes view 0 when set, this bit tells the pci master logic to do byte swapping. 4 swap words view 0 when set, this bit tells the pci master to do word swapping. 3 assume 64 bit xfer view 0 when set, this bit tells the pci master logic to assume a 64 bit data access. 2 assume 32 bit xfer view 0 when set, this bit tells the pci master logic to assume a 32 bit data access. 1-0 transfer type view 0 these bits indicate the transaction type ? 00 ? config cycle ? 01 ? i/o cycle ? 1- ? memory cycle bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 494 of 676 pnr25.chapt05.01 august 14, 2000 17.46: pcore last packet address register the pcore last packet address register is the last address to the packet memory bus at the time of the hang condition. when the system locks up, this register holds the last packet memory address that was or is currently being presented to the packet memory subsystem. 17.47: pcore last control address register the pcore last control address register is the last address to the control memory bus at the time of the hang condition. when the system locks up, this register holds the last control memory address that was or is currently being presented to the control memory subsystem. 17.48: pcore last pci lower address register the pcore last pci lower address register is the last address to the pci bus at the time of the hang condition. when the system locks up, this register holds the last pci bus address that was or is currently being presented to the control memory subsystem. length 32 bits type read address xxxx 4094 power on reset value x ? ff ff ff fc ? restrictions none length 32 bits type read address xxxx 4098 power on reset value x ? ff ff ff fc ? restrictions none length 32 bits type read address xxxx 409c power on reset value x ? ff ff ff fc ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 495 of 676 17.49: pcore last register address register the pcore last register address register is the last address to the pci bus at the time of the hang condi- tion. when the system locks up, this register holds the last pci bus address that was or is currently being presented to the control memory subsystem. 17.50: pcore sram base address the sram base address register is used to select the base address of the 4k byte window to access the sram. length 32 bits type read address xxxx 40a0 power on reset value x ? ff ff ff fc ? restrictions none length 32 bits (17:12) active type read/write address xxxx 40a4 power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 496 of 676 pnr25.chapt05.01 august 14, 2000 17.51: pcore read data transfer buffers the pcore read data transfer buffers hold the read data that is being transferred from one of the target subsystems and the cobra core. eight bytes are buffered on the interfaces except for the IBM3206K0424 register interface which buffers four bytes. 17.52: pcore write data transfer buffers the pcore write data transfer buffers hold the data that is being transferred between the cobra core and one of the target subsystems. eight bytes can be stored for each target subsystem, with the exception of the IBM3206K0424 register target which holds just four bytes. length 32 bits type read address pci upper read data transfer buffer xxxx 40a8 pci lower read data transfer buffer xxxx 40ac packet upper read data transfer buffer xxxx 40b0 packet lower read data transfer buffer xxxx 40b4 control upper read data transfer buffer xxxx 40b8 control lower read data transfer buffer xxxx 40bc IBM3206K0424 register space read data transfer buffer xxxx 40c0 power on reset value x ? 00000000 ? restrictions none length 32 bits type read address pci upper write data transfer buffer xxxx 40c4 pci lower write data transfer buffer xxxx 40c8 packet upper write data transfer buffer xxxx 40cc packet lower write data transfer buffer xxxx 40d0 control upper write data transfer buffer xxxx 40d4 control lower write data transfer buffer xxxx 40d8 IBM3206K0424 register space write data transfer buffer xxxx 40dc power on reset value x ? 00000000 ? restrictions none
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 497 of 676 17.53: pcore polling register the pcore polling register provides status information to pcore about IBM3206K0424 operations. it allows pcore to poll specific IBM3206K0424 status without using pci bus bandwidth. 17.54: pcore integer input rate conversion register this register is the integer input port for the rate conversion logic. an integer rate is placed in this register. the on board logic converts it to an abr rate format. length 32 bits type read dcr address x ? 20e ? power on reset value x ? 00 00 00 00 ? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved memory locked control memory locked packet memory locked virtual lock arbit lock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-5 reserved reserved. 4 memory locked memory is locked. 3 control memory locked control memory is locked. 2 packet memory locked packet memory is locked. 1 virtual lock vimem is the locker of memory. 0 arbit lock arbit is the locker of memory. length 32 bits type read/write dcr address x ? 20b ? power on reset value x ? 00 00 00 00 ? restrictions none
IBM3206K0424 ibm processor for network resources preliminary processor core (pcore) page 498 of 676 pnr25.chapt05.01 august 14, 2000 17.55: pcore abr output rate register this register is the output port of the rate conversion logic. an integer rate was placed in the integer input register. the logic converts it to an abr rate and places the result in this register. 17.56: pcore debug states control this register serves as the pcore control for external debug states. the intst debug states control for the address range desired must be set to select these pcore state bits. if that is done, then this register acts to select the four ranges. see bit descriptions below. length 16 bits type read dcr address x ? 20c ? power on reset value x ? 00 00 ? restrictions none length 32 bits type read/write address xxxx 431c power on reset value x ? 0000 0000 ? restrictions none entity state mux control 4 (hardware debug) entity state mux control 3 (hardware debug) entity state mux control 2 (hardware debug) entity state mux control 1 (hardware debug) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-24 entity state mux control 4 (hardware debug) select of these bits allows internal state machines, counters, etc., to show up on chip outputs enstate(63 down to 48). selection encoding is the same as mux 1 control. 23-16 entity state mux control 3 (hardware debug) select of these bits allow internal state machines, counters, etc., to show up on chip outputs enstate(47 down to 32). selection encoding is the same as mux 1 control. 15-8 entity state mux control 2 (hardware debug) select of these bits allow internal state machines, counters, etc., to show up on chip outputs enstate(31 down to 16). selection encoding is the same as mux 1 control. 7-0 entity state mux control 1 (hardware debug) select of these bits allow internal state machines, counters, etc., to show up on chip outputs enstate(15 down to 0). x ? 00 ? disabled (no transition on outputs) x ? 01 ? select 15-0 states x ? 40 ? -x ? ff ? reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 processor core (pcore) page 499 of 676 17.57: pcore debug states config this register serves as the pcore configuration for external debug states. the intst debug states control for the address range desired must be set to select these pcore state bits. if that is done, then this register acts to select the characteristics according to the bit descriptions below. length 8 bits type read/write dcr address xxxx 4320 power on reset value x ? 00 ? restrictions none lsu selector(1) reg selector bpu config (1-0) reserved lsu selector(0) fxu selector 76543210 bit(s) name description 7 lsu selector(1) tbd 6 reg selector tbd 5-4 bpu config (1-0) tbd 3-2 reserved reserved 1 lsu selector(0) tbd 0 fxu selector tbd
IBM3206K0424 ibm processor for network resources preliminary powerpc on-chip memory (ppocm) entity page 500 of 676 pnr25.chapt05.01 august 14, 2000 entity 18: powerpc on-chip memory (ppocm) entity the ppocm entity is comprised of several sram arrays that provide a xxxk memory that may be used by the internal processor or by the IBM3206K0424. also included in ppocm is a dma controller that the proces- sor may use to do bulk data moves between the sram arrays and control memory, packet memory, or memory on an external pci device. the ppocm arrays will subsequently referred to as on-chip memory and the three external memories (control, packet, pci) just mentioned will subsequently be referred to collectively as off-chip memory. dma controller the dma controller moves data in eight byte aligned, eight byte portions. in real addressing mode, up to 64k bytes may be transferred at once. in virtual addressing mode, there are more restrictions. the dma must remain within the virtual 4k page for both the ppocm array address and the off-chip memory address. 18.1: ppocm control register this register contains information which controls the functions of the entity. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write dcr address 100 and 01 power on reset value x ? 00000000 ? restrictions none reserved dma blocking mode dma read not write start dma 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-4 reserved rserved 3-2 dma blocking mode these bits control how non-dma accesses to ppocm are handled while a dma is in progress. they are encoded as follows: ? 00 ? non-dma ppocm accesses are held off until the dma is complete. ? 01 ? non-dma ppocm accesses are held off only if the requester is attempting to use an array that will be involved in the dma. ? 10 ? reserved ? 11 ? reserved 1 dma read not write setting this bit will indicate the dma being set up is to transfer data from off-chip mem- ory into ppocm. clearing this bit indicates the dma should transfer data from ppocm to off-chip memory.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 powerpc on-chip memory (ppocm) entity page 501 of 676 18.2: ppocm status register this register contains status information that can be used to generate interrupts. see note on set/clear type registers on page 93 for more details on addressing. 0 start dma setting this bit initiates the dma operation. this bit will automatically clear when the dma is completed. length 32 bits type read/write dcr address 102 and 03 power on reset value x ? 00000000 ? restrictions none reserved zero length dma dma beyond bounds of on-chip memory on-chip address virtual mode page violation off-chip address virtual mode page violation virtual mode length error real addressing mode length error addressing mode error timeout complete 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-9 reserved reserved 8 zero length dma this bit, set to ? 1 ? , indicates that a dma with a length of zero was attempted. 7 dma beyond bounds of on-chip memory this bit, set to ? 1 ? , indicates that the on-chip address plus the dma length yields a value that exceeds the address pace of the on-chip memory. 6 on-chip address virtual mode page violation this bit, set to ? 1 ? , indicates that the on-chip virtual address provided to ppocm in combination with the dma length results in a virtual page cross. 5 off-chip address virtual mode page violation this bit, set to ? 1 ? , indicates that the off-chip virtual address provided to ppocm in combination with the dma length results in a virtual page cross. 4 virtual mode length error this bit, set to ? 1 ? , indicates that a virtual address mode dma was started and the value in the dma length register is greater than 4k. 3 real addressing mode length error this bit, set to a '1,' indicates that a real address mode dma was started and the value in the dma length register is greater than 64k. 2 addressing mode error this bit, set to a '1,' indicates that the off-chip memory and on-chip address written to the dma address registers must be either both real or both virtual. bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary powerpc on-chip memory (ppocm) entity page 502 of 676 pnr25.chapt05.01 august 14, 2000 18.3: ppocm interrupt enable register this register enables the bits of the status register to generate an interrupt. the bits of this register corre- spond to the bits of the status register. see note on set/clear type registers on page 93 for more details on addressing. 18.4: ppocm dma off-chip effective address register this register provides the dma controller the effective address of the off-chip portion of the dma. 1 timeout this bit, set to a ? 1, ? indicates that the dma timer expired. 0 complete this bit, set to a ? 1, ? indicates that the dma completed. the other bits in this register being a ? 0 ? will indicate a good completion. length 32 bits type read/write dcr address 104 and 05 power on reset value x ? 00000000 ? restrictions none length 32 bits type read/write dcr address 106 power on reset value x ? 00000000 ? restrictions none reserved reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-3 reserved reserved 2-0 reserved reserved bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 powerpc on-chip memory (ppocm) entity page 503 of 676 18.5: ppocm dma on-chip effective address register this register provides the dma controller the effective address of the on-chip portion of the dma. length 32 bits type read/write dcr address 107 power on value x ? 00000000 ? restrictions none reserved reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-3 reserved reserved 2-0 reserved reserved
IBM3206K0424 ibm processor for network resources preliminary powerpc on-chip memory (ppocm) entity page 504 of 676 pnr25.chapt05.01 august 14, 2000 18.6: ppocm dma length register this register provides the dma controller the length of the dma. the maximum dma length in real address- ing mode is x ? 00010000 ? (64k). the maximum dma length in virtual addressing mode is x ? 00001000 ? (4k). 18.7: ppocm dma timeout timer register this register is compared to a timer that begins running when bit 0 of the control register is set to ? 1 ? . when the timer reaches the value in this register, the dma is terminated and a status bit is set. the default value of x'ffffff' results in a timeout value of 125 ms. length 32 bits type read/write dcr address 108 power on value x ? 00000000 ? restrictions none reserved dma length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-16 reserved reserved 16-0 dma length only bits 16-3 are writable as dmas are done only in eight-byte segments. length 32 bits type read/write dcr address 109 power on value x ? 00ffffff ? restrictions none reserved dma length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-24 reserved reserved 23-0 dma length dma timeout value
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 rs-232 interface logic (rs-232) page 505 of 676 entity 19: rs-232 interface logic (rs-232) the rs232 entity provides a means by which an external debugger and the processor core can communi- cate. the rs-232 operates a one-or four-byte wide basis. rs-232 interface logic registers 19.1: rs-232 control register this register controls the operation of the rs-232 logic. see note on set/clear type registers on page 93 for more details on addressing. length 32 bits type read/write dcr address x ? 210 ? and 211 ? power on value x ? 00000000 ? restrictions none reserved byte wide mode internal wrap mode force rts active force dsr active internal force cts active internal stop bits parity enable odd/even parity transmit start rs-232 port enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-10 reserved reserved 9 byte wide mode this bit set to ? 1 ? makes the port operate in byte-wide mode. when a transmit is started, only bits 7-0 of the transmit buffer are sent. a receive interrupt is generated whenever a byte is received. 8 internal wrap mode this bit set to ? 1 ? connects the transmit data stream to the receive data stream. 7 force rts active this bit set to ? 1 ? forces rts to be driven active, regardless of what the transmit state machine is doing. 6 force dsr active internal this bit set to ? 1 ? forces dsr internal to rs-232 to appear active, regardless of the dsr input's state. 5 force cts active internal this bit set to ? 1 ? forces cts internal to rs-232 to appear active, regardless of the cts input's state. 4 stop bits this bit set to ? 1 ? indicates the port should use two stop bits. this bit set to ? 0 ? indicates the port should use one stop bit. 3 parity enable this bit set to ? 1 ? enables parity. 2 odd/even parity if parity is enabled, this bit, set to ? 1 ? , sets the parity type to odd. this bit set to ? 0 ? sets the parity type to even.
IBM3206K0424 ibm processor for network resources preliminary rs-232 interface logic (rs-232) page 506 of 676 pnr25.chapt05.01 august 14, 2000 19.2: rs-232 status register this register controls the operation of the rs-232 logic. see note on set/clear type registers on page 93 for more details on addressing. 1 transmit start this bit set to ? 1 ? initiates the transmission of what is in the transmit buffer. this bit is cleared by hardware when the transmission is complete. 0 rs-232 port enable this bit set to ? 1 ? enables the rs-232 port. length 32 bits type read/write dcr address x ? 212 and 213 ? power on value x ? 00000000 ? restrictions none reserved dsr inactive cts inactive transmit complete framing error overrun error parity error receive complete 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-7 reserved reserved 6 dsr inactive this bit set to ? 1 ? indicates dsr has gone inactive. 5 cts inactive this bit set to ? 1 ? indicates cts has gone inactive. 4 transmit complete this bit set to ? 1 ? indicates the current transmission has completed. 3 framing error this bit set to ? 1 ? indicates a framing error has been detected. 2 overrun error this bit set to ? 0 ? indicates four bytes were received before the previous (one-byte mode) or four bytes (four-byte mode) had been read from the receive buffer. 1 parity error this bit set to ? 1 ? indicates a parity error has been detected. 0 receive complete this bit set to ? 1 ? indicates data from a clean reception is in the receive buffer. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 rs-232 interface logic (rs-232) page 507 of 676 19.3: rs-232 interrupt enable register this register contains bits corresponding to the bits in the rs-232 status register. if a bit in this register is set and the corresponding bit is set in the rs-232 status register, an interrupt is generated. bits six through four generate a transmit interrupt and bits three through zero generate a receive interrupt. see note on set/clear type registers on page 93 for more details on addressing. 19.4: rs-232 transmit buffer this register contains the data to be sent over the rs-232 connection. length 7 bits type read/write dcr address x ? 214 and 215 ? power on value: x ? 00000000 ? restrictions none length 32 bits type read/write dcr address x ? 216 ? power on value x ? 00000000 ? restrictions none transmit data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 transmit data data to be sent over link. only bits 7-0 are sent in byte mode. the other bits are shifted, so the user can write all four bytes at once and just set the transmit bit four times.
IBM3206K0424 ibm processor for network resources preliminary rs-232 interface logic (rs-232) page 508 of 676 pnr25.chapt05.01 august 14, 2000 19.5: rs-232 receive buffer this register contains the data received over the rs-232 connection. once this buffer is full, software has four byte receive times minimum to read it before an overrun condition can occur. 19.6: rs-232 baud rate register this register contains the value used to determine the baud rate. the value to place in this register can be determined by this formula: baudrate = 133mhz/(8*(baud rate register + 1)). length 32 bits type read/write dcr address x ? 217 ? power on value x ? 00000000 ? restrictions none receive data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 receive data data received over the link. only bits 7-0 are valid in byte mode. length 16 bits type read/write dcr address x ? 218 ? power on value x ? 00000000 ? restrictions none reserved baud rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-16 reserved reserved 15-0 baud rate suggested values: x ? 120 ? - 56600 x ? 1b0 ? - 38400 x ? 240 ? - 28800 x ? 360 ? - 19200
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 rs-232 interface logic (rs-232) page 509 of 676 19.7: rs-232 cts/dsr glitch timer rate this register contains the number of (baud rate/8) clocks cts/dsr must be active/inactive before the state of cts/dsr is considered valid. transitions of shorter duration are assumed to be glitches. 19.8: rs-232 reset register this register resets the port. see note on set/clear type registers on page 93 for more details on address- ing. length 32 bits type read/write dcr address x ? 219 ? power on value x ? 00000020 ? restrictions none reserved glitch timer rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-16 reserved reserved 15-0 glitch timer rate length 32 bits type read/write dcr address x ? 21a and 21b ? power on value x ? 00000000 ? restrictions none reserved reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-1 reserved reserved 0 reset this bit set to ? 1 ? resets the port. the port will remain reset until this bit is cleared.
IBM3206K0424 ibm processor for network resources preliminary rs-232 interface logic (rs-232) page 510 of 676 pnr25.chapt05.01 august 14, 2000 19.9: rs-232 error forcing register this register can be used by diagnostics in a wrap environment (external or internal) to force frame and parity errors. overrun errors can be generated by sending four bytes, not reading the receive buffer, and sending four more bytes. length 32 bits type read/write dcr address x ? 21c ? power on value x ? 00000000 ? restrictions none reserved force framing error force parity error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-2 reserved reserved 1 force framing error setting this bit to a ? 1 ? forces the first frame bit to a b'0' on all transmits. 0 force parity error setting this bit to a ? 0 ? forces the receive logic to check for the opposite parity the trans- mit logic is using.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 reset and power-on logic (crset) page 511 of 676 entity 20: reset and power-on logic (crset) this entity performs bist and flush operations. chip software resets can be controlled by this entity, as well as the chip clock control. reset and power-on logic registers 20.1: reset status register this register is used to reflect the last type of reset was. a hardware reset will clear software reset status bits, but a software reset will not have an affect on the hardware status bits. length 8 bits type read/write address xxxx 0500 por value ? db00001 ? or ? db00010 ? , where b is the state of the bist results, and d is the pll phase detection. software reset value ? db001qq ? or ? db010qq ? , where q is the state of this bit before the software reset and b is the state of the bist results. restrictions none pci clock frequency change pll out-of-phase detect bist results pcore reset software reset software reset/bist por reset reserved 76543210 bit(s) name description 7 pci clock frequency change a value of ? 1 ? means that the real time pci frequency calculator has detected a major change in frequency and has calculated new range bits for the pll. 6 pll out-of-phase detect a value of ? 1 ? means that the out-of-phase detector circuit has triggered. this is just an indicator and is normal operation. 5 bist results a value of ? 1 ? means that a failure occurred within the bist checking logic. 4 pcore reset the pcore entity has been reset via a software reset request (bit 3 of software reset register). 3 software reset a software reset has occurred; the chip was flushed. 2 software reset/bist a software reset has occurred; and bist/flush was run. 1 por reset a por hardware reset that flushed the chip has occurred. 0 reserved
IBM3206K0424 ibm processor for network resources preliminary reset and power-on logic (crset) page 512 of 676 pnr25.chapt05.01 august 14, 2000 20.2: software reset enable register this register protects the software reset register. if this register is not set, then a reset will not occur. write a x ? b4 ? to this register to enable software reset. a software reset will clear this register. 20.3: software reset register this register generates a scan path flush reset of the chip, or software initiated run of bist, with the excep- tion of the registers in the reset entity. length 8 bits type read/write address xxxx 0504 por value x ? 0 ? restrictions none length 4 bit type write only address xxxx 0508 por value b ? 0 ? restrictions writing to this register without first setting the software reset enable register will have no affect. the register will not be set, thus the order of writing the enable and the software reset is important; the enable must be written first. additionally, all current operations being performed by the IBM3206K0424 must be terminated before doing a reset operation. a minimum number of enable bits to turn off would be bits four, five, and six in intst control register and bit 2 in pcint config word 1. pcore reset total software reset run bist software reset 3210 bit(s) name description 3 pcore processor reset writing this bit to a ? 1 ? causes the internal processor core to reset. 2 total software reset writing this bit to a ? 1 ? causes software reset and will be cleared after the software reset has occurred. the config registers in pcint will also be put to their reset state. 1run bist writing this bit to a ? 1 ? causes bist to run and will be cleared after the software reset has occurred. this function is primarily for pre-loading the bist registers to get more test coverage. 0 software reset writing this bit to a ? 1 ? causes software reset and will be cleared after the software reset has occurred. the config registers in pcint will not be affected by this reset.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 reset and power-on logic (crset) page 513 of 676 20.4: memory type register this register indicates the type of memory used for control and packet memory so that reset hardware will know how to properly preserve it during a reset. length 4 bits type read/write address xxxx 050c por value x ? 0 ? restrictions none packet memory type control memory type 3210 bit(s) name description 3-2 packet memory type decodes the same as bits nine through eight of comet/pakit control register on page 186. 1-0 control memory type decodes the same as bits nine through eight of comet/pakit control register on page 186.
IBM3206K0424 ibm processor for network resources preliminary reset and power-on logic (crset) page 514 of 676 pnr25.chapt05.01 august 14, 2000 20.5: crset pll range debug used to debug the ppl operation. length 32 bits type read only address xxxx 0518 por value x ? xxxxxxxx ? tbd pll range bit ? 1 ? (a) pll range bit ? 0 ? (a) pll range bit ? 1 ? (b) pll range bit ? 0 ? (b) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-4 tbd 3 pll range bit ? 1 ? (a) 2 pll range bit ? 0 ? (a) 1 pll range bit ? 1 ? (b) 0 pll range bit ? 0 ? (b)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 reset and power-on logic (crset) page 515 of 676 20.6: crset control register used to control pci frequency detection logic. length 13 bits type read/write address xxxx 0510 por value x ? 0330 ? disable delay pci rst# to the processor enable pcore IBM3206K0424 software reset enable pcore processor unit reset disable the frequency change detection interrupt disable the out-of-phase detection interrupt disable pll lock control encoded control for pll out-of-phase detection circuitry enable bits 2-0 encoded control for selecting clk speed 1211109876543210 bit(s) name description 12 disable delay pci rst# to the IBM3206K0424 setting this bit to a ? 1 ? will disable the function that delays a pci bus reset to the IBM3206K0424 if a serial eprom is attached and still busy accessing data from the prior reset. by disabling this function, any pci requirement to tri-state the i/o drivers would be met, but eprom initialization information would be lost. 11 enable pcore IBM3206K0424 software reset setting this bit to a ? 1 ? will enable the pcore entity to issue an IBM3206K0424 soft- ware reset. 10 enable pcore processor unit reset setting this bit to a ? 1 ? will enable the pcore entity to issue a processor unit reset. 9 disable the frequency change detection interrupt setting this bit to a ? 1 ? will disable using the frequency change detection bit as an inter- rupt source to intst. 8 disable the out-of-phase detection interrupt setting this bit to a ? 1 ? will disable using the out-of-phase detection bit as an interrupt source to intst. 7 disable pll lock control setting this bit to a ? 1 ? will disable using the pll lock output to make state transitions in the out-of-phase detection logic. 6-4 encoded control for pll out-of-phase detection circuitry these bits determine how much time buffering is allowed before an out-of-phase con- dition is detected. for a value of '000', a value of about 150 ps buffering is used. for each encoded increment value, an additional 150 ps is added. for example, the default value of three is about 600 ps of buffering. 3 enable bits 2-0 setting this bit to a ? 1 ? will enable bits 2-0 to override the pffcfg(2-0) bits that are strapped at the card level.
IBM3206K0424 ibm processor for network resources preliminary reset and power-on logic (crset) page 516 of 676 pnr25.chapt05.01 august 14, 2000 20.7: clock control register (nibble aligned) used to disable clocks for power conservation and provide the select a clock function for mpeg and front end support. to change a nibble field in this register, always set it to ? 0 ? first, and then to the new value. 2-0 encoded control for selecting clk speed these three bits have the same encoding as the chip i/o pffcfg(2-0) bits. length 29 bits type read/write address xxxx 0520 por value x'000e5532' framer tree disabled (framr) encoded control for bist speed reserved (encoded con- trol for pcore clock rate) encoded memory clock control encoded control for cell opportunity logic (cello) encoded control for mpeg clocking logic (mpegt) encoded control for transmit logic (linkt) and sonet framer (framr) encoded control for receive logic (linkr) and sonet framer (framr) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 28 framer tree disabled (framr) when set, this bit will disable the clock tree to the sonet framer logic. 27-24 reserved (for encoded control for bist clock rate) reserved 23-20 reserved (for encoded control for pcore clock rate) reserved 19-16 memory clock control encoding of bits: x'd ? use an early version of the clock x'e' use a nominal version of the clock x'f' use a late version of the clock 15-12 encoded control for cell opportu- nity logic (cello) same as bits 3-0. 11-8 encoded control for mpeg clock- ing logic (mpegt) same as bits 3-0. 7-4 encoded control for transmit logic (linkt) and sonet framer (framr) same as bits 3-0. bit(s) name description
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 reset and power-on logic (crset) page 517 of 676 3-0 encoded control for receive logic (linkr) and sonet framer (framr) below is the encoded value of the bits that select a given clock. always refer to ?select a clock" selection matrix below for inputs supported for each clock out type. x ? 0 ? turn this clock off. x ? 1 ? use the external mpeg oscillator. x ? 2 ? use the external rx clock. x ? 3 ? use the external tx clock. x ? 4 ? reserved x ? 5 ? use the internal 15 ns clock. assumes 33 or 66mhz pci clock. x ? 6 ? use the internal 30 ns clock. assumes 33 or 66mhz pci clock. x ? 7 ? use the internal 60 ns clock. assumes 33 or 66mhz pci clock. x ? 8 ? use the internal 120 ns clock. assumes 33 or 66mhz pci clock. x ? 9 ? use the internal 240 ns clock. assumes 33 or 66mhz pci clock. x ? a ? use the internal 480 ns clock. assumes 33 or 66mhz pci clock. x ? b ? use the differential receiver clock divided by eight. x ? c ? use the differential transmit clock divided by eight. x ? d ? use the differential receiver clock (chopped). x ? e ? use the differential high speed receiver clock (divided by 8 and 50% duty cycle). ? select a clock" selection matrix clock frequency base cello bco cco mpegt bmt cmt linkt(tx) btx ctx rtx linkr(rx) brx crx rrx nibble code hs rx rec diff osc x x ? e ? rx rec diff osc x x ? d ? tx/8 diff osc x x ? c ? rx/8 diff osc x x ? b ? 480 ns x x x x x ? a ? 240 ns x x x x x ? 9 ? 120 ns x x x x x ? 8 ? 60 ns x x x x x ? 7 ? 30 ns x x x x x ? 6 ? 15 ns x x x x x ? 5 ? reserved x ? 4 ? tx osc x x x x x ? 3 ? rx osc x x x x x ? 2 ? mpeg osc x x x x x ? 1 ? off x x x x x ? 0 ? control bits 15-12 11-8 7-4 3-0 bit(s) name description
IBM3206K0424 ibm processor for network resources preliminary reset and power-on logic (crset) page 518 of 676 pnr25.chapt05.01 august 14, 2000 20.8: cbist prpg results this is the prpg results register, updated after bist has run. it is used by the bist function for chip test. 20.9: cbist misr results this is the misr results register, updated after bist has run. it is used by the bist function for chip test. 20.10: cbist bist rate this register holds a counter value that separates the time between when the a clock and the b clock are launched during bist. this allows finer tuning to how much power bist uses versus how much testing gets done within the time allowed. it is used by the bist function for chip test. 20.11: cbist prpg expected signature this is the prpg signature register, which should be written by crisco code with the expected value of signature, based on the value in cbist cyct load value and the clock selected for bist to run from. it is used by the bist function for chip test. length 32 bits type read/write address xxxx 05b0 por value x ? ffffffff ? length 32 bits type read/write address xxxx 05b4 por value x ? 00000000 ? length 3 bits type read/write address xxxx 05b8 por value x ? 0 ? length 32 bits type read/write address xxxx 05c0 por value x ? ffffffff ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 reset and power-on logic (crset) page 519 of 676 20.12: cbist misr expected signature this is the misr signature register, which should be written by crisco code with the expected value of signature, based on the value in cbist cyct load value and the clock selected for bist to run from. it is used by the bist function for chip test. 20.13: cbist cyct load value this register is the loaded value for the cbist bist rate register. the time for bist to run can be computed by the following equation: (shift count) ? (c30 clock ? 2) ? (cycle time). it is used by the bist function for chip test. length 32 bits type read/write address xxxx 05c4 por value x ? 00000000 ? length 18 bits type read/write address xxxx 05c8 por value x ? 00005800 ?
IBM3206K0424 ibm processor for network resources preliminary jtag interface logic (cjtag) page 520 of 676 pnr25.chapt05.01 august 14, 2000 entity 21: jtag interface logic (cjtag) the cjtag entity contains logic to support a test access port (tap) controller compliant with the ieee 1149.1-1993 standard. the tap controller is accessed via the following five pins: the proper operation of these signals and the tap controller is defined in the ieee 1149.1-1993 standard. scanning the tap controller supports two types of scans: instruction scans and data scans. instruction scans control the type of operation and select which (if any) scan chains are involved in the operation. data scans generally clock the data on tdi into the selected scan chain. tck test clock. all activity of the jtag interface is clocked via tck. events occur on the rising or falling edge of tck. tck should have a maximum frequency of 20mhz. tms test mode select. test mode select is used to control state transitions in the tap controller. these transitions occur on the rising edge of tck. the btr selected for tms should be one with an internal pullup. tdi test data in. serial data input to the jtag logic. the btr selected for tdi should be one with an internal pullup. tdo test data out. serial data output to the jtag logic. trst test reset. asynchronous, minus active reset to the tap controller. assertion of this input causes the tap controller to reset and the jtag instruction register to load the idcode instruction. it is preferable to have trst be independent of any chip reset. with an independent reset, the jtag logic can be reset, allowing the chip ? s state to be examined without having to reset the core logic. the btr selected for trst should be one with an internal pullup.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 jtag interface logic (cjtag) page 521 of 676 21.1: instruction format the processor ? s jtag logic supports 32-bit instructions in one of two formats: the first format uses opcodes compliant with the ieee standard; the other supports opcodes as defined by the walnut chip that are compat- ible but not compliant with the ieee standard. as an instruction is scanned in, status for the previous instruc- tion is presented on tdo. instruction opcode odd parity reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 instruction opcode 16 in compatible mode, this is odd parity over bits 15-0 15-0 reserved reserved walnut compliant mode bad modifier parity detected bist running reserved hardwired to ? 01 ? as required by ieee specification 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 reserved 5 walnut compliant mode. 4 bad modifier parity detected. 3 bist running. 2reserved 1-0 hardwired to ? 01 ? as required by ieee specification.
IBM3206K0424 ibm processor for network resources preliminary jtag interface logic (cjtag) page 522 of 676 pnr25.chapt05.01 august 14, 2000 instructions the following instructions are supported: 21.2: idcode returns a 32-bit identification code when a data scan is performed. the idcode has the following structure: 21.3: sample/preload captures the state of the boundary scan i/o. as the values captured are scanned out, new values can be loaded into the boundary scan latches. this operation will not affect functional operation. 21.4: extest drives the values in the boundary scan latches onto their respective i/o. this function can be used in conjunction with sample/preload to perform card wire tests. 21.5: bypass selects the single bit bypass register for data scans. opcode x ? 0300 xxxx ? version number part number manufacturer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-28 version number this is set to x ? 4 ? for IBM3206K0424. 27-12 part number this is set to x ? 1d00 ? for IBM3206K0424. 11-0 manufacturer this is set to x ? 049 ? for ibm. opcode x ? 0402 xxxx ? opcode (compliant) x ? 00000000 ? opcode (compatible) x ? 0600 xxxx ? opcode (compliant) x ? ffffffff ? opcode (compatible) x ? ffffxxxx ? or x ? 0000xxxx ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt05.01 august 14, 2000 jtag interface logic (cjtag) page 523 of 676 21.6: runbist causes built in self test (bist) to execute. 21.7: bist_results returns a 64-bit value when a data scan is performed. bits 63-32 are the prpg and bits 31-0 are the misr from the bist logic. 21.8: walnut_mode this command enables walnut compatible mode. 21.9: compliant_mode this command enables jtag compliant mode. 21.10: stop this command halts the functional clocks of IBM3206K0424 in anticipation of a scan. after the stop command is scanned in, a data scan that takes the tap controller through the capture-dr, exit1-dr, and update-dr states should be performed. this will capture the state of the i/o so that they can be held in a known state if a scan command is issued. 21.11: scan this command causes tdi to be clocked into the scan chain during a subsequent data scan. the scan out of the scan chain is placed on tdo. this command will not work unless a stop command is sent down immediately before the scan command is issued. opcode x ? 0770 xxxx ? opcode x ? 1f02xxxx ? opcode x ? 3000 ? opcode x ? 33010000 ? opcode x ? 2002 ? opcode x ? 0802 ?
IBM3206K0424 ibm processor for network resources preliminary jtag interface logic (cjtag) page 524 of 676 pnr25.chapt05.01 august 14, 2000 21.12: scan_in this command causes tdi to be clocked into the scan chain during a subsequent data scan. tdo is forced to ? 0 ? . this command will not work unless a stop command is sent down immediately before the scan_in command is issued. 21.13: scan_out this command causes the scan out of the scan chain to be placed on tdo. data is recirculated through the scan chains. tdi is ignored. this command will not work unless a stop command is sent down immediately before the scan_out command is issued. 21.14: private_rw1 this command is used by riscwatch. 21.15: private_rw2 this command is used by riscwatch. 21.16: private_rw3 this command is used by riscwatch. opcode x ? 0900 ? opcode x ? 0a00 ? opcode x'0500' opcode x'0582' opcode x ? 05c0 ?
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint architecture page 525 of 676 sonet framer core (framr chiplet address mapping) gppint architecture overview the general purpose processor interface (gppint) provides direct access to registers located in the gppint module; it provides delayed access to registers and counters located in the gpphandler modules of the various chiplets of the sonet core. gppint controls the handshaking with the external microprocessor as well as the handshaking with the gpphandlers at the asynchronous chiplet interfaces. address decoding is done to the chiplet level in gppint. in addition, addresses are decoded to the register level for the local gppint registers. reset register each chiplet is controlled by one reset bit. at power-on, all reset bits are active and the chiplets are disabled. they can be released by the general purpose processor (gpp) only after all global configuration parameters have been set and the clocks to the chiplets have been established. in addition, there are reset bits for the chiplets that do not have their own gpphandler. interrupt registers the interrupt register is used as a pointer to the chiplet interrupt registers with pending requests: the clock status error register, and the handshaking error register. an active bit of the interrupt register is reset by removing the cause for the request in the corresponding chiplet or by masking the active irq bit(s) in the chiplet; therefore, the interrupt registers (including the pointer) are read only. all interrupt and pointer regis- ters have a corresponding mask register (r/w). every unmasked, active interrupt bit causes an active pointer bit. every unmasked, active pointer bit causes activation of the interrupt signal to the microprocessor. framr chiplet address mapping chiplet name short name chiplet base address chiplet address range number of bytes reserved x ? 000 ? x ? 000 - 0ff ? 256 ach_tx ht x ? 100 ? x ? 100 - 1ff ? 256 ach_rx hr x ? 200 ? x ? 200 - 2ff ? 256 reserved x ? 300 ? x ? 300 - 3ff ? 256 ofp_tx ot x ? 400 ? x ? 400 - 7ff ? 1024 ofp_rx or x ? 800 ? x ? 800 - bff ? 1024 gppint gp x ? c00 ? x ? c00 - cff ? 256 reserved x ? d00 ? x ? d00 - fff ? 768
IBM3206K0424 ibm processor for network resources preliminary gppint architecture page 526 of 676 pnr25.chapt06.01 august 14, 2000 handshaking error registers each bit of the handshaking error registers indicates a locked interface to one of the chiplet gpphandlers. two additional bits indicate various timeout events. to reset an individual bit of the handshaking error regis- ter, the cause for the request must be removed and a one must be written into the bit location of the register (r/w). reading the register will reset the whole (eight-bit) register if the corresponding "clear-register" option is set in the configuration register. the handshaking error indication register has a corresponding mask register (r/w). every unmasked, active handshaking error bit causes activation of the pointer bit in the gppint interrupt register. clock monitor status registers the clock monitor status register bits indicate the loss of a specific chiplet ? s clock. they are set whenever a difference between the clock test signal and the individual chiplet clock acknowledge signal occurs after one clock monitor test period. to reset an individual bit of the clock monitor status registers, the clock of the corre- sponding chiplet must be restored and a one must be written into the bit location of the register (r/w). reading one of the registers will reset the whole (eight-bit) register if the corresponding "clear-register" option is set in the configuration register. the clock monitor status register has a corresponding mask register (r/w). every unmasked, active clock monitor status bit causes activation of the pointer bit in the gppint register. local gppint configuration registers there are registers (r/w) for the clock monitor test period, the watchdog timer period and the "clear-regis- ter" option. a read-only register provides the vital product data (vpd). global static configuration registers these are configuration parameters that are shared by many chiplets or that are needed by chiplets that have no gpphandler. the initial values can be modified by the microprocessor after power-on, but should not be changed later on. all global static configuration registers are r/w. status registers these registers provide status information from chiplets that have no gpphandler and are read only. presently, there is only one status register for the sim chiplet (pll lock status).
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint architecture page 527 of 676 gppint chiplet address mapping overview: base address = x ? c00 ? register name description 1 address offset type initial value resgp1 reset register x ? 00 ? r/w b ? 11111111 ? ... reserved x ? 01 - 0f ? irqgp1 chiplet interrupt request register #1 x ? 10 ? rb ? 00000000 ? ... reserved x ? 11 - 17 ? irmgp1 chiplet interrupt mask register #1 x ? 18 ? r/w b ? 00000000 ? ... reserved x ? 19 - 1f ? hshake1 handshaking error register #1 x ? 20 ? r/w b ? 00000000 ? ... reserved x ? 21 - 27 ? hsmask1 handshaking error mask register #1 x ? 28 ? r/w b ? 00000000 ? ... reserved x ? 29 - 2f ? clkstat1 clock status register #1 x ? 30 ? r/w b ? 00000000 ? ... reserved x ? 31 - 37 ? clkmask1 clock status mask register #1 x ? 38 ? r/w b ? 00000000 ? ... reserved x ? 39 - 47 ? cmongp1 clock monitor test period x ? 48 ? r/w b ? 00000000 ? wdtgp1 watchdog timer period x ? 49 ? r/w b ? 11111111 ? confgp1 "clear-register" option register x ? 4a ? r/w b ? 11111111 ? ... reserved x ? 4b - 4f ? vmd vital macro data register x ? 50 ? rb ? 10000001 ? ... reserved x ? 51 - 57 ? gatmcs common atm/cs static configuration register x ? 58 ? r/w b ? 00000000 ? gcasc common cascading static configuration register x ? 59 ? r/w b ? 10101010 ? glooptx transmit loopback static configuration register x ? 5a ? r/w b ? 00000000 ? glooprx receive loopback static configuration register x ? 5b ? r/w b ? 00000000 ? gextres external clock recovery circuit reset register x ? 5c ? r/w b ? 00000000 ? ... reserved x ? 5d - 67 ? ofptxgp ofp_tx static configuration register x ? 68 ? r/w b ? 00000000 ? ofprxgp1 ofp_rx static configuration register #1 x ? 69 ? r/w b ? 00000000 ? ofprxgp2 ofp_rx static configuration register #2 x ? 6a ? r/w b ? 00000000 ? ... reserved x ? 6b - 71 ? pimrconf2 pim_rx static configuration register #2 x ? 73 ? r/w b ? 00000000 ? ... reserved x ? 74 - 7e ? simstat sim status register x ? 7f ? rn.a. ... reserved x ? 80 - ff ? 1. all registers are of eight-bit width.
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 528 of 676 pnr25.chapt06.01 august 14, 2000 22: gppint register description 22.1: chiplet reset register (resgp) the bits of the chiplet reset register control the resetting (enabling/disabling) of complete chiplets. for each bit position: 0 = reset inactive for this chiplet 1 = reset active (chiplet is disabled; default). length 8 bits type read/write address c00 power on value x ? ff ? resht reshr resot resor txrpis rxrpis reserved 76543210 bit(s) name description 7 resht reset to chiplet ach_tx 6 reshr reset to chiplet ach_rx 5 resot reset to chiplet ofp_tx 4 resor reset to chiplet ofp_rx 3 txrpis reset to chiplet pis_tx 2 rxrpis reset to chiplet pis_rx 1-0 reserved reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 529 of 676 22.2: chiplet interrupt and mask registers (irqgp1 (irmgp1)) the chiplet interrupt request register indicates pending interrupt requests from individual chiplets. an active bit of this register is reset by removing the cause for the request in the corresponding chiplet or by masking the active irq bit(s) in the chiplet; therefore, this register is read only. for each bit position: 0 = no chiplet interrupt request pending. 1 = chiplet has pending interrupt request(s). the chiplet interrupt request mask register bits control the propagation of a chiplet interrupt request to the sonet macro interrupt output pin. the mask registers allow read and write access. for each bit position: 0 = the corresponding interrupt request bit is masked (default). 1 = the corresponding interrupt request bit is active (for irmgp1, the corresponding interrupt request bit activates the sonet macro interrupt). length 8 bits type read address c10 power on value x ? 00 ? irqht irqhr irqot irqor reserved feioccs feiochs 76543210 bit(s) name description 7 irqht irq from ach_tx 6 irqhr irq from ach_rx 5 irqot irq from ofp_tx 4 irqor irq from ofp_rx 3-2 reserved reserved 1 feloccs pending clock status error active 0 felochs pending handshaking error active
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 530 of 676 pnr25.chapt06.01 august 14, 2000 22.3: handshaking error indication and mask registers (hshake1) the local handshaking error indication register indicates pending handshaking error requests from the gppint chiplets. for each bit position: 0 = normal operation of the corresponding chiplet. 1 = the corresponding chiplet did not deassert its dtack signal. exception: the signals toerror and interror (hshake2(1-0)) have the following meaning: normal opera- tion gpp deasserts strobes without waiting for dtack assertion watchdog timeout in rest state watchdog timeout in req state. an active bit of the handshaking error indication register is reset by removing the cause for the malfunctioning of the chiplet and by writing a one into the corresponding bit position. reading one register will reset all bits of this register if the "clear-register" option is set in confgp1(2). the handshaking error indication mask register bits control the propagation of the gppint handshaking error requestof the register hshake1. hsmask1 controls propagation to the signal felochs (bit 0 of irqgp1 register). the mask registers allow read and write access. for each bit position: 0 = the corresponding handshaking error indication bit is masked (default). 1 = the corresponding request bit is active (for hsmask1, the corresponding request bit activates signal felochs (bit 0 of irqgp1 register). "clear-register" option set in confgp1(2). length 8 bits type read/write address c20 power on value x ? 00 ? dtack from ach_tx dtack from ach_rx dtack from ofp_tx dtack from ofp_rx reserved toerror interror 76543210 bit(s) name description 7 dtack from ach_tx stuck at one 6 dtack from ach_rx stuck at one 5 dtack from ofp_tx stuck at one 4 dtack from ofp_rx stuck at one 3-2 reserved reserved 1 toerror time out error of the gpp interface (see above) 0 interror gpp interface error (see above)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 531 of 676 22.4: clock monitor status and mask registers (clkstat1 (clkmask1)) the clock monitor status register bits indicate the loss of a specific island ? s clock. they are set whenever a difference between the clock test signal and the individual island ? s clock acknowledge signal occurs after the clock monitor test period. for each bit position: 0 = normal operation of the corresponding clock island 1 = the corresponding island clock is lost. an active bit of this register is reset by restoring the clock of the corresponding clock island and by writing a one into the corresponding bit position. reading one reg- ister will reset all bits of this register if the "clear-register" option is set in bit confgp1(3). the clock moni- tor mask register clkmask1 controls the propagation of active clock monitor status signals. clkmask1 controls propagation to the signal feloccs (bit 1 of irqgp1 register). the mask registers allow read and write access. for each bit position: 0 = the corresponding clock status bit is masked (default). 1 = the corresponding clock status bit is active (for clkmask1, the corresponding bit activates the signal feloccs (bit 1 of irqgp1 register). length 8 bits type read/write address c30 power on value x ? 00 ? island ach_tx island ach_rx island ofp_tx island ofp_rx reserved 76543210 bit(s) description 7 island ach_tx lost clock 6 island ach_rx lost clock 5 island ofp_tx lost clock 4 island ofp_rx lost clock 3-0 reserved
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 532 of 676 pnr25.chapt06.01 august 14, 2000 22.5: clock monitor test period register (cmongp1) divider ratio to derive the clock monitor test period from the gppclk clock. clock monitoring is disabled if equal x ? 00 ? (default). 22.6: watchdog timer period register (wdtgp1) divider ratio to derive the interface timeout period from the gppclk clock. this register is reset to x ? ff ? whenever a timeout occurs; it has to be reconfigured by a gpp write access. length 8 bits type read/write address c48 power on value x ? 00 ? cmongp1 76543210 bit(s) name description 7-0 cmongp1(7-0) number of gppclk cycles/test period length 8 bits type read/write address c49 power on value x ? ff ? wdtgp1 76543210 bit(s) name description 7-0 wdtgp1(7-0) number of gppclk clock cycles per timeout period
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 533 of 676 22.7: gppint local configuration registers (confgp1) the bits of this local configuration register control the resetting of complete registers upon read access ("clear register" option). for each bit position: 0 = no action upon read access. 1 = the corresponding register is reset upon read access (default). length 8 bits type read/write address c4a power on value x ? ff ? reserved clkstat1 & clkstat2 hshake1 & hshake2 simstat reserved 76543210 bit(s) description 7-4 reserved 3 clear-bit for registers clkstat1 & clkstat2 2 clear-bit for registers hshake1 & hshake2 1 clear-bit for register simstat 0 reserved
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 534 of 676 pnr25.chapt06.01 august 14, 2000 22.8: vital macro data register (vpd) this read-only register displays the macro identification. 22.9: static configuration register (gatmcs) common static configuration data, providing control signals that are distributed to multiple chiplets. set once by the gpp before the individual chiplets get enabled and not changing during normal operation. length 8 bits type read address c50 power on value x ? 01 ? macro type version number 76543210 bit(s) description 7-5 macro type (000) 4-0 version number length 8 bits type read/write address c58 power on value x ? 00 ? reserved gatmcsrx reserved gatmcstx 76543210 bit(s) name description 7-5 reserved reserved 4 gatmcsrx atm cell or cs mode for sdh macro in receive direction: 0 = sdh macro in atm mode 1 = sdh macro in cs mode 3-1 reserved reserved 0 gatmcstx atm cell or cs mode for sdh macro in transmit direction: 0 = sdh macro in atm mode, 1 = sdh macro in cs mode
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 535 of 676 22.10: gcasc 22.11: glooptx transmit loopback control. for each bit position: 0 = ach loopback disabled (default). 1 = ach loopback enabled. length 8 bits type read/write address c59 power on value x ? 88 ? gcascrx gcasctx 76543210 bit(s) name description 7-4 gcascrx(7-4) defines sdh macros in receive direction: 0001 sts3c 1000 stm1 others reserved 3-0 gcasctx(7-4) defines sdh macros in transmit direction: 0001 sts3c 1000 stm1 others reserved length 8 bits type read/write address c5a power on value x ? 00 ? reserved txlpb2 reserved txlpb1 76543210 bit(s) name description 7-5 reserved reserved 4 txlpb2 loopback #2 control, tx macro 3-1 reserved reserved 0 txlpb1 loopback #1 control, tx macro
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 536 of 676 pnr25.chapt06.01 august 14, 2000 22.12: glooprx receive loopback control. for each bit position: 0 = ach loopback disabled (default). 1 = ach loopback enabled. 22.13: gextres external clock recovery circuit reset signal. delivered to external circuit (deserializer) via device pins. the active level depends on the external circuit used. default value at power-on-reset is low. length 8 bits type read/write address c5b power on value x ? 00 ? reserved rxlpb2 76543210 bit(s) name description 7-1 reserved reserved 0 rxlpb2 loopback #2 control, rx macro length 8 bits type read/write address c5c power on value x ? 00 ? reserved rstcrec 76543210 bit(s) name description 7-1 reserved reserved 0 rstcrec external recovery reset
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 537 of 676 22.14: ofptxgp static configuration data, providing control signals for chiplet ofp_tx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. 22.15: ofprxgp1 length 8 bits type read/write address c68 power on value x ? 00 ? reserved ptrproc reserved cdhc1tx 76543210 bit(s) name description 7-5 reserved reserved 4 ptrproc 0 = au pointer processing disabled in atm mode 1 = au pointer processing enabled in atm mode 3-1 reserved reserved 0 sdhc1tx 0 = c1 byte replaced by section trace j1 byte (itu-t standard) 1 = old numbering scheme is used. ofprxgp1 & 2: static configuration data, providing control signals for chiplets ofp_rx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. length 8 bits type read/write address c69 power on value x ? 00 ? reserved sdhc1rx 76543210 bit(s) name description 7-1 reserved reserved 0 sdhc1rx 0 = the new (itu-t standard) numbering scheme is used 1 = old numbering scheme is used
IBM3206K0424 ibm processor for network resources preliminary gppint register description page 538 of 676 pnr25.chapt06.01 august 14, 2000 22.16: ofprxgp2 22.17: pimrconf2 static configuration data, providing control signals for chiplets pim_tx/pim_rx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. length 8 bits type read/write address c6a power on value x ? 00 ? reserved a2frm 76543210 bit(s) name description 7-2 reserved reserved 1-0 a2frm ofp_rx rxsofrm assertion controls: 00 rxsofrm asserted during 3rd a2 byte 01 rxsofrm asserted during 1st a2 byte 10 rxsofrm asserted during 2nd a2 byte 11 rxsofrm asserted during 3rd a2 byte length 8 bits type read/write address c73 power on value x ? 00 ? reserved algo1 76543210 bit(s) name description 7-2 reserved reserved 1-0 algo1(7-6) selects frame pattern recognition algorithm: 00 all bits checked; maximum four bad frames 01 12 bits checked; only maximum four bad frames 10 all bits checked; maximum five bad frames 11 12 bits checked only; maximum five bad frames
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gppint register description page 539 of 676 22.18: simstat status register, providing the gpp with information from the sim chiplet via pim. either sim-internal or exter- nal pll lock status. "clear-register" option set in confgp1(1). length 8 bits type read address c7f power on value n/a reserved rx_lock 76543210 bit(s) name description 7-1 reserved reserved 0 rx_lock 0 rx pll is still in phase aquisition process 1 rx pll is enabled and has locked to the incoming data stream incoming data stream
IBM3206K0424 ibm processor for network resources preliminary gpphandler architecture page 540 of 676 pnr25.chapt06.01 august 14, 2000 23: gpphandler architecture overview all gpp handlers for the various chiplets have the following general register structure. counter registers every counter has an enable bit in the counter enable register (addr 2 or 3), and optionally up to two program- mable thresholds. each counter has an interrupt bit for overflow and up to two interrupt bits for threshold crossing in the counter interrupt registers. for all counters in one handler there is one common ? read-on-the-fly register ? that is used to store the higher order bytes to obtain a correct readback value for counters larger than eight bits. counters are read-only registers; the count enable registers are read/write. note: counter reading is independent of the counter length, given that a counter has address n as base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no influence on the counter, but reading address n-1 will reset the counter after the read. reading address n or n-1 will always latch the higher order bytes into the read on the fly register (before the optional automatic reset). counters can only be read and not written to. for a 16-bit counter, the most significant byte should be read from rofmid (address 0). for a 24-bit counter, the most significant byte is read from rofhi (address 1), the next byte from rofmid (address 0). to completely read a 24-bit counter: first read least significant byte from counter address n or n-1, then read rofmid and rofhi (address 0; address 1). reset registers each handler has a two-bit reset register. bit 0 is the chiplet reset control. this bit is active high after power on reset, causing the chiplet to be disabled. bit 1 is the chiplet halt signal, which for selected chiplets freezes the state machines for diagnostic purposes. this is a read/write register. command registers the optional command register(s) will generate events to the chiplet. when a bit is written high by the micro- processor, it will remain high for one chiplet clock cycle. therefore, reading back a command register w ill always read back zeroes. this is a read/write register. gpphandler architecture address range register function x ? 0 - 1 ? read on the fly registers x ? 2 - 3 ? counter enable registers x ? 4 - 2f ? counters and counter threshold registers x ? 30 ? reset register x ? 31 - 32 ? command registers x ? 33 - 37 ? event latch registers (was called status) x ? 38 - 47 ? interrupt registers (addr=int reg, addr-1=int mask reg) x ? 48 - 57 ? configuration registers
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 gpphandler architecture page 541 of 676 event latch registers the optional event latch register(s) remember one ore more occurances of events that happen in a chiplet. this may be considered as a one-bit saturating counter. each bit in the register corresponds to an event in the chiplet. such bits remain high after the event happened until the microprocessor implicitly or explicitly resets the bit. this is configurable: implicit reset is done by writing a high value to the bit that is to be reset. explicit will reset all bits of one register when the register is read. this is a read/write register. interrupt registers when there are counters, user interrupts, or fatal bits in a chiplet, a main interrupt register will be present. bit 0 always is the fatal interrupt bit, which is set as soon as any of the fatal interrupt events occur. the other bits refer to counters or user interrupt registers to allow easy determination of the interrupt cause. each interrupt register has an interrupt mask register to enable or disable interrupt. after power on reset, interrupts are disabled. the interrupt registers are the same as the event latch registers, with the addition that when an interrupt register bit is set, and the corresponding mask register bit is set, the interrupt signal to the gppint chiplet is activated. the same mechanism to reset the interrupt register bits is used as for the event latch registers. the interrupt mask registers are only chan ged by the microprocessor. the interrupt and interrupt mask registers are read/write. configuration registers these registers are programmed by the microprocessor with setup information, and are read/write. the first configuration register reserves bit 1 and seven to configure explicit or implicit reset of the event latch registers and interrupt registers respectively (when such registers are present). register types f read-on-the-fly register (auto-generated) n counter register r reset register i interrupt register (auto-generated) c configuration register x control or mask register (auto-generated) s status (event latch) register o command register
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture : transmit direction page 542 of 676 pnr25.chapt06.01 august 14, 2000 atm cell handler architecture : transmit direction ach_tx gpp handler address mapping base address = x ? 100 ? register name description address offset type width initial value rofmid read-on-the-fly register x ? 0 ? f 8 ? 00000000 ? rofhi read-on-the-fly register (msbyte) x ? 1 ? f 8 ? 00000000 ? cnten1 count enable register x ? 2 ? x 3 ? 000 ? acbc cell counter (read from external fifo), no threshold 2 x ? 4/5 ? 2 n 24 ? x ? 000000 ?? iuc idle/unassigned cell counter, no threshold 2 x ? 6/7 ? 2 n 24 ? x ? 000000 ?? acbe corrupted cell error counter 2 x ? 8/9 ? 2 n 8 ? 00000000 ? acbeth11 threshold register for counter acbe x ? a ? x 8 ? 10000000 ? reset default reset register x ? 30 ? r 2 ? 01 ? stat1 status register #1 x ? 33 ? s 8 iucstat1 status register #2 x ? 34 ? s 2 mainirq main interrupt register x ? 38 ? i 2 m_mainirq int mask register (for mainirq) x ? 39 ? x 2 ? 00 ? cntrirq1 counter interrupt register x ? 3a ? i 4 m_cntrirq1 int mask register (for cntrirq1) x ? 3b ? x 4 ? 0000 ? celltenable chiplet cofiguration register x ? 48 ? c 6 ? 001111 ? acbtxthrpae programmable almost empty threshold x ? 49 ? c 7 ? 0001110 ? headerbyte1 iu-cell header byte 1 1 x ? 4a ? c 8 ? 00000000 ? headerbyte2 iu-cell header byte 2 1 x ? 4b ? c 8 ? 00000000 ? headerbyte3 iu-cell header byte 3 1 x ? 4c ? c 8 ? 00000000 ? headerbyte4 iu-cell header byte 4 1 x ? 4d ? c 8 ? 00000001 ? headerbyte5 iu-cell header byte 5 1 x ? 4e ? c 8 ? 01010010 ? payloadbyte iu-cell payload byte x ? 4f ? c 8 ? 01101010 ? hecenctrl hec processing control x ? 50 ? c 7 ? 0001100 ? hecoffset hec offset pattern register x ? 51 ? c 8 ? 01010101 ? hecmaskand hec error corruption mask (and) x ? 52 ? c 8 ? 11111111 ? hecmaskor hec error corruption mask (or) x ? 53 ? c 8 ? 00000000 ? sdbtxthrpaf programmable almost full threshold x ? 54 ? c 6 ? 110000 ? 1. defaults according itu i.432 2. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 543 of 676 24: ach tx register description counter registers 24.1: rofmid read-on-the-fly register, middle significant byte. 24.2: rofhi read-on-the-fly register, most significant byte. length 8 bits type read address 100 power on value x ? 00 ? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register, middle significant byte length 8 bits type read address 101 power on value x ? 00 ? rofhi 76543210 bit(s) name description 7-0 rofhi(7-0) read-on-the-fly register, most significant byte
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 544 of 676 pnr25.chapt06.01 august 14, 2000 24.3: acbc number of cells read from external fifo (24-bit counter). overflow leads to an interrupt request. 24.4: iuc number of transmitted idle and unassigned cells (24-bit counter). overflow leads to an interrupt request. length 8 bits type read address 104/105 power on value x ? 00 ? acbc(16:23) 76543210 bit(s) name description 7-0 acbc(16:23) external fifo cell counter, least significant byte length 8 bits type read address 106/107 power on value x ? 00 ? iuc(16:23) 76543210 bit(s) name description 7-0 iuc(16:23) idle/unassigned cell counter, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 545 of 676 24.5: acbe number of errors (corrupted cell read from external fifo). eight-bit counter overflow leads to an interrupt request. length 8 bits type read address 108/109 power on value x ? 00 ? acbe 76543210 bit(s) name description 7-0 acbe(7-0) external fifo error counter
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 546 of 676 pnr25.chapt06.01 august 14, 2000 24.6: acbeth11 threshold for number of errors. threshold overstep leads to an interrupt request. 24.7: cnten1 counter on/off control register for ach_tx. for each bit position: 0 = counter is disabled. 1 = counter is enabled. length 8 bits type read/write address 10a power on value x ? 80 ? acbeth11 76543210 bit(s) name description 7-0 acbeth11(7-0) threshold for error counter length 8 bits type read/write address 102 power on value x ? 00 ? reserved en-acbe en-icu en-acbc 76543210 bit(s) name description 7-3 reserved reserved 2 en-acbe error counter enable 1 en-iuc idle/unassigned cell counter enable 0 en-acbc cell counter enable
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 547 of 676 24.8: reset register (reset) reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal resht from the gppint. for each bit position: 0 = reset/halt not active. 1 = reset/halt active. length 8 bits type read/write address 130 power on value x ? 01 ? reserved halt ach_tx reset ach_tx 76543210 bit(s) description 7-2 reserved 1 halt (freeze) ach_tx chiplet 0 reset (disable) ach_tx chiplet
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 548 of 676 pnr25.chapt06.01 august 14, 2000 status registers 24.9: stat1 status register #1 of this chiplet. this is an event latch register. length 8 bits type read/write address 133 power on value - rxlpb2fe txlpb2fe txlpb1fe cellgenstatus sdbtxpaf sdbtxff acbtxpae acbtxef 76543210 bit(s) name description 7 rxlpb2fe rx loopback #2 configuration mismatch 6 txlpb2fe tx loopback #2 configuration mismatch 5 txlpb1fe tx loopback #1 configuration mismatch 4 cellgenstatus 0 = idle/unassigned cell is transmitted 1 = cell from external fifo is transmitted 3 sdbtxpaf programmable almost full flag from sdb_tx 2 sdbtxff fifo full flag from sdb_tx 1 acbtxpae programmable almost empty flag from external transmit fifo 0 acbtxef fifo empty flag from external transmit fifo
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 549 of 676 24.10: iucstat1 status register #2 of this chiplet. this is an event latch register. interrupt request and mask registers 24.11: mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position; 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 134 power on value - reserved iucferr 76543210 bit(s) name description 7-1 reserved reserved 0 iucferr unexpected state transition in fsm length 8 bits type read/write address 138 power on value - reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 550 of 676 pnr25.chapt06.01 august 14, 2000 24.12: m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates signal irqht1 to gppint. length 8 bits type read/write address 139 power on value x ? 00 ? reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 551 of 676 24.13: cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 13a power on value - reserved th-acbe ov-acbe ov-iuc ov-acbc 76543210 bit(s) name description 7-4 reserved reserved 3 th-acbe threshold overstep error counter 2 ov-acbe overflow error counter 1 ov-iuc overflow idle/unassigned cell counter 0 ov-acbc overflow cell counter
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 552 of 676 pnr25.chapt06.01 august 14, 2000 24.14: m_cntrirq1 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 13b power on value x ? 00 ? reserved th-acbe ov-acbe ov-iuc ov-acbc 76543210 bit(s) name description 7-4 reserved reserved 3 th-acbe threshold overstep error counter 2 ov-acbe overflow error counter 1 ov-iuc overflow idle/unassigned cell counter 0 ov-acbc overflow cell counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 553 of 676 configuration registers 24.15: celltenable register to control various modes of operation of this chiplet. length 8 bits type read/write address 148 power on value x ? 0f ? reserved txlpb1only txlpb2only iucenable acbenable autrst_sta autrst_int 76543210 bit(s) name description 7-6 reserved reserved 5 txlpb1only 0 = on the fly monitoring (lpb #1) 1 = loopback #1 only 4 txlpb2only 0 = on the fly monitoring (lpb #2) 1 = loopback #2 only 3 iucenable 0 = generation of iuc disabled 1 = generation of iuc enabled 2 acbenable 0 = external fifo read disabled 1 = external fifo read enabled 1autrst_sta 0 = no action on read access 1 = auto-reset status registers upon read access 0autrst_int 0 = no action on read access 1 = auto-reset interrupt request registers upon read access
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 554 of 676 pnr25.chapt06.01 august 14, 2000 24.16: acbtxthrpae threshold for programmable almost empty flag of external fifo in transmit direction. 24.17: sdbtxthrpaf threshold for programmable almost full flag (sdb_tx). length 8 bits type read/write address 149 power on value x ? 0e ? reserved acbtxthrpae 76543210 bit(s) name description 7 reserved reserved 6-0 acbtxthrpae(7-1) threshold for pae flag length 8 bits type read/write address 154 power on value x ? 30 ? reserved sdbtxthrpaf 76543210 bit(s) name description 7-6 reserved reserved 5-0 sdbtxthrpaf(7-2) threshold for paf flag
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 555 of 676 24.18: headerbyte1 idle/unassigned cell header byte #1. default pattern according to itu i.432. 24.19: headerbyte2 idle/unassigned cell header byte #2. default pattern according to itu i.432. length 8 bits type read/write address 14a power on value x ? 00 ? headerbyte1 76543210 bit(s) name description 7-0 headerbyte1(7-0) iu-cell header byte #1 length 8 bits type read/write address 14b power on value x ? 00 ? headerbyte2 76543210 bit(s) name description 7-0 headerbyte2(7-0) iu-cell header byte #2
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 556 of 676 pnr25.chapt06.01 august 14, 2000 24.20: headerbyte3 idle/unassigned cell header byte #3. default pattern according to itu i.432. 24.21: headerbyte4 idle/unassigned cell header byte #4. default pattern according to itu i.432. length 8 bits type read/write address 14c power on value x ? 00 ? headerbyte3 76543210 bit(s) name description 7-0 headerbyte3(7-0) iu-cell header byte #3 length 8 bits type read/write address 14d power on value x ? 01 ? headerbyte4 76543210 bit(s) name description 7-0 headerbyte4(7-0) iu-cell header byte #4
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 557 of 676 24.22: headerbyte5 idle/unassigned cell header byte #5. default pattern according to itu i.432. 24.23: payloadbyte idle/unassigned cell payload byte. length 8 bits type read/write address 14e power on value x ? 52 ? headerbyte5 76543210 bit(s) name description 7-0 headerbyte5(7-0) iu-cell header byte #5 length 8 bits type read/write address 14f power on value x ? 6a ? payloadbyte 76543210 bit(s) name description 7-0 payloadbyte(7-0) iu-cell payload byte
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 558 of 676 pnr25.chapt06.01 august 14, 2000 24.24: hecenctrl hec processing control configuration register. length 8 bits type read/write address 150 power on value x ? 0c ? reserved payload byte control screnable hecenable heccntludf2 76543210 bit(s) name description 7reserved 6-4 payload byte control 000 each payload byte is the same (default) 001 increment payload byte for each atm cell, start with default after reset 010 increment each payload byte of a cell; start each cell with default byte 011 increment each pl byte of a cell; cross cell boundaries; start first cell after reset with default byte 1xx each payload byte is the same 3 screnable 0 = atm cell payload scrambling disabled 1 = atm cell payload scrambling enabled 2 hecenable 0 = hec calculation/manipulation disabled 1 = hec calculation/manipulation enabled 1-0 heccntludf2 mode of final hec manipulation by udf1 byte after hecoffset, hecmaskand, hecmaskor operations: 00 no manipulation 01 hec xor udf1 10 hec and udf1 11 hec or udf1
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 ach tx register description page 559 of 676 24.25: hecoffset hec offset pattern register for the byte pattern used in the atm cell header hec calculation as base offset according to itu i.432. 24.26: hecmaskand hec mask pattern register for the byte pattern used in the atm cell header hec calculation as dedicated (anding) hec error corruption mask. length 8 bits type read/write address 151 power on value x ? 55 ? hecoffset 76543210 bit(s) name description 7-0 hecoffset(7-0) hec offset pattern length 8 bits type read/write address 152 power on value x ? ff ? hecmaskand 76543210 bit(s) name description 7-0 hecmaskand(7-0) hec error corruption mask (and)
IBM3206K0424 ibm processor for network resources preliminary ach tx register description page 560 of 676 pnr25.chapt06.01 august 14, 2000 24.27: hecmaskor hec mask pattern register for the byte pattern used in the atm cell header hec calculation as dedicated (oring) hec error corruption mask. length 8 bits type read/write address 153 power on value x ? 00 ? hecmaskor 76543210 bit(s) name description 7-0 hecmaskor(7-0) hec error corruption mask (or)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 561 of 676 atm cell handler architecture: receive direction ach_rx gpp handler address mapping base address = x ? 200 ? register name description address offset type width initial value rofmid read-on-the-fly register x ? 0 ? f 8 ? 00000000 ? rofhi read-on-the-fly register (msbyte) x ? 1 ? f 8 ? 00000000 ? cnten1 count enable register x ? 2 ? x 4 ? 0000 ? fhr counter, atm cells written into external fifo, no threshold x ? 4/5 ? 1 n 24 ? x ? 000000 ?? ihr counter, received idle cells from ofp, no threshold x ? 6/7 ? 1 n 24 ? x ? 000000 ?? ehr1 counter, detected hec errors with threshold x ? 8/9 ? 1 n 16 ? x ? 0000 ?? ehr1th12 threshold reg byte2 (lsbyte) for counter ehr1 x ? a ? x 8 ? 00000001 ? ehr1th11 threshold reg byte1 for counter ehr1 x ? b ? x 8 ? 10000000 ? bhr counter, fifo full discarded cells: (discpaf1=1) and (txlpb11=0) with threshold. 1 x ? c/d ? 1 n 16 ? x ? 0000 ?? bhrth12 threshold reg byte2 (lsbyte) for counter bhr x ? e ? x 8 ? 00000001 ? bhrth11 threshold register byte1 for counter bhr x ? f ? x 8 ? 10000000 ? reset default reset register x ? 30 ? r 2 ? 01 ? cmd1 command register (fifo reset) x ? 31 ? o 2 ? 00 ? stat1 status register x ? 33 ? s 6 mainirq main interrupt register x ? 38 ? i 2 m_mainirq interrupt mask register (for mainirq) x ? 39 ? x 2 ? 00 ? cntrirq1 counter interrupt register x ? 3a ? i 6 m_cntrirq1 interrupt mask register (for cntrirq1) x ? 3b ? x 6 ? 000000 ? conf5 chiplet configuration register x ? 48 ? c 8 ? 00000011 ? conf6 chiplet configuration register (alpha/delta) x ? 49 ? c 8 ? 01100101 ? h1conf confirmation bytes to identify idle or unassigned cells. x ? 4a ? c 8 ? 00000000 ? h2conf confirmation bytes to identify idle or unassigned cells. x ? 4b ? c 8 ? 00000000 ? h3conf confirmation bytes to identify idle or unassigned cells. x ? 4c ? c 8 ? 00000000 ? h4conf confirmation bytes to identify idle or unassigned cells. x ? 4d ? c 8 ? 00000001 ? h5conf dummy byte to align payload in external fifo x ? 4e ? c 8 ? 11010000 ? confc external fifo buffer almost full threshold x ? 4f ? c 7 ? 1100000 ? 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation.
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 562 of 676 pnr25.chapt06.01 august 14, 2000 ach_rx register description counter registers 24.28: rofmid read-on-the-fly registers, middle significant byte. 24.29: rofhi read-on-the-fly registers, most significant byte. length 8 bits type read address 200 power on value x ? 00 ? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register, middle significant byte length 8 bits type read address 201 power on value x ? 00 ? rofhi 76543210 bit(s) name description 7-0 rofhi(7-0) read-on-the-fly register, most significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 563 of 676 24.30: fhr number of atm cells written into external fifo (24-bit counter). overflow leads to an interrupt request. 24.31: ihr number of idle cells received from ofp_rx (24-bit counter). overflow leads to an interrupt request. length 8 bits type read address 204/205 power on value x ? 00 ? fhr (16:23) 76543210 bit(s) name description 7-0 fhr(16:23) atm cell counter, least significant byte length 8 bits type read address 206/207 power on value x ? 00 ? ihr (16:23) 76543210 bit(s) name description 7-0 ihr(16:23) idle/unassigned cell counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 564 of 676 pnr25.chapt06.01 august 14, 2000 24.32: ehr1 number of detected hec errors (16-bit counter). overflow leads to an interrupt request. 24.33: ehr1th11 threshold for number of hec cells, most significant byte. length 8 bits type read address 208/209 power on value x ? 00 ? ehr1 (8:15) 76543210 bit(s) name description 7-0 ehr1(8:15) hec error counter, least significant byte length 8 bits type read/write address 20b power on value x ? 80 ? ehr1th11 76543210 bit(s) name description 7-0 ehr1th11(7-0) threshold for hec error counter, most significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 565 of 676 24.34: eht1th12 threshold for number of hec errors (least significant byte). threshold overstep leads to an interrupt request. 24.35: bhr number of discarded cells because of fifo full condition (16 bit counter). overflow leads to an interrupt request. length 8 bits type read/write address 207 power on value x ? 01 ? ehr1th12 76543210 bit(s) name description 7-0 ehr1th12(7-0) threshold for hec error counter, least significant byte length 8 bits type read address 20c/20d power on value x ? 00 ? bhr (8:15) 76543210 bit(s) name description 7-0 bhr(8:15) discarded cell counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 566 of 676 pnr25.chapt06.01 august 14, 2000 24.36: bhrth11 threshold for number of discarded cells, most significant byte. 24.37: bhrth12 threshold for number of discarded cells (least significant byte). threshold overstep leads to an interrupt request. length 8 bits type read/write address 20f power on value x ? 80 ? bhrth11 76543210 bit(s) name description 7-0 bhrth11(7-0) threshold for discarded cell counter, most significant byte length 8 bits type read/write address 20e power on value x ? 01 ? bhrth12 76543210 bit(s) name description 7-0 bhrth12(7-0) threshold for discarded cell counter, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 567 of 676 24.38: cnten1 counter on/off control register for ach_rx. for each bit position: 0 = counter is disabled. 1 = counter is enabled. length 8 bits type read/write address 202 power on value x ? 00 ? reserved en-bhr en-ehr1 en-ihr en-fhr 76543210 bit(s) name description 7-4 reserved reserved 3 en-bhr discarded cell counter enable 2 en-ehr1 hec error counter enable 1 en-ihr idle cell counter enable 0 en-fhr atm cell counter enable
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 568 of 676 pnr25.chapt06.01 august 14, 2000 24.39: reset register (reset) reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal reshr from the gppint. for each bit position: 0 = reset/halt not active. 1 = reset/halt active. 24.40: command register (cmd1) command register for this chiplet. single-cycle active if ? 1 ? is written into bit position. length 8 bits type read/write address 230 power on value x ? 01 ? reserved halt ach_rx reset ach_rx 76543210 bit(s) description 7-2 reserved 1 halt (freeze) ach_rx chiplet 0 reset (disable) ach_rx chiplet length 8 bits type read/write address 231 power on value x ? 00 ? reserved acbfifo sdbfifo 76543210 bit(s) name description 7-2 reserved reserved 1 acbfifo reset external fifo 0 sdbfifo reset sdb_rx fifo
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 569 of 676 24.41: status register (stat1) status register of this chiplet. this is an event latch register. length 8 bits type read/write address 233 power on value - reserved celldelo rdflagef wrflagpaf wrflagff 76543210 bit(s) name description 7-6 reserved reserved 5-3 celldelo state of the cell delineation process : 000 reset state 001 hunt state 010 presync state 100 sync state 2 rdflagef sdb fifo: read fifo empty flag 1 wrflagpaf external fifo: write fifo programmable almost full flag 0 wrflagff external fifo: write fifo full flag
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 570 of 676 pnr25.chapt06.01 august 14, 2000 interrupt request and mask registers 24.42: mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 238 power on value - reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 571 of 676 24.43: m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates signal irqhr1 to gppint. length 8 bits type read/write address 239 power on value x ? 00 ? reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 572 of 676 pnr25.chapt06.01 august 14, 2000 24.44: cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 240 power on value - reserved th-bhr ov-bhr th-ehr1 ov-ehr1 ov-ihr ov-fhr 76543210 bit(s) name description 7-6 reserved reserved 5 th-bhr threshold overstep discarded cell counter 4 ov-bhr overflow discarded cell counter 3 th-ehr1 threshold overstep hec error counter 2 ov-ehr1 overflow hec error counter 1 ov-ihr overflow idle cell counter 0 ov-fhr overflow atm cell counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 573 of 676 24.45: m_cntrirq1 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 241 power on value x ? 00 ? reserved th-bhr ov-bhr th-ehr1 ov-ehr1 ov-ihr ov-fhr 76543210 bit(s) name description 7-6 reserved reserved 5 th-bhr threshold overstep discarded cell counter 4 ov-bhr overflow discarded cell counter 3 th-ehr1 threshold overstep hec error counter 2 ov-ehr1 overflow hec error counter 1 ov-ihr overflow idle cell counter 0 ov-fhr overflow atm cell counter
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 574 of 676 pnr25.chapt06.01 august 14, 2000 configuration registers 24.46: conf5 register to control various modes of operation of this chiplet. length 8 bits type read/write address 248 power on value x ? 03 ? detstrtoc nwrtofifo notdethecer wrtchece ndescramb wridlec autrst_sta autrst_int 76543210 bit(s) name description 7detstrtoc 0 do not detect start of cell 1 detect start of cell 6 nwrtofifo 0 write into acb fifo 1 do not write into acb fifo; all received cells are discarded 5 notdethecer 0 detect atm cell with hec errors 1 do not detect atm cell with hec errors 4 wrtchece 0 do not write atm cell with hec errors 1 write atm cell with hec errors 3ndescramb 0 descramble atm cell payload 1 do not descramble atm cell payload 2 wridlec 0 do not write idle cell into external fifo 1 write idle cell into acb fifo 1autrst_sta 0 no action on read access 1 auto-reset status register upon read access 0autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 575 of 676 24.47: conf6 register to control atm cell synchronization in this chiplet. 24.48: confc threshold for programmable almost full flag of the external fifo. length 8 bits type read/write address 249 power on value x ? 65 ? alpha delta 76543210 bit(s) name description 7-4 alpha(7-4) required number of consecutive false hec detected to return from sync to hunt state 3-0 delta(7-4) required number of consecutive good hec detected to jump from presync to sync state length 8 bits type read/write address 24f power on value x ? 60 ? reserved confc (7-1) 76543210 bit(s) name description 7 reserved reserved 6-0 confc(7-1) threshold for paf flag headerbyte1/2/3/4/5: idle/unassigned cell header bytes, default pat- tern according to itu i.432.
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 576 of 676 pnr25.chapt06.01 august 14, 2000 24.49: h1conf header pattern #1 to identify idle/unassigned cells. 24.50: h2conf header pattern #2 to identify idle/unassigned cells. length 8 bits type read/write address 24a power on value x ? 00 ? h1conf 76543210 bit(s) name description 7-0 h1conf(7-0) header byte #1 length 8 bits type read/write address 24b power on value x ? 00 ? h2conf 76543210 bit(s) name description 7-0 h2conf(7-0) header byte #2
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 atm cell handler architecture: receive direction page 577 of 676 24.51: h3conf header pattern #3 to identify idle/unassigned cells. 24.52: h4conf header pattern #4 to identify idle/unassigned cells. length 8 bits type read/write address 24c power on value x ? 00 ? h3conf 76543210 bit(s) name description 7-0 h3conf(7-0) header byte #3 length 8 bits type read/write address 24d power on value x ? 01 ? h4conf 76543210 bit(s) name description 7-0 h4conf(7-0) header byte #4
IBM3206K0424 ibm processor for network resources preliminary atm cell handler architecture: receive direction page 578 of 676 pnr25.chapt06.01 august 14, 2000 24.53: h5conf dummy byte to align the payload in the acb_rx buffer. length 8 bits type read/write address 24e power on value x ? d0 ? h5conf 76543210 bit(s) name description 7-0 h5conf(7-0) payload alignment byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 579 of 676 overhead frame processor architecture: transmit direction ofp_tx gpp handler address mapping base address = x ? 400 ? (page 1 of 3) register name description address offset type width initial value cnten1 count enable register x ? 2 ? x 4 ? 0000 ? ptrinc pointer increment event counter 1 x ? 4/5 ? 1 n 8 ? 00000000 ? no threshold n 8 ptrdec pointer decrement event counter 1 x ? 6/7 ? 1 n 8 ? 00000000 ? no threshold n 8 nd_evcnt new data event counter, no threshold 1 x ? 8/9 ? 1 n 8 ? 00000000 ? juscnt justification error counter 1 x ? a/b ? 1 n 8 ? 00000000 ? with no threshold n 8 juscntth11 threshold register for counter juscnt x ? c ? x 8 ? 10000000 ? reset default reset register x ? 30 ? r 2 ? 01 ? cmd1 njus, pjus, ndf x ? 31 ? o 3 ? 000 ? stat1 init, hug, mode(7-5) x ? 33 ? s 6 stat2 njus, pjus, ndf x ? 34 ? s 3 mainirq main interrupt register x ? 38 ? i 3 m_mainirq interrupt mask register (for mainirq) x ? 39 ? x 3 ? 000 ? cntrirq1 counter interrupt register x ? 3a ? i 5 m_cntrirq1 interrupt mask register (for cntrirq1) x ? 3b ? x 5 ? 00000 ? irq3 user interrupt register x ? 3c ? i 6 m_irq3 interrupt mask register (for irq3) x ? 3d ? x 6 ? 000000 ? conf1 configuration register #1 (general a) x ? 48 ? c 8 ? 00000011 ? conf2 configuration register #2 (general b) x ? 49 ? c 3 ? 000 ? conf3 configuration register #3 x ? 4a ? c 8 ? 11111110 ? (fscr reload pattern) n 8 conf4 configuration register #4 (errmask) x ? 4b ? c 8 ? 00000000 ? conf5 configuration register #5 (erraddress) x ? 4c ? c 8 ? 00000000 ? conf6 configuration register #6 (fscr control) x ? 4d ? c 8 ? 00000001 ? conf7 configuration register #7 (dcc control) x ? 4e ? c 4 ? 0000 ? conf8 configuration register #8 (thrlow) x ? 4f ? c 6 ? 000011 ? conf9 configuration register #9 (thrnow) x ? 50 ? c 6 ? 010001 ? conf10 configuration register #10 (thrhiw) x ? 51 ? c 6 ? 100000 ? soh-a11 first a1 x ? 100 ? 8 soh-a12 second1 a1 x ? 101 ? 8 soh-a13 third a1 x ? 102 ? 8 soh-a21 first a2 x ? 103 ? 8 soh-a22 second a2 x ? 104 ? 8 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation 2. address range 100-17f located in 128x8 gra. address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16-byte addresses of 16 byte j1 path trace to map a full 64 byte space
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 580 of 676 pnr25.chapt06.01 august 14, 2000 soh-a23 third a2 x ? 105 ? 8 soh-j0 j0 x ? 106 ? 8 reserved for national use and not included in frame scrambling x ? 107-8 ? 8 soh-b1 b1 x ? 109 ? 8 media dependant bytes x ? 10a-0b ? 8 soh-e1 e1 x ? 10c ? 8 media dependant byte x ? 10d ? 8 reserved for future standardization x ? 10e ? 8 soh-f1 f1 x ? 10f ? 8 reserved for national use x ? 110-11 ? 8 soh-d1 d1 x ? 112 ? 8 media dependant bytes x ? 113-14 ? 8 soh-d2 d2 x ? 115 ? 8 media dependant byte x ? 116 ? 8 reserved for future standardization x ? 117 ? 8 soh-d3 d3 x ? 118 ? 8 reserved for future standardization x ? 119-1a ? 8 soh-h1 h1 x ? 11b ? 8 soh-j0 x ? 11c-1d ? 8 b ? 1001ss11 ? with s unspeci- fied soh-h2 h2 x ? 11e ? 8 soh-1s x ? ff ? x ? 11f-20 ? 8 soh-h31 first h3 x ? 121 ? 8 soh-h32 second h3 x ? 122 ? 8 soh-h23 third h3 x ? 123 ? 8 soh-b21 first b2 x ? 124 ? 8 soh-b22 second b2 x ? 125 ? 8 soh-b23 third b2 x ? 126 ? 8 soh-k1 k1 x ? 127 ? 8 reserved for future standardization x ? 128-29 ? 8 soh-k2 k2 x ? 12a ? 8 reserved for future standardization x ? 12b-2c ? 8 soh-d4 d4 x ? 12d ? 8 reserved for future standardization x ? 12e-2f ? 8 soh-d5 d5 x ? 130 ? 8 reserved for future standardization x ? 131-32 ? 8 soh-d6 d6 x ? 133 ? 8 ofp_tx gpp handler address mapping base address = x ? 400 ? (page 2 of 3) register name description address offset type width initial value 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation 2. address range 100-17f located in 128x8 gra. address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16-byte addresses of 16 byte j1 path trace to map a full 64 byte space
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 581 of 676 reserved for future standardization x ? 134-35 ? 8 soh-d7 d7 x ? 136 ? 8 reserved for future standardization x ? 137-38 ? 8 soh-d8 d8 x ? 139 ? 8 reserved for future standardization x ? 13a-3b ? 8 soh-d9 d9 x ? 13c ? 8 reserved for future standardization x ? 13d-3e ? 8 soh-d10 d10 x ? 13f ? 8 reserved for future standardization x ? 140-41 ? 8 soh-d11 d11 x ? 142 ? 8 reserved for future standardization x ? 143-44 ? 8 soh-d12 d12 x ? 145 ? 8 reserved for future standardization x ? 146-47 ? 8 soh-s1 s1 x ? 148 ? 8 soh-z11 reserved for future standardization x ? 149-4c ? 8 soh-m1 m1 x ? 14d ? 8 soh-m1 e2 x ? 14e ? 8 reserved for future standardization x ? 14f-50 ? 8 justification stuff bytes x ? 151-53 ? 8 poh-j1 j1 x ? 154 ? 8 poh-b3 b3 x ? 155 ? 8 poh-c2 c2 x ? 156 ? 8 poh-g1 g1 x ? 157 ? 8 poh-f2 f2 x ? 158 ? 8 poh-h4 h4 x ? 159 ? 8 poh-f3 f3 x ? 15a ? 8 poh-k3 k3 x ? 15b ? 8 x ? poh-n1 ? n1 15c 8 reserved x ? 15d-5f ? 8 poh-j0-16 16 byte j0 section trace x ? 160-6f ? 8 reserved x ? 170-7f ? 8 poh-j1-16 16-byte j1 path trace 3 x ? 180-8f ? 8 poh-j1-64 64-byte j1 path trace 3 x ? 190-bf ? 8 ofp_tx gpp handler address mapping base address = x ? 400 ? (page 3 of 3) register name description address offset type width initial value 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation 2. address range 100-17f located in 128x8 gra. address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16-byte addresses of 16 byte j1 path trace to map a full 64 byte space
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 582 of 676 pnr25.chapt06.01 august 14, 2000 ofp_tx register description counter registers 24.54: ptrinc number of pointer increment events (eight-bit counter). overflow leads to an interrupt request. 24.55: ptrdec number of pointer decrement events (eight-bit counter). overflow leads to an interrupt request. length 8 bits type read address 404/405 power on value x ? 00 ? ptrinc 76543210 bit(s) name description 7-0 ptrinc(7-0) pointer increment counter length 8 bits type read address 406/407 power on value x ? 00 ? ptrdec 76543210 bit(s) name description 7-0 ptrdec(7-0) pointer decrement counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 583 of 676 24.56: nd_evcnt number of new data events (eight-bit counter). overflow leads to an interrupt request. 24.57: juscnt number of justification errors detected (eight-bit counter). overflow leads to an interrupt request. length 8 bits type read address 408/409 power on value x ? 00 ? nd_evcnt 76543210 bit(s) name description 7-0 nd_evcnt(7-0) new data event counter length 8 bits type read address 40a/40b power on value x ? 00 ? juscnt 76543210 bit(s) name description 7-0 juscnt(7-0) justification error counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 584 of 676 pnr25.chapt06.01 august 14, 2000 24.58: juscntth11 threshold for number of justification errors. threshold overstep leads to an interrupt request. 24.59: cnten1 counter on/off control register for ofp_tx. for each bit position: 0 = counter is disabled. 1 = counter is enabled. length 8 bits type read/write address 40c power on value x ? 80 ? juscntth11 76543210 bit(s) name description 7-0 juscntth11(7-0) threshold for justificication error counter length 8 bits type read/write address 402 power on value x ? 00 ? reserved en-juscnt en-nd_evcnt en-ptrdec en-ptrinc 76543210 bit(s) name description 7-4 reserved reserved 3 en-juscnt justification error counter enable 2 en-nd_evcnt new data event counter enable 1 en-ptrdec pointer decrement counter enable 0 en-ptrinc pointer increment counter enable
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 585 of 676 24.60: reset register (reset) reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal resot coming from gppint chiplet. for each bit position: 0 = reset/halt not active. 1 = reset/halt active. length 8 bits type read/write address 430 power on value x ? 01 ? reserved halt ofp_tx reset ofp_tx 76543210 bit(s) description 7-2 reserved 1 halt (freeze) ofp_tx chiplet 0 reset (disable) ofp_tx chiplet
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 586 of 676 pnr25.chapt06.01 august 14, 2000 24.61: command register (cmd1) command register for the chiplet. single-cycle active if b ? 1 ? is written into bit position. length 8 bits type read/write address 431 power on value x ? 00 ? reserved ndf pjus njus 76543210 bit(s) name description 7-3 reserved reserved 2 ndf force a start-of-new-vc-4 event 1 pjus perform a positive frequency justification 0 njus perform a negative frequency justification
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 587 of 676 status registers 24.62: stat1 status register #1 of the chiplet. this is an event latch register. 24.63: stat2 status register #2 of the chiplet. this is an event latch register. length 8 bits type read/write address 433 power on value x ? 00 ? reserved hug init 76543210 bit(s) name description 7-2 reserved reserved 1 hug 0 higher order unequipped generator inactive 1 higher order unequipped generator active 0init 0 default gra initialization not completed 1 default gra initialization completed ? length 8 bits type read/write address 434 power on value - reserved ndf pjus njus 76543210 bit(s) name description 7-3 reserved reserved 2 ndf 0 no ndf transmitted 1 ndf transmitted 1 pjus 0 no positive frequency justification transmitted 1 positive frequency justification transmitted 0 njus 0 no negative frequency justification transmitted 1 negative frequency justification transmitted
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 588 of 676 pnr25.chapt06.01 august 14, 2000 interrupt and mask registers 24.64: mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 438 power on value - reserved irq3 cntrirq1 fatal 76543210 bit(s) name description 7-3 reserved reserved 2 irq3 active request in irq3 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 589 of 676 24.65: m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates signal irqot to gppint. length 8 bits type read/write address 439 power on value x ? 00 ? reserved irq3 cntrirq1 fatal 76543210 bit(s) name description 7-3 reserved reserved 2 irq3 active request in irq3 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 590 of 676 pnr25.chapt06.01 august 14, 2000 24.66: cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 43a power on value - reserved th-juscnt ov-juscnt ov-nd_evcnt ov-ptrinc ov-ptrdec 76543210 bit(s) name description 7-5 reserved reserved 4 th-juscnt threshold overstep justification error counter 3 ov-juscnt overflow justification error counter 2 ov-nd_evcnt overflow new data event counter 0 ov-ptrinc overflow pointer increment counter 1 ov-ptrdec overflow pointer decrement counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 591 of 676 24.67: m_cntrirq1 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 43b power on value x ? 00 ? reserved th-juscnt ov-juscnt ov-nd_evcnt ov-ptrinc ov-ptrdec 76543210 bit(s) name description 7-5 reserved reserved 4 th-juscnt threshold overstep justification error counter 3 ov-juscnt overflow justification error counter 2 ov-nd_evcnt overflow new data event counter 0 ov-ptrinc overflow pointer increment counter 1 ov-ptrdec overflow pointer decrement counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 592 of 676 pnr25.chapt06.01 august 14, 2000 24.68: irq3 register to indicate active user interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 43c power on value - reserved dloss flow fhigh frmerr spcir txlpow 76543210 bit(s) name description 7-6 reserved reserved 5 dloss data loss = data fifo empty 4 flow fifo low threshold overflow 3 fhigh fifo high threshold overflow 2: frmerr framing error detected 1 spcir spc fsm interrupt request 0 txlpow low power indication from optical/electrical module
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 593 of 676 24.69: m_irq3 register to mask pending user interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 43d power on value x ? 00 ? reserved dloss flow fhigh frmerr spcir txlpow 76543210 bit(s) name description 7-6 reserved reserved 5 dloss data loss = data fifo empty 4 flow fifo low threshold overflow 3 fhigh fifo high threshold overflow 2 frmerr framing error detected 1 spcir spc fsm interrupt request 0 txlpow low power indication from optical/electrical module
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 594 of 676 pnr25.chapt06.01 august 14, 2000 configuration registers 24.70: conf1 configuration register #1. general ofp_tx configuration signals a. length 8 bits type read/write address 448 power on value x ? 03 ? spci j1mode jusfrm autrst_sta autrst_int 76543210 bit(s) name description 7-4 spci(7-4) specifies stm-n row number in which an interrupt request will be issued 3 j1mode 0 transmit 16-byte j1 path trace 1 transmit 64-byte j1 path trace 2jusfrm 0 allow pointer modification to be performed on frame-to-frame basis 1 enforces three frames being interleaved between two pointer modification operations 1autrst_sta 0 no action on read access 1 auto-reset status register upon read access 0autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 595 of 676 24.71: conf2 configuration register #2. general ofp_tx configuration signals b. 24.72: conf3 configuration register #3. length 8 bits type read/write address 449 power on value x ? 00 ? reserved txsdown hug msais 76543210 bit(s) name description 7-3 reserved reserved 2 txsdown directly connected to output pin : 0 optical/electrical normal operation 1 transmit shutdown for optical/electrical module 1 hug 0 no unequipped stm-n signal 1 enforce unequipped stm-n signal 0msais 0 no multiplex section ais 1 enforce multiplex section ais length 8 bits type read/write address 44a power on value x ? fe ? not used fscr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 not used 7-0 fscr(7-0) reload pattern for frame scrambler
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 596 of 676 pnr25.chapt06.01 august 14, 2000 24.73: conf4 configuration register #4. 24.74: conf5 configuration register #5. length 8 bits type read/write address 44b power on value x ? 00 ? errmask 76543210 bit(s) name description 7-0 errmask(7-0) mask register forcing bit error insertion. xored with retrieved soh/poh length 8 bits type read/write address 44c power on value x ? 00 ? erraddr 76543210 bit(s) name description 7-0 erraddr(7-0) error mask address register. indicates address of soh/poh byte to be corrupted
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 597 of 676 24.75: conf6 configuration register #6. frame scrambling control register. length 8 bits type read/write address 44d power on value x ? 01 ? cidnum ciden scren 76543210 bit(s) name description 7-2 cidnum(7-2) number of all - ? 1 ? / ? 0 ? bytes 1ciden cid insertion enable: 0 no cid insertion 1 perform cid insertion 0scren scramble enable: 0 no scrambling 1 perform scrambling
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: transmit direction page 598 of 676 pnr25.chapt06.01 august 14, 2000 24.76: conf7 configuration register #7. dcc control register. 24.77: conf8 configuration registers #8. low water fifo threshold register. length 8 bits type read/write address 44e power on value x ? 00 ? reserved edge mode clkmode opmode enable 76543210 bit(s) name description 7-4 reserved reserved 3 edgemode 0 active falling edge 1 active rising edge 2 clkmode 0 continuous clock 1 strobed clock 1 opmode 0 dcc1 channel (d1 - d3) 1 cc2 channel (d4 - d12) 0 enable 0 disable dcc1 processing 1 enable dcc1 processing length 8 bits type read/write address 44f power on value x ? 03 ? reserved thrlow (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrlow(7-2) low water fifo threshold; default value is three
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: transmit direction page 599 of 676 24.78: conf9 configuration registers #9. normal water fifo threshold register. 24.79: conf10 configuration registers #10. high water fifo threshold register. length 8 bits type read/write address 450 power on value x ? 11 ? reserved thrnow (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrnow(7-2) normal water fifo threshold; default value is 17 length 8 bits type read/write address 451 power on value x ? 20 ? reserved thrhiw (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrhiw(7-2) high water fifo threshold; default value is 32
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 600 of 676 pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction ofp_rx gpp handler address mapping base address = x ? 800 ? (page 1 of 4) register name description address offset type width initial value rofmid read-on-the-fly register x ? 0 ? f 8 ? 00000000 ? cnten1 count enable register #1 x ? 2 ? x 8 ? 00000000 ? cnten2 count enable register #2 x ? 3 ? x 3 ? 000 ? b1bitcnt bip-8 b1 bit error counter x ? 4/5 ? 1 n 16 ? x ? 0000 ?? b1bitcntth12 threshold register byte2 (least significant byte) for b1bitcnt x ? 6 ? x 8 ? 00000000 ? b1bitcntth11 threshold register byte1 for counter b1bitcnt x ? 7 ? x 8 ? 01111101 ? b1blkcnt bip-8 b1 block error counter 1 )x ? 8/9 ? 1 n 16 ? x ? 0000 ?? b1blkcntth12 threshold register byte2 (least significant byte) for b1blkcnt x ? a ? x 8 ? 00000000 ? b1blkcntth11 threshold register byte1 for counter b1blkcnt x ? b ? x 8 ? 01111101 ? b2bitcnt bip-24 b2 bit error counter, 2 thresholds 1 x ? c/d ? 1 n 16 ? x ? 0000 ?? b2bitcntth12 degradation threshold byte2 (least significant byte) for b2bitcnt x ? e ? x 8 ? 00100000 ? b2bitcntth11 degradation threshold byte1 for b2bitcnt x ? f ? x 8 ? 01001110 ? b2bitcntth22 failure threshold byte2 (least significant byte) for b2bitcnt x ? 10 ? x 8 ? 00000000 ? b2bitcntth21 failure threshold byte1 for b2bitcnt x ? 11 ? x 8 ? 01111101 ? b2blkcnt bip-24 b2 block error counter, 2 thresholds 1 x ? 12/13 ? 1 n 16 ? x ? 0000 ?? b2blkcntth12 degration threshold byte2 (least significant byte) for b2blkcnt x ? 14 ? x 8 ? 00100000 ? b2blkcntth11 degradation threshold byte1 forb2blkcnt x ? 15 ? x 8 ? 01001110 ? b2blkcntth22 failure threshold byte2 (least significant byte) for b2blkcnt x ? 16 ? x 8 ? 00000000 ? b2blkcntth21 failure threshold byte1 for b2blkcnt x ? 17 ? x 8 ? 01111101 ? b3bitcnt bip-8 b3 bit error counter 1 x ? 18/19 ? 1 n 16 ? x ? 0000 ?? b3bitcntth12 threshold register byte2 (least significant byte) for b3bitcnt x ? 1a ? x 8 ? 00000000 ? b3bitcntth11 threshold register byte1 for counter b3bitcnt x ? 1b ? x 8 ? 01111101 ? b3blkcnt bip-8 b3 block error counter 1 x ? 1c/1d ? 1 n 16 ? x ? 0000 ?? b3blkcntth12 threshold register byte2 (least significant byte) for b3blkcnt x ? 1e ? x 8 ? 00000000 ? b3blkcntth11 threshold register byte1 for counter b3blkcnt x ? 1f ? x 8 ? 01111101 ? msreicnt multiplex section remote error indication counter 1 x ? 20/21 ? 1 n 16 ? x ? 0000 ?? msreicntth12 threshold register byte2 (least significant byte) for msreicnt x ? 22 ? x 8 ? 00000000 ? msreicntth11 threshold register byte1 for counter msreicnt x ? 23 ? x 8 ? 01111101 ? hpreicnt higher-order path remote error indication counter 1 x ? 24/25 ? 1 n 16 ? x ? 0000 ?? hpreicntth12 threshold register byte2 (least significant byte) for hpreicnt x ? 26 ? x 8 ? 00000000 ? hpreicntth11 threshold register byte1 for counter hpreicnt x ? 27 ? x 8 ? 01111101 ? pj_evcnt positive justification counter, no threshold 1 x ? 28/29 ? 1 n 8 ? 00000000 ? nj_evcnt negative justification counter, no threshold 1 x ? 2a/2b ? 1 n 8 ? 00000000 ? 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation. 2. address range 100-17f located in 128x8. gra address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 601 of 676 nd_evcnt new data event counter, no threshold 1 x ? 2c/2d ? 1 n 8 ? 00000000 ? reset default reset register x ? 30 ? r 2 ? 01 ? stat1 status register #1 (mode) x ? 33 ? s 3 stat2 status register #2 (au pointer) x ? 34 ? s 6 stat3 status register #3 (soh) x ? 35 ? s 6 stat4 status register #4 (poh) x ? 36 ? s 4 mainirq main interrupt register x ? 38 ? i 7 m_mainirq interrupt mask register for mainirq x ? 39 ? x 7 ? 0000000 ? cntrirq1 counter interrupt register x ? 3a ? i 8 m_cntrirq1 interrupt mask register for cntrirq1 x ? 3b ? x 8 ? 00000000 ? cntrirq2 counter interrupt register x ? 3c ? i 8 m_cntrirq2 interrupt mask register for cntrirq2 x ? 3d ? x 8 ? 00000000 ? cntrirq3 counter interrupt register x ? 3e ? i 5 m_cntrirq3 interrupt mask register for cntrirq3 x ? 3f ? x 5 ? 00000 ? irq6 user interrupt register x ? 40 ? i 4 m_irq6 interrupt mask register for irq6 x ? 41 ? x 4 ? 0000 ? irq7 user interrupt register x ? 42 ? i 8 m_irq7 interrupt mask register for irq7 x ? 43 ? x 8 ? 00000000 ? irq8 user interrupt register x ? 44 ? i 8 m_irq8 interrupt mask register for irq8 x ? 45 ? x 8 ? 00000000 ? conf1 configuration register #1 (general) x ? 48 ? c 8 ? 00111111 ? conf2 configuration register #2 (soh processing) x ? 49 ? c 6 ? 0000 ? conf3 configuration register #3 (poh processing) x ? 4a ? c 4 ? 0000 ? conf4 configuration register #4 (aps processing) x ? 4b ? c 8 ? 00000000 ? conf7 configuration register #7 (miscellaneous) x ? 4e ? c 8 ? 00100000 ? conf8 configuration register #8 (fscr) x ? 4f ? c 8 ? 11111110 ? conf9 configuration register #9 (sl) x ? 50 ? c 8 ? 00010011 ? soh-a11 first a1 x ? 100 ? 8 soh-a12 second1 a1 x ? 101 ? 8 soh-a13 third a1 x ? 102 ? 8 soh-a21 first a2 x ? 103 ? 8 soh-a22 second a2 x ? 104 ? 8 soh-a23 third a2 x ? 105 ? 8 soh-j0 j0 x ? 106 ? 8 reserved for national use and not included in frame scrambling (c1) x ? 107-8 ? 8 ofp_rx gpp handler address mapping base address = x ? 800 ? (page 2 of 4) register name description address offset type width initial value 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation. 2. address range 100-17f located in 128x8. gra address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space.
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 602 of 676 pnr25.chapt06.01 august 14, 2000 soh-b1 b1 x ? 109 ? 8 media dependant bytes x ? 10a-0b ? 8 soh-e1 e1 x ? 10c ? 8 media dependant byte x ? 10d ? 8 reserved for future standardization x ? 10e ? 8 soh-f1 f1 x ? 10f ? 8 reserved for national use x ? 110-11 ? 8 soh-d1 d1 x ? 112 ? 8 media dependant bytes x ? 113-14 ? 8 soh-d2 d2 x ? 115 ? 8 media dependant byte x ? 116 ? 8 reserved for future standardization x ? 117 ? 8 soh-d3 d3 x ? 118 ? 8 reserved for future standardization x ? 119-1a ? 8 soh-h1 h1 x ? 11b ? 8 soh-j0 b ? 1001ss11 ? with s unspecified x ? 11c-1d ? 8 soh-h2 h2 x ? 11e ? 8 soh-1s x ? ff ? x ? 11f-20 ? 8 soh-h31 first h3 x ? 121 ? 8 soh-h32 second h3 x ? 122 ? 8 soh-h23 third h3 x ? 123 ? 8 soh-b21 first b2 x ? 124 ? 8 soh-b22 second b2 x ? 125 ? 8 soh-b23 third b2 x ? 126 ? 8 soh-k1 k1 x ? 127 ? 8 reserved for future standardization x ? 128-29 ? 8 soh-k2 k2 x ? 12a ? 8 reserved for future standardization x ? 12b-2c ? 8 soh-d4 d4 x ? 12d ? 8 reserved for future standardization x ? 12e-2f ? 8 soh-d5 d5 x ? 130 ? 8 reserved for future standardization x ? 131-32 ? 8 soh-d6 d6 x ? 133 ? 8 reserved for future standardization x ? 134-35 ? 8 soh-d7 d7 x ? 136 ? 8 reserved for future standardization x ? 137-38 ? 8 soh-d8 d8 x ? 139 ? 8 reserved for future standardization x ? 13a-3b ? 8 ofp_rx gpp handler address mapping base address = x ? 800 ? (page 3 of 4) register name description address offset type width initial value 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation. 2. address range 100-17f located in 128x8. gra address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space.
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 603 of 676 soh-d9 d9 x ? 13c ? 8 reserved for future standardization x ? 13d-3e ? 8 soh-d10 d10 x ? 13f ? 8 reserved for future standardization x ? 140-41 ? 8 soh-d11 d11 x ? 142 ? 8 reserved for future standardization x ? 143-44 ? 8 soh-d12 d12 x ? 145 ? 8 reserved for future standardization x ? 146-47 ? 8 soh-s1 s1 x ? 148 ? 8 reserved for future standardization x ? 149-9c ? 8 soh-m1 m1 x ? 14d ? 8 soh-m1 e2 x ? 14e ? 8 reserved for future standardization x ? 14f-50 ? 8 reserved x ? 151-53 ? 8 poh-j1 j1 x ? 154 ? 8 poh-b3 b3 x ? 155 ? 8 poh-c2 c2 x ? 156 ? 8 poh-g1 g1 x ? 157 ? 8 poh-f2 f2 x ? 158 ? 8 poh-h4 h4 x ? 159 ? 8 poh-f3 f3 x ? 15a ? 8 poh-k3 k3 x ? 15b ? 8 poh-n1 n1 x ? 15c ? 8 reserved x ? 15d-5f ? 8 poh-j0-16-e expected 16-byte j0 section trace x ? 160-6f ? 8 poh-j0-16-r received 16-byte j0 section trace x ? 170-7f ? 8 poh-j1-16 expected 16-byte j1 path trace 3 x ? 180-8f ? 8 poh-j1-64 64-byte j1 path trace 3 x ? 190-bf ? 8 ofp_rx gpp handler address mapping base address = x ? 800 ? (page 4 of 4) register name description address offset type width initial value 1. independent of the counter width, given that a counter has chiplet address n as a base. reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no affect on the counter, but reading address n-1 resets the counter after read operation. 2. address range 100-17f located in 128x8. gra address range 180-1bf located in 64x8 gra. 3. the 64-byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space.
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 604 of 676 pnr25.chapt06.01 august 14, 2000 counter registers 24.80: rofmid read-on-the-fly registers. 24.81: b1bitcnt number of bip-8 b1 bit errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. length 8 bits type read address 800 power on value x ? 00 ? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register, most significant byte length 8 bits type read address 804/805 power on value x ? 00 ? b1bitcnt (8:15) 76543210 bit(s) name description 7-0 b1bitcnt(8:15) bip-8 b1 bit error counter, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 605 of 676 24.82: b1bitcntth11 threshold for number of bip-8 b1 bit errors. 24.83: b1bitcntth12 threshold for number of bip-8 b1 bit errors. threshold overstep leads to an interrupt request. length 8 bits type read/write address 807 power on value x ? 7d ? b1bitcntth11 76543210 bit(s) name description 7-0 b1bitcntth11(7-0) threshold for bip-8 b1 bit error counter, most significant byte length 8 bits type read/write address 806 power on value x ? 00 ? b1bitcntth12 76543210 bit(s) name description 7-0 b1bitcntth12(7-0) threshold for bip-8 b1 bit error error counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 606 of 676 pnr25.chapt06.01 august 14, 2000 24.84: b1blkcnt number of bip-8 b1 block errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. 24.85: b1blkcntth11 threshold for number of bip-8 b1 block errors. length 8 bits type read address 808/809 power on value x ? 00 ? b1blkcnt (8:15) 76543210 bit(s) name description 7-0 b1blkcnt(8:15) bip-8 b1 block error counter, least significant byte length 8 bits type read/write address 80b power on value x ? 7d ? b1blkcntth11 76543210 bit(s) name description 7-0 b1blkcntth11(7-0) threshold for bip-8 b1 block error counter, most significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 607 of 676 24.86: b1blkcntth12 threshold for number of bip-8 b1 block errors. threshold overstep leads to an interrupt request. 24.87: b2bitcnt number of bip-24 b2 bit errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. length 8 bits type read/write address 80a power on value x ? 00 ? b1blkcntth12 76543210 bit(s) name description 7-0 b1blkcntth12(7-0) threshold for bip-8 b1 block error counter, least significant byte length 8 bits type read address 80c/80d power on value x ? 00 ? b2bitcnt (8:15) 76543210 bit(s) name description 7-0 b2bitcnt(8:15) bip-24 b2 bit error counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 608 of 676 pnr25.chapt06.01 august 14, 2000 24.88: b2bitcntth11 degradation threshold for number of bip-24 b2 bit errors. 24.89: b2bitcntth12 degradation threshold for number of bip-24 b2 bit errors. threshold overstep leads to an interrupt request. length 8 bits type read/write address 80f power on value x ? 4e ? b2bitcntth11 76543210 bit(s) name description 7-0 b2bitcntth11(7-0) degradation threshold for bip-24 b2 bit error counter, most significant byte length 8 bits type read/write address 80e power on value x ? 20 ? b2bitcntth12 76543210 bit(s) name description 7-0 b2bitcntth12(7-0) degradation threshold for bip-24 b2 bit error counter, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 609 of 676 24.90: b2bitcntth21 failure threshold for number of bip-24 b2 bit errors. 24.91: b2bitcntth22 failure threshold for number of bip-24 b2 bit errors. threshold overstep leads to an interrupt request. length 8 bits type read/write address 811 power on value x ? 7d ? b2bitcntth21 76543210 bit(s) name description 7-0 b2bitcntth21(7-0) failure threshold for bip-24 b2 bit error counter, most significant byte length 8 bits type read/write address 810 power on value x ? 00 ? b2bitcntth22 76543210 bit(s) name description 7-0 b2bitcntth22(7-0) failure threshold for bip-24 b2 bit error counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 610 of 676 pnr25.chapt06.01 august 14, 2000 24.92: b2blkcnt number of bip-24 b2 block errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. 24.93: b2blkcntth11 degradation threshold for number of bip-24 b2 block errors. length 8 bits type read address 812/813 power on value x ? 00 ? b2blkcnt 76543210 bit(s) name description 7-0 b2blkcnt(8:15) bip-24 b2 block error counter, least significant byte length 8 bits type read/write address 815 power on value x ? 4e ? b2blkcntth11 76543210 bit(s) name description 7-0 b2blkcntth11(7-0) degradation threshold for bip-24 b2 block error counter, most significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 611 of 676 24.94: b2blkcntth12 degradation threshold for number of bip-24 b2 block errors. threshold overstep leads to an interrupt request. 24.95: b2blkcntth21 failure threshold for number of bip-24 b2 block errors. length 8 bits type read/write address 814 power on value x ? 20 ? b2blkcntth12 76543210 bit(s) name description 7-0 b2blkcntth12(7-0) degradation threshold for bip-24 b2 block error counter, least significant byte length 8 bits type read/write address 817 power on value x ? 7d ? b2blkcntth21 76543210 bit(s) name description 7-0 b2blkcntth21(7-0) failure threshold for bip-24 b2 block error counter, most significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 612 of 676 pnr25.chapt06.01 august 14, 2000 24.96: b2blkcntth22 failure threshold for number of bip-24 b2 block errors. threshold overstep leads to an interrupt request. 24.97: b3bitcnt number of bip-8 b3 bit errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. length 8 bits type read/write address 816 power on value x ? 00 ? b2blkcntth22 76543210 bit(s) name description 7-0 b2blkcntth22(7-0) failure threshold for bip-24 b2 block error counter, least significant byte length 8 bits type read address 818/819 power on value x ? 00 ? b3bitcnt 76543210 bit(s) name description 7-0 b3bitcnt(8:15) bip-8 b3 bit error counter, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 613 of 676 24.98: b3bitcntth11 threshold for number of bip-8 b3 bit errors. 24.99: b3bitcntth12 threshold for number of bip-8 b3 bit errors. threshold overstep leads to an interrupt request. length 8 bits type read/write address 81b power on value x ? 7d ? b3bitcntth11 76543210 bit(s) name description 7-0 b3bitcntth11(7-0) threshold for bip-8 b3 bit error counter, most significant byte length 8 bits type read/write address 81a power on value x ? 00 ? b3bitcntth12 76543210 bit(s) name description 7-0 b3bitcntth12(7-0) threshold for bip-8 b3 bit error counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 614 of 676 pnr25.chapt06.01 august 14, 2000 24.100: b3blkcnt number of bip-8 b3 block errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. 24.101: b3blkcntth11 threshold for number of bip-8 b3 block errors. length 8 bits type read address 81c/81d power on value x ? 00 ? b3blkcnt 76543210 bit(s) name description 7-0 b3blkcnt(8:15) bip-8 b3 block error counter, least significant byte length 8 bits type read/write address 81f power on value x ? 7d ? b3blkcntth11 76543210 bit(s) name description 7-0 b3blkcntth11(7-0) threshold for bip-8 b3 block error counter, most significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 615 of 676 24.102: b3blkcntth12 threshold for number of bip-8 b3 block errors. threshold overstep leads to an interrupt request. 24.103: msreicnt multiplex section remote error indication counter (16-bit counter). overflow leads to an interrupt request. length 8 bits type read/write address 81e power on value x ? 00 ? b3blkcntth12 76543210 bit(s) name description 7-0 b3blkcntth12(7-0) threshold for bip-8 b3 block error counter, least significant byte length 8 bits type read address 820/821 power on value x ? 00 ? msreicnt (8:15) 76543210 bit(s) name description 7-0 msreicnt(8:15) multiplex section remote error indication counter, least significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 616 of 676 pnr25.chapt06.01 august 14, 2000 24.104: msreicntth11 threshold for number of multiplex section remote errors. 24.105: msreicntth12 threshold for number of multiplex section remote errors. threshold overstep leads to an interrupt request. length 8 bits type read/write address 823 power on value x ? 7d ? msreicntth11 76543210 bit(s) name description 7-0 msreicntth11(7-0) threshold for multiplex indication counter section remote error, most significant byte length 8 bits type read/write address 822 power on value x ? 00 ? msreicntth12 76543210 bit(s) name description 7-0 msreicntth12(7-0) threshold for multiplex indication counter section remote error, least significant byte
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 617 of 676 24.106: hpreicnt higher-order path remote error indication counter (16-bit counter). overflow leads to an interrupt request. 24.107: hpreicntth11 threshold for number of higher-order path remote errors. length 8 bits type read address 824/825 power on value x ? 00 ? hpreicnt (8:15) 76543210 bit(s) name description 7-0 hpreicnt(8:15) higher-order path remote error indication counter, least significant byte length 8 bits type read/write address 827 power on value x ? 7d ? hpreicntth11 76543210 bit(s) name description 7-0 hpreicntth11(7-0) threshold for higher-order path remote error indication counter, most significant byte
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 618 of 676 pnr25.chapt06.01 august 14, 2000 24.108: hpreicntth12 threshold for number of higher-order path remote errors. threshold overstep leads to an interrupt request. 24.109: pj_evcnt positive justification event counter (eight-bit counter). overflow leads to an interrupt request. length 8 bits type read/write address 826 power on value x ? 00 ? hpreicntth12 76543210 bit(s) name description 7-0 hpreicntth12(7-0) threshold for higher-order path remote error indication counter, least significant byte length 8 bits type read address 828/829 power on value x ? 00 ? pj_evcnt 76543210 bit(s) name description 7-0 pj_evcnt(7-0) positive justification event counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 619 of 676 24.110: nj_evcnt negative justification event counter (eight-bit counter). overflow leads to an interrupt request. 24.111: nd_evcnt new data event counter (eight-bit counter). overflow leads to an interrupt request. length 8 bits type read address 82a/82b power on value x ? 00 ? nj_evcnt 76543210 bit(s) name description 7-0 nj_evcnt(7-0) negative justification event counter length 8 bits type read address 82c/82d power on value x ? 00 ? nd_evcnt 76543210 bit(s) name description 7-0 nd_evcnt(7-0) new data event counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 620 of 676 pnr25.chapt06.01 august 14, 2000 24.112: cnten1 counter on/off control register #1 for ofp_rx. for each bit position: 0 = counter is disabled. 1 = counter is enabled. length 8 bits type read/write address 802 power on value x ? 00 ? en-hpreicnt en-msreicnt en-b3blkcnt en-b3bitcnt en-b2blkcnt en-b2bitcnt en-b1blkcnt en-b1bitcnt 76543210 bit(s) name description 7 en-hpreicnt higher-order path remote error indication counter enable 6 en-msreicnt multiplex section remote error indication counter enable 5 en-b3blkcnt bip-8 b3 block error counter enable 4 en-b3bitcnt bip-8 b3 bit error counter enable 3 en-b2blkcnt bip-24 b2 block error counter enable 2 en-b2bitcnt bip-24 b2 bit error counter enable 1 en-b1blkcnt bip-8 b1 block error counter enable 0 en-b1bitcnt bip-8 b1 bit error counter enable
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 621 of 676 24.113: cnten2 counter on/off control register #2 for ofp_rx. for each bit position: 0 = counter is disabled. 1 = counter is enabled. length 8 bits type read/write address 803 power on value x ? 00 ? reserved en-nd_evcnt en-nj_evcnt en-pj_evcnt 76543210 bit(s) name description 7-3 reserved reserved 2 en-nd_evcnt new data event counter enable 1 en-nj_evcnt negative justification event counter enable 0 en-pj_evcnt positive justification event counter enable
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 622 of 676 pnr25.chapt06.01 august 14, 2000 24.114: reset register (reset) reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal resot coming from gppint chiplet. for each bit position: 0 = reset/halt not active. 1 = reset/halt active. status registers 24.115: stat1 status register #1 of the chiplet. ofp_rx mode status information. this is an event latch register. length 8 bits type read/write address 830 power on value x ? 01 ? reserved halt ofp_rx reset ofp_rx 76543210 bit(s) description 7-2 reserved 1 halt (freeze) ofp_rx chiplet 0 reset (disable) ofp_rx chiplet length 8 bits type - address 833 power on value - reserved 76543210 bit(s) description 7-0 reserved
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 623 of 676 24.116: stat2 status register #2 of the chiplet. au pointer status information of ofp_rx. this is an event latch register. length 8 bits type read/write address 834 power on value - reserved concrx newptr invptr ndf pjus njus 76543210 bit(s) name description 7-6 reserved reserved 5 concrx concatenation indication received 4 newptr valid new pointer received 3 invptr invalid pointer received 2 ndf ndf received 1 pjus positive frequency justification received 0 njus negative frequency justification received
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 624 of 676 pnr25.chapt06.01 august 14, 2000 24.117: stat3 status register #3 of the chiplet. section overhead (soh) status of ofp_rx. this is an event latch register. length 8 bits type read/write address 835 power on value - reserved e1chg e2chg f1chg d1chg d4chg m1chg 76543210 bit(s) name description 7-6 reserved reserved 5 e1chg orderwire channel e1 content changed 4 e2chg orderwire channel e2 content changed 3 f1chg user communication channel f1 content changed 2 d1chg d1-d3 communication channel content changed 1 d4chg d4-d12 communication channel content changed 0 m1chg number of bit blocks in error changed
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 625 of 676 24.118: stat4 status register #4 of the chiplet. path overhead (poh) status of ofp_rx. this is an event latch register. length 8 bits type read/write address 836 power on value - reserved c2chg g1chg f2chg z5 76543210 bit(s) name description 7-4 reserved reserved 3 c2chg payload composition indication changed 2 g1chg path status indication changed 1 f2chg user communication channel f2 content changed 0 z5 z5 content changed
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 626 of 676 pnr25.chapt06.01 august 14, 2000 interrupt and mask registers 24.119: mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 838 power on value - reserved irq8 irq7 irq6 cntrirq3 cntrirq2 cntrirq1 fatal 76543210 bit(s) name description 7 reserved reserved 6 irq8 active request in irq8 register 5 irq7 active request in irq7 register 4 irq6 active request in irq6 register 3 cntrirq3 active request in cntrirq3 register 2 cntrirq2 active request in cntrirq2 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 627 of 676 24.120: m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates signal irqor to gppint. length 8 bits type read/write address 839 power on value x ? 00 ? reserved irq8 irq7 irq6 cntrirq3 cntrirq2 cntrirq1 fatal 76543210 bit(s) name description 7 reserved reserved 6 irq8 active request in irq8 register 5 irq7 active request in irq7 register 4 irq6 active request in irq6 register 3 cntrirq3 active request in cntrirq3 register 2 cntrirq2 active request in cntrirq2 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 628 of 676 pnr25.chapt06.01 august 14, 2000 24.121: cntrirq1 register #1 to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 83a power on value - ov-b2blkcnt t2-b2bitcnt th-b2bitcnt ov-b2bitcnt th-b1blkcnt ov-b1blkcnt th-b1bitcnt ov-b1bitcnt 76543210 bit(s) name description 7 ov-b2blkcnt overflow bip-24 b2 block error counter 6 t2-b2bitcnt failure threshold overstep bip-24 b2 bit error counter 5 th-b2bitcnt degradation threshold overstep bip-24 b2 bit error counter 4 ov-b2bitcnt overflow bip-24 b2 bit error counter 3 th-b1blkcnt threshold overstep bip-8 b1 block error counter 2 ov-b1blkcnt overflow bip-8 b1 block error counter 1 th-b1bitcnt threshold overstep bip-8 b1 bit error counter 0 ov-b1bitcnt overflow bip-8 b1 bit error counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 629 of 676 24.122: m_cntrirq1 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 83b power on value x ? 00 ? ov-b2blkcnt t2-b2bitcnt th-b2bitcnt ov-b2bitcnt th-b1blkcnt ov-b1blkcnt th-b1bitcnt ov-b1bitcnt 76543210 bit(s) name description 7 ov-b2blkcnt overflow bip-24 b2 block error counter 6 t2-b2bitcnt failure threshold overstep bip-24 b2 bit error counter 5 th-b2bitcnt degradation threshold overstep bip-24 b2 bit error counter 4 ov-b2bitcnt overflow bip-24 b2 bit error counter 3 th-b1blkcnt threshold overstep bip-8 b1 block error counter 2ov-b1blkcnt overflow bip-8 b1 block error counter 1 th-b1bitcnt threshold overstep bip-8 b1 bit error counter 0 ov-b1bitcnt overflow bip-8 b1 bit error counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 630 of 676 pnr25.chapt06.01 august 14, 2000 24.123: cntrirq2 register #2 to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 83c power on value - th-msreicnt ov-msreicnt th-b3blkcnt ov-b3blkcnt th-b3bitcnt ov-b3bitcnt t2-b2blkcnt th-b2blkcnt 76543210 bit(s) name description 7 th-msreicnt threshold overstep multiplex section remote error indication counter 6 ov-msreicnt overflow multiplex section remote error indication counter 5 th-b3blkcnt threshold overstep bip-8 b3 block error counter 4 ov-b3blkcnt overflow bip-8 b3 block error counter 3 th-b3bitcnt threshold overstep bip-8 b3 bit error counter 2 ov-b3bitcnt overflow bip-8 b3 bit error counter 1 t2-b2blkcnt failure threshold overstep bip-24 b2 block error counter 0 th-b2blkcnt degradation threshold overstep bip-24 b2 block error counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 631 of 676 24.124: m_cntrirq2 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 83d power on value x ? 00 ? th-msreicnt ov-msreicnt th-b3blkcnt ov-b3blkcnt th-b3bitcnt ov-b3bitcnt t2-b2blkcnt th-b2blkcnt 76543210 bit(s) name description 7 th-msreicnt threshold overstep multiplex section remote error indication counter 6 ov-msreicnt overflow multiplex section remote error indication counter 5 th-b3blkcnt threshold overstep bip-8 b3 block error counter 4 ov-b3blkcnt overflow bip-8 b3 block error counter 3 th-b3bitcnt threshold overstep bip-8 b3 bit error counter 2 ov-b3bitcnt overflow bip-8 b3 bit error counter 1 t2-b2blkcnt failure threshold overstep bip-24 b2 block error counter 0 th-b2blkcnt degradation threshold overstep bip-24 b2 block error counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 632 of 676 pnr25.chapt06.01 august 14, 2000 24.125: cntrirq3 register #3 to indicate active counter interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 83e power on value - reserved ov-nd_evcnt ov-nj_evcnt ov-pj_evcnt th-hpreicnt ov-hpreicnt 76543210 bit(s) name description 7-5 reserved reserved 4 ov-nd_evcnt overflow new data event counter 3 ov-nj_evcnt overflow negative justification event counter 2 ov-pj_evcnt overflow positive justification event counter 1 th-hpreicnt threshold overstep higher-order path remote error indication counter 0 ov-hpreicnt overflow hpr error indication counter
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 633 of 676 24.126: m_cntrirq3 register to mask pending counter interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 83f power on value x ? 00 ? reserved ov-nd_evcnt ov-nj_evcnt ov-pj_evcnt th-hpreicnt ov-hpreicnt 76543210 bit(s) name description 7-5 reserved reserved 4 ov-nd_evcnt overflow new data event counter 3 ov-nj_evcnt overflow negative justification event counter 2 ov-pj_evcnt overflow positive justification event counter 1 th-hpreicnt threshold overstep higher-order path remote error indication counter 0 ov-hpreicnt overflow hpr error indication counter
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 634 of 676 pnr25.chapt06.01 august 14, 2000 24.127: irq6 register to indicate active user interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 840 power on value - reserved sdbfull frmerr s1chg hprei 76543210 bit(s) name description 7-4 reserved reserved 3 sdbfull sdb_rx fifo full 2 frmerr interrupt from orxaug fsm 1 s1chg synchronization status changed 0 hprei higher-order path remote error indication
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 635 of 676 24.128: m_irq6 register to mask pending user interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 841 power on value x ? 00 ? reserved sdbfull frmerr s1chg hprei 76543210 bit(s) name description 7-4 reserved reserved 3 sdbfull sdb_rx fifo full 2 frmerr interrupt from orxaug fsm 1 s1chg synchronization status changed 0 hprei higher-order path remote error indication
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 636 of 676 pnr25.chapt06.01 august 14, 2000 24.129: irq7 register to indicate active user interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 842 power on value - oof los lof lop hpais hprdi uneq slm 76543210 bit(s) name description 7 oof out of frame alarm 6 los loss of signal alarm 5 lof loss of frame alarm 4 lop loss of pointer alarm 3 hpais higher-order path ais 2 hprdi higher-order path rdi 1 uneq unequipped signal 0 slm signal label mismatch alarm
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 637 of 676 24.130: m_irq7 register to mask pending user interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 843 power on value x ? 00 ? oof los lof lop hpais hprdi uneq slm 76543210 bit(s) name description 7 oof out of frame alarm 6 los loss of signal alarm 5 lof loss of frame alarm 4 lop loss of pointer alarm 3 hpais higher-order path ais 2 hprdi higher-order path rdi 1 uneq unequipped signal 0 slm signal label mismatch alarm
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 638 of 676 pnr25.chapt06.01 august 14, 2000 24.131: irq8 register to indicate active user interrupt requests of this chiplet. for each bit position: 0 = no interrupt request pending. 1 = interrupt request pending. length 8 bits type read/write address 844 power on value - msais msrdi reserved mstim hptim ptrerr 76543210 bit(s) name description 7 msais multiplex section ais 6 msrdi multiplex section rdi 5-3 reserved reserved 2 mstim multiplex section trace identifier mismatch 1 hptim higher-order path trace identifier mismatch 0 ptrerr pointer processing error
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 639 of 676 24.132: m_irq8 register to mask pending user interrupt requests. for each bit position: 0 = the corresponding pending request bit is masked (default). 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8 bits type read/write address 845 power on value x ? 00 ? msais msrdi reserved mstim hptim ptrerr 76543210 bit(s) name description 7 msais multiplex section ais 6 msrdi multiplex section rdi 5-3 reserved reserved 2 mstim multiplex section trace identifier mismatch 1 hptim higher-order path trace identifier mismatch 0 ptrerr pointer processing error
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 640 of 676 pnr25.chapt06.01 august 14, 2000 configuration registers 24.133: conf1 configuration register #1. general ofp_rx configuration signals. length 8 bits type read/write address 848 power on value x ? 3f ? reshunt bellcore j1gra j0gra fifoen graen autrst_sta autrst_int 76543210 bit(s) name description 7 reshunt 0 hunt free running 1 reset hunt to pim 6 bellcore 0 operate according to itu standard 1 operate according to bellcore specification 5 j1gra 0 do not write j1 section trace to gra 1 write j1 section trace to gra 4 j0gra 0 do not write j0 section trace to gra 1 write j0 section trace to gra 3 fifoen 0 do not write c4 payload to fifo 1 write c4 payload to fifo 2 graen 0 do not write soh/poh info to gra 1 write received soh/poh info to gra 1 autrst_sta 0 no action on read access 1 auto-reset status register upon read access 0 autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 641 of 676 24.134: conf2 configuration register #2. soh processing configuration signals. length 8 bits type read/write address 849 power on value x ? 00 ? reserved k2en s1en m1en oproc 76543210 bit(s) name description 7-4 reserved reserved 3 k2en 0 disable k2 ais processing 1 enable k2 ais processing 2 s1en 0 disable s1 synchronization status processing 1 enable s1 synchronization status processing 1 m1en 0 disable m1 rei processing 1 enable m1 rei processing 0 j0proc 0 disable j0 section trace processing 1 enable j0 section trace processing
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 642 of 676 pnr25.chapt06.01 august 14, 2000 24.135: conf3 configuration register #3. poh byte processing configuration signals. length 8 bits type read/write address 84a power on value x ? 00 ? reserved c2en g1en j1mode64 j1proc 76543210 bit(s) name description 7-4 reserved 3 c2en 0 disable c2 signal label processing 1 enable c2 signal label processing 2 g1en 0 disable g1 path status processing 1 enable g1 path status processing 1 j1mode64 0 16-byte j1 trace 1 64-byte j1 trace 0 j1proc 0 disable j1 path trace processing 1 enable j1 path trace processing
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 643 of 676 24.136: conf4 configuration register #4. aps processing configuration signals. length 8 bits type read/write address 84b power on value x ? 00 ? sfen aaen sdfen prior chnum (7-4) 76543210 bit(s) name description 7 sfen 0 disable sf k2 ms_rdi processing 1 enable sf k2 ms_rdi processing 6 aaen 0 disable automatic alarm processing for k2 1 enable automatic alarm processing for k2 5 sdfen 0 disable automatic sdf k1 processing 1 enable automatic sdf k1 processing 4 prior priority level 3-0 chnum(7-4) channel number
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 644 of 676 pnr25.chapt06.01 august 14, 2000 24.137: conf7 configuration register #7. miscellaneous ofp_rx configuration signals. length 8 bits type read/write address 84e power on value x ? 20 ? edgemode clkmode opmode dccen outnum (7-6) innum (7-6) 76543210 bit(s) name description 7 edgemode 0 active falling edge 1 active rising edge 6 clkmode 0 continuous clock mode 1 strobed clock mode 5 opmode 0 dcc 1 channel selected 1 dcc 2 channel selected 4 dccen 0 disable dcc processing 1 enable dcc processing 3-2 outnum(7-6) number of s for in-frame to out-of-frame transition 1-0 innum(7-6) number of s for out-of-frame to in-frame transition
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt06.01 august 14, 2000 overhead frame processor architecture: receive direction page 645 of 676 24.138: conf8 configuration register #8. pattern register signals. 24.139: conf9 configuration register #9. pattern register signals. length 8 bits type read/write address 84f power on value x ? fe ? fscrrx 76543210 bit(s) name description 7-0 fscrrx(7-0) frame descrambling reload pattern length 8 bits type read/write address 850 power on value x ? 13 ? slexpct 76543210 bit(s) name description 7-0 slexpct(7-0) expected signal label
IBM3206K0424 ibm processor for network resources preliminary overhead frame processor architecture: receive direction page 646 of 676 pnr25.chapt06.01 august 14, 2000
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 page 647 of 676 memory map for registers and arrays address entity elements accessed xxxx 0000 - ff pcint registers xxxx 0100 - ff gpdma registers & array xxxx 0400 - ff intst registers xxxx 0500 - ff crset registers xxxx 0600 - 8ff dmaqs registers & array xxxx 0900 - ff comet/pakit registers xxxx 0a00 - ff chksm registers xxxx 0b00 - ff linkc registers xxxx 0d00 - ff vimem registers xxxx 0e00 - ff arbit registers xxxx 1000 - 1ff bcach registers & array xxxx 1200 - 3ff csked registers & array xxxx 1400 - 5ff segbf registers & array xxxx 1600 - 7ff reasm registers & array xxxx 1800 - fff rxque registers & arrays xxxx 2000 - fff npbus/framr registers & external eeprom xxxx 3000 - fff pools registers & arrays xxxx 4000 - fff pcore registers & arrays xxxx 5000 - fff ppocm arrays
IBM3206K0424 ibm processor for network resources preliminary page 648 of 676 pnr25.chapt07.01 august 14, 2000 signal pin listing by signal name (page 1 of 5) signal name grid position book signal name grid position book signal name grid position book bist0di1 0w01 k cmclk(4) 0n01 b cmdata(38) 0e04 c cm0cs(0) ad17 c cmclke ad13 c cmdata(4) 0l03 c cm0cs(1) 0y15 c cmdata(0) 0m09 c cmdata(5) 0l09 c cm0cs(2) ae16 c cmdata(1) 0n03 c cmdata(6) 0m03 c cm0cs(3) ae15 c cmdata(10) 0l05 c cmdata(7) 0l04 c cm0dqm(0) 0u14 c cmdata(11) 0l06 c cmdata(8) 0l08 c cm0dqm(1) ab15 c cmdata(12) 0j02 c cmdata(9) 0k03 c cm0dqm(2) ae14 c cmdata(13) 0l07 c cmsyncas(0) 0u15 c cm0dqm(3) ac14 c cmdata(14) 0l10 c cmsyncas(1) ac17 c cmaddr(0) 0w02 c cmdata(15) 0k05 c cmsynras(0) ae18 c cmaddr(1) 0u03 c cmdata(16) 0j05 c cmsynras(1) aa17 c cmaddr(10) 0r05 c cmdata(17) 0h01 c cmwe(0) 0w13 c cmaddr(11) 0p03 c cmdata(18) 0j03 c cmwe(1) aa13 c cmaddr(12) 0r03 c cmdata(19) 0k09 c cts 0p07 t cmaddr(13) 0r04 c cmdata(2) 0n02 c dsr 0w03 o cmaddr(14) 0r02 c cmdata(20) 0j04 c dtr aa05 o cmaddr(15) 0n04 c cmdata(21) 0j07 c enstate(0) 0c24 a cmaddr(16) 0n07 c cmdata(22) 0h03 c enstate(1) 0b25 a cmaddr(17) 0n08 c cmdata(23) 0k07 c enstate(10) ae24 a cmaddr(18) 0m11 c cmdata(24) 0g02 c enstate(11) ad21 a cmaddr(19) 0n10 c cmdata(25) 0f01 c enstate(12) ae04 a cmaddr(2) 0r08 c cmdata(26) 0j09 c enstate(13) ad05 a cmaddr(20) 0n06 c cmdata(27) 0h05 c enstate(14) ae01 a cmaddr(3) 0u02 c cmdata(28) 0j06 c enstate(15) ac02 a cmaddr(4) 0t05 c cmdata(29) 0g04 c enstate(16) ad01 a cmaddr(5) 0u04 c cmdata(3) 0l02 c enstate(17) ab01 a cmaddr(6) 0r07 c cmdata(30) 0f03 c enstate(18) aa02 a cmaddr(7) 0t03 c cmdata(31) 0j08 c enstate(19) 0b01 a cmaddr(8) 0r06 c cmdata(32) 0g05 c enstate(2) 0e24 a cmaddr(9) 0n09 c cmdata(33) 0h07 c enstate(20) 0e02 a cmclk(0) 0j01 b cmdata(34) 0d03 c enstate(21) 0d01 a cmclk(1) 0k01 b cmdata(35) 0f05 c enstate(22) 0c02 a cmclk(2) 0l01 b cmdata(36) 0g06 c enstate(23) 0b03 a cmclk(3) 0m01 b cmdata(37) 0g07 c enstate(24) 0a02 a
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 page 649 of 676 enstate(25) 0a04 a enstate(56) ae23 k fyrdat(12) 0m19 t enstate(26) 0b05 a enstate(57) ac23 k fyrdat(13) 0c19 t enstate(27) 0a22 a enstate(58) ac25 k fyrdat(14) aa14 t enstate(28) 0b21 a enstate(59) aa25 k fyrdat(15) 0w14 t enstate(29) 0a25 a enstate(6) ac24 a fyrdat(2) 0w23 t enstate(3) aa24 a enstate(60) 0c25 k fyrdat(3) ac21 t enstate(30) 0b23 a enstate(61) 0c23 k fyrdat(4) aa21 t enstate(31) 0a24 a enstate(62) 0a23 k fyrdat(5) 0p21 t enstate(32) 0n23 j enstate(63) 0a21 k fyrdat(6) 0m21 t enstate(33) 0r22 j enstate(7) ad23 a fyrdat(7) 0e21 t enstate(34) 0r19 j enstate(8) ae25 a fyrdat(8) 0c21 t enstate(35) 0u22 j enstate(9) ae22 a fyrdat(9) ae19 t enstate(36) 0t21 j fcdp(0) aa20 l fyreop 0l23 l enstate(37) 0u24 j fcdp(1) 0w18 l fyrmod 0l24 l enstate(38) 0r18 j fcgbusy aa19 l fyrpar(0) 0k23 n enstate(39) 0u23 j fcphase(0) ab21 l fyrpar(1) 0m17 n enstate(4) ab25 a fcphase(1) 0y19 l fyrrdb 0r23 n enstate(40) 0w24 j fcsync ac20 l fyrsclkn 0j25 da enstate(41) 0v23 j fy0emp 0l17 n fyrsclkp 0j24 da enstate(42) 0v25 j fy0ful 0j23 n fyrsdatn 0m25 da enstate(43) 0t19 j fy0renb 0h25 i fyrsdatp 0m23 da enstate(44) 0r17 j fy0tenb 0j21 i fyrsoc 0r24 l enstate(45) 0r16 j fydiscrd 0k21 l fytadr(0) 0n20 g enstate(46) 0u20 j fydtct 0l18 n fytadr(1) 0n21 g enstate(47) 0u21 j fyradr(0) 0l19 g fytadr(2) 0t25 g enstate(48) 0v21 j fyradr(1) 0l20 g fytadr(3) 0n22 g enstate(49) 0w22 j fyradr(2) 0k25 g fytadr(4) 0n24 g enstate(5) ad25 a fyradr(3) 0l25 g fytca 0n25 l enstate(50) aa01 k fyradr(4) 0l21 g fytdat(0) 0f21 j enstate(51) ac01 k fyrca 0l22 l fytdat(1) 0k17 j enstate(52) ac03 k fyrdat(0) aa23 t fytdat(10) 0h21 g enstate(53) ae03 k fyrdat(1) 0w25 t fytdat(11) 0m15 g enstate(54) ae05 k fyrdat(10) ac19 t fytdat(12) 0k19 g enstate(55) ae21 k fyrdat(11) 0p19 t fytdat(13) 0h23 g signal pin listing by signal name (page 2 of 5) signal name grid position book signal name grid position book signal name grid position book
IBM3206K0424 ibm processor for network resources preliminary page 650 of 676 pnr25.chapt07.01 august 14, 2000 fytdat(14) 0l16 g mgnt 0c22 d pad(25) 0a18 d fytdat(15) 0j22 g mhaltppc 0u19 n pad(26) 0g19 d fytdat(2) 0g20 j mint2 0j16 d pad(27) 0e20 d fytdat(3) 0g21 j minta 0j17 d pad(28) 0f19 d fytdat(4) 0e22 j mirdy 0h15 d pad(29) 0e19 d fytdat(5) 0j18 j mpcirst aa03 e pad(3) 0g13 d fytdat(6) 0d23 j mpegclk 0c07 t pad(30) 0c20 d fytdat(7) 0g22 j mperr 0c16 d pad(31) 0a20 d fytdat(8) 0j19 g mpllreset aa12 v pad(4) 0h13 d fytdat(9) 0j20 g mpmevent 0y25 f pad(5) 0j13 d fyteop 0r21 h mreq 0d21 d pad(6) 0k13 d fytmod 0p17 h mreq64 0d11 d pad(7) 0d13 d fytpar(0) 0p15 j mserr 0a15 d pad(8) 0b13 d fytpar(1) 0n19 j mstop 0d17 d pad(9) 0a13 d fytsclkn 0r25 da mtrdy 0b17 d pad64(32) 0c04 d fytsclkp 0t23 da nselft ac05 t pad64(33) 0d05 d fytsdatn 0p25 db pad(0) 0c13 d pad64(34) 0a06 d fytsdatp 0p23 db pad(1) 0f13 d pad64(35) 0c06 d fytsoc 0u25 g pad(10) 0c15 d pad64(36) 0e06 d fytwrb 0r20 n pad(11) 0d15 d pad64(37) 0e07 d ibdinh1 0e05 q pad(12) 0a16 d pad64(38) 0b07 d ibdinh2 0a03 r pad(13) 0c14 d pad64(39) 0f07 d ibdrinh 0c01 u pad(14) 0a14 d pad64(40) 0d07 d jtag0rst 0g12 t pad(15) 0e15 d pad64(41) 0g09 d jtagtck 0e12 t pad(16) 0j15 d pad64(42) 0f09 d jtagtdi 0e14 t pad(17) 0k15 d pad64(43) 0e08 d jtagtdo 0a07 k pad(18) 0g16 d pad64(44) 0j10 d jtagtms 0g14 t pad(19) 0h17 d pad64(45) 0g08 d jtcomply 0c03 m pad(2) 0l14 d pad64(46) 0h09 d leaktst 0a05 s pad(20) 0g18 d pad64(47) 0g10 d mack64 0c10 d pad(21) 0f17 d pad64(48) 0c08 d mdevsel 0e16 d pad(22) 0e17 d pad64(49) 0k11 d mextpmevent 0g15 n pad(23) 0e18 d pad64(50) 0d09 d mframe 0c17 d pad(24) 0c18 d pad64(51) 0j11 d signal pin listing by signal name (page 3 of 5) signal name grid position book signal name grid position book signal name grid position book
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 page 651 of 676 pad64(52) 0c09 d pcbe(1) 0a17 d pmaddr(16) 0u06 c pad64(53) 0a08 d pcbe(2) 0b19 d pmaddr(17) 0p11 c pad64(54) 0e09 d pcbe(3) 0d19 d pmaddr(18) 0p09 c pad64(55) 0e10 d pcbe64(4) 0a12 d pmaddr(19) 0t07 c pad64(56) 0h11 d pcbe64(5) 0c12 d pmaddr(2) 0y05 c pad64(57) 0g11 d pcbe64(6) 0l12 d pmaddr(20) 0v03 c pad64(58) 0a09 d pcbe64(7) 0c11 d pmaddr(3) 0t09 c pad64(59) 0b09 d pciclk 0g25 pll pmaddr(4) 0v07 c pad64(60) 0f11 d pdblclk 0y23 n pmaddr(5) 0r10 c pad64(61) 0a10 d pffcfg(0) 0g01 t pmaddr(6) 0w05 c pad64(62) 0a11 d pffcfg(1) 0g03 t pmaddr(7) 0u08 c pad64(63) 0e11 d pffcfg(2) 0c05 t pmaddr(8) ab03 c pb0eprm 0v17 n pffosc 0e03 t pmaddr(9) 0r09 c pb0phy1 ac22 n pidsel 0g17 d pmclk(0) 0p01 b pb0phy2 ab19 n pintclk 0t17 n pmclk(1) 0r01 b pbaddr16 0w17 n plltune(0) 0g23 p pmclk(2) 0t01 b pbaddr17 0y17 n plltune(1) 0e23 p pmclk(3) 0u01 b pbale1 aa18 n pm0cs(0) 0r14 c pmclk(4) 0v01 b pbale2 0u16 n pm0cs(1) ac15 c pmclke ac11 c pbdata(0) 0w21 j pm0cs(2) ad15 c pmdata(0) ab11 c pbdata(1) 0u18 j pm0cs(3) ae13 c pmdata(1) ae10 c pbdata(2) 0w20 j pm0dqm(0) 0y13 c pmdata(10) 0w11 c pbdata(3) 0v19 j pm0dqm(1) 0v13 c pmdata(11) ab09 c pbdata(4) ab23 j pm0dqm(2) 0u13 c pmdata(12) aa10 c pbdata(5) 0y21 j pm0dqm(3) ad11 c pmdata(13) ad09 c pbdata(6) 0w19 j pm66en 0a19 e pmdata(14) 0v11 c pbdata(7) aa22 j pmaddr(0) aa04 c pmdata(15) ac09 c pbintra ae20 n pmaddr(1) 0w06 c pmdata(16) ad07 c pbphyrst ad19 n pmaddr(10) 0y03 c pmdata(17) ac08 c pbrdrdy 0w16 n pmaddr(11) 0y01 c pmdata(18) ae08 c pbrnwrt ac18 n pmaddr(12) 0u07 c pmdata(19) 0w10 c pbsclk 0t15 n pmaddr(13) 0w04 c pmdata(2) ae12 c pbsdata ab17 j pmaddr(14) 0v05 c pmdata(20) 0u11 c pcbe(0) 0b15 d pmaddr(15) 0u05 c pmdata(21) 0t11 c signal pin listing by signal name (page 4 of 5) signal name grid position book signal name grid position book signal name grid position book
IBM3206K0424 ibm processor for network resources preliminary page 652 of 676 pnr25.chapt07.01 august 14, 2000 pmdata(22) 0y09 c pmsyncas(0) 0v15 c unused_gnd00 0d25 x pmdata(23) aa09 c pmsyncas(1) aa16 c unused_gnd01 0f23 x pmdata(24) aa08 c pmsynras(0) 0w15 c unused_gnd02 0h19 x pmdata(25) ab07 c pmsynras(1) ae17 c unused_gnd03 0n16 x pmdata(26) 0w09 c pmwe(0) 0r12 c unused_gnd04 0n18 x pmdata(27) ae06 c pmwe(1) ac13 c unused_gnd05 aa15 x pmdata(28) ac06 c ppar 0f15 d unused_gnd06 0t13 x pmdata(29) 0u10 c ppar64 0b11 d unused_gnd07 ad03 x pmdata(3) ac12 c ppllout 0u17 j unused_gnd08 0j12 x pmdata(30) 0u09 c ppllti 0w12 v unused_gnd09 0j14 x pmdata(31) 0y07 c pvdda 0e25 pll unused_vdd2500 ac16 y pmdata(32) aa07 c rts 0m07 o unused_vdd2501 ab13 y pmdata(33) 0v09 c rxclk ae07 t unused_vdd2502 ae02 y pmdata(34) aa06 c rxd 0m05 t unused_vdd2503 0n05 y pmdata(35) 0w08 c testm 0e01 w unused_vdd3300 0f25 z pmdata(36) ab05 c txclk ac07 t unused_vdd3301 0g24 z pmdata(37) 0w07 c txd 0p05 o unused_vdd3302 0n17 z pmdata(38) ac04 c unused_vdd3303 0e13 z pmdata(4) aa11 c pmdata(5) 0u12 c pmdata(6) ae09 c pmdata(7) 0y11 c pmdata(8) ae11 c pmdata(9) ac10 c signal pin listing by signal name (page 5 of 5) signal name grid position book signal name grid position book signal name grid position book
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 page 653 of 676 ac timing characteristics phy timing description min max units fytwrb high to fytdat(15:0) 2 10 ns fytwrb high to fytpar(1:0) 2 10 ns fytwrb high to fytsoc, fy0tenb, fytmod, fyteop, fytadr(4:0) 210 ns fytca to fytwrb setup 3 -- ns fytca to fytwrb hold 1 -- ns fy0ful to fytwrb setup 3 -- ns fy0ful to fytwrb hold 1 -- ns fyrrdb high to fyrenb, fyradr(4:0) 2 10 ns fyrdat(15:0) to fyrrdb setup 3 -- ns fyrdat(15:0) to fyrrdb hold 1 -- ns fyrpar(1:0) to fyrrdb setup 3 -- ns fyrpar(1:0) to fyrrdb hold 1 -- ns fyrsoc to fyrrdb setup 3 -- ns fyrsoc to fyrrdb hold 1 -- ns fy0ful to fyrrdb setup 3 -- ns fy0ful to fyrrdb hold 1 -- ns fy0emp to fyrrdb setup 3 -- ns fy0emp to fyrrdb hold 1 -- ns fy0discrd to fyrrdb setup 3 -- ns fy0discrd to fyrrdb hold 1 -- ns fy0dtct to fyrrdb setup 3 -- ns fy0dtct to fyrrdb hold 1 -- ns fyrca to fyrrdb setup 3 -- ns fyrca to fyrrdb hold 1 -- ns fyrmod to fyrrdb setup 3 -- ns fyrmod to fyrrdb hold 1 -- ns fyreop to fyrrdb setup 3 -- ns fyreop to fyrrdb hold 1 -- ns
IBM3206K0424 ibm processor for network resources preliminary page 654 of 676 pnr25.chapt07.01 august 14, 2000 npbus timing description min max units pintclk high to pbdata(7:0) 2 6 ns pintclk high to pbdatap 2 6 ns pintclk high to pbrnwrt 2 6 ns pintclk high to pbrdrdy 2 6 ns pintclk high to pbaddr(15:0) 2 6 ns pbdata(7:0) to pintclk setup 15 -- ns pbdata(7:0) to pintclk hold 0 -- ns pbdatap to pintclk setup 15 -- ns pbdatap to pintclk hold 0 -- ns pbrdrdy to pintclk setup 15 -- ns pbrdrdy to pintclk hold 0 -- ns pbrnwrt to pintclk setup 15 -- ns pbrnwrt to pintclk hold 0 -- ns i/o pci bus timing (page 1 of 2) description min max units pciclk high to pad(31:0) 2 6 ns pciclk high to ppar 2 6 ns pciclk high to pcbe(3:0) 2 6 ns pciclk high to mframe 2 6 ns pciclk high to mtrdy 2 6 ns pciclk high to mirdy 2 6 ns pciclk high to mstop 2 6 ns pciclk high to mdevsel 2 6 ns pciclk high to mreq 2 6 ns pciclk high to mperr 2 6 ns pciclk high to mserr 2 6 ns pciclk high to minita 2 6 ns pciclk high to mint2 2 6 ns pciclk high to mreq64 2 6 ns pciclk high to ppar64 2 6 ns pciclk high to pad64(63:32) 2 6 ns pciclk high to mack64 2 6 ns mframe to pciclk setup 3 -- ns mframe to pciclk hold 0 -- ns pcbe(3:0) to pciclk setup 3 -- ns
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 page 655 of 676 pcbe(3:0) to pciclk hold 0 -- ns pad(31:0) to pciclk setup 3 -- ns pad(31:0) to pciclk hold 0 -- ns ppar to pciclk setup 3 -- ns ppar to pciclk hold 0 -- ns mperr to pciclk setup 3 -- ns mperr to pciclk hold 0 -- ns pidsel to pciclk setup 3 -- ns pidsel to pciclk hold 0 -- ns mdevsel to pciclk setup 3 -- ns mdevsel to pciclk hold 0 -- ns mtrdy to pciclk setup 3 -- ns mtrdy to pciclk hold 0 -- ns mirdy to pciclk setup 3 -- ns mirdy to pciclk hold 0 -- ns mstop to pciclk setup 3 -- ns mstop to pciclk hold 0 -- ns mgnt to pciclk setup 3 -- ns mgnt to pciclk hold 0 -- ns pcbe64(7:4) to pciclk setup 3 -- ns pcbe64(7:4) to pciclk hold 0 -- ns i/o pci bus timing (page 2 of 2) description min max units
IBM3206K0424 ibm processor for network resources preliminary synchronous dram timing diagrams page 656 of 676 pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams sdram read cycle (1 of 4) data out cmclk t1 t2 t3 t4 t5 t6 t7 cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs cas latency=2, burst length=1 xxxxxxxx xxxxxx col xxxxxxxxxx row zzzzzzzzzzzzz zzzzzzzzzz t8 t9 (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams page 657 of 676 sdram read cycle (2 of 4) data out t1 t2 t3 t4 t5 t6 t7 cas latency=3, burst length=1 t8 t9 xxx row xxxxxxxxxx col xxxxxx zzzzzzzzzzzzzzzzzzz zzzzz cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 ibm processor for network resources preliminary synchronous dram timing diagrams page 658 of 676 pnr25.chapt07.01 august 14, 2000 sdram read cycle (3 of 4) xxxxxxxx t1 t2 t3 t4 t5 t6 t7 t8 zzzzzzzz zzzzzz z data out xxxxxxxx row col cas latency=2, burst length=2 cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams page 659 of 676 sdram read cycle (4 of 4) 12345 67 cas latency=3, burst length=2 89 row xxx col xxxxxxxx zzzzzzzzzz data out zzzzz cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 ibm processor for network resources preliminary synchronous dram timing diagrams page 660 of 676 pnr25.chapt07.01 august 14, 2000 sdram write cycle (1 of 4) t1 zzzzzzzzzzz t2 t3 t4 t5 t6 t7 xxxxxxxx xxxxxx col xxxxxxxxxx row zzzzzzzz xxxxxx data cas latency=2, burst length=1 bank address cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams page 661 of 676 sdram write cycle (2 of 4) t1 xxxxxx t2 t3 t4 t5 t6 t7 cas latency=3, burst length=1 xxxxxxxx row zzzzzzzz xxxxxxxxxx col xxxxxx zzzzzzzzzzz data cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 ibm processor for network resources preliminary synchronous dram timing diagrams page 662 of 676 pnr25.chapt07.01 august 14, 2000 sdram write cycle (3 of 4) data t1 t2 t3 t4 t5 t6 t7 cas latency=2, burst length=2 xxxxxxxx row col xxxxxxxxx zzzzzzzzzz zzzzzzzzzzz 00000000 cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams page 663 of 676 sdram write cycle (4 of 4) t9 t1 t2 t3 t4 t5 t6 t7 cas latency=3, burst length=2 t8 xxxxxxxx row col xxxxxxx zzzzzzzz 00000000 data zzzzzzzz cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 ibm processor for network resources preliminary synchronous dram timing diagrams page 664 of 676 pnr25.chapt07.01 august 14, 2000 sdram write of 64-byte burst with cas latency=2 cas latency=2, burst length=2 t1 t2 t3 t4 t5 t17 t18 xx row col0 col1 col2 zzzzzzzz data 0 data 1 data 2 t19 t20 t21 t22 t23 t24 t25 data 14 data 15 zzzzzzzz col 14 col 15 xxxxxxxx t6 cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 synchronous dram timing diagrams page 665 of 676 sdram write of 64-byte burst with cas latency=3 cas latency=3, burst length=2 t1 t2 t3 t4 t5 t18 t19 xx t20 t21 t22 data 14 data 15 t6 xxxxxxxx t23 col0 row col1 col 14 col 15 zzzzzzzz data 1 data 0 zzzzzzzz cmclk cm0dqm cmwe cmsyncas cm0cs cmsynras cmaddr cm0cs (4:0) (1:0) (1:0) (1:0) (3:0) (3:2) cmdata bank address
IBM3206K0424 ibm processor for network resources preliminary sram timing diagrams page 666 of 676 pnr25.chapt07.01 august 14, 2000 sram timing diagrams sram read cycle cmclk (4:0) cmwe cmaddr cmdata (35:0) zzzzzzzz xxxxxxxx zzz 56 1234 addr xxxxxxxx cm0cs cmsynras (1:0) data (bit 1) (bit 0) cmsyncas (1:0)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 sram timing diagrams page 667 of 676 sram write cycle f xxxxxxxx addr t5 t6 t1 t2 t3 t4 zzzzzzzz data zzzzzzzz f 0 cmclk (4:0) cmwe cmaddr cmdata (35:0) cm0cs cmsynras (1:0) (bit 1) (bit 0) cmsyncas (1:0)
IBM3206K0424 ibm processor for network resources preliminary sram timing diagrams page 668 of 676 pnr25.chapt07.01 august 14, 2000 sram read cycle with byte enables 56 1234 f addr 0 zzzzzzzz xxxxxxxx f zzzzzzzz data xxxxxxxx cmclk (4:0) cmwe cmaddr cmdata (35:0) cm0cs cmsynras (1:0) (bit 1) (bit 0) cmsyncas (1:0)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 sram timing diagrams page 669 of 676 sram write cycle with byte enables t5 t6 t1 t2 t3 t4 data zzzzzzzz f addr 0 zzzzzzzz xxxxxxxx f cmclk (4:0) cmwe cmaddr cmdata (35:0) cm0cs cmsynras (1:0) (bit 1) (bit 0) cmsyncas (1:0)
IBM3206K0424 ibm processor for network resources preliminary eprom timing diagrams page 670 of 676 pnr25.chapt07.01 august 14, 2000 eprom timing diagrams parallel eprom read t1 t3 t5 t7 t9 pintclk pbphy1 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbeprm pbdata t11 t13 t15 t17 (7:0) ? 1 ? hi-z data address enstate (47:32) (address 15:0) t19 hi-z :h or l
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 eprom timing diagrams page 671 of 676 parallel eprom write t1 t3 t5 t7 t9 t11 t13 t15 t17 pintclk pbphy1 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbeprm pbdata (7:0) address enstate (47:32) (address 15:0) :h or l data
IBM3206K0424 ibm processor for network resources preliminary eprom timing diagrams page 672 of 676 pnr25.chapt07.01 august 14, 2000 serial eprom read serial eprom read follows i2c bus protocol pbsdata is single sequence split over several lines) pbsclk pbsdata pbsdata pbsdata pbsdata (continued) (continued) (continued)
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 eprom timing diagrams page 673 of 676 serial eprom write pbsclk pbsdata pbsdata pbsdata (continued) (continued) serial eprom write follows i2c bus protocol pbsdata is single sequence split over several lines)
IBM3206K0424 ibm processor for network resources preliminary phy timing diagrams page 674 of 676 pnr25.chapt07.01 august 14, 2000 phy timing diagrams phy read t1 t3 t5 t7 t9 t21 t22 t23 t24 pintclk pbphy1 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbdata (7:0) enstate (47:32) (address 15:0) address pbeprm data hi-z :h or l
IBM3206K0424 preliminary ibm processor for network resources pnr25.chapt07.01 august 14, 2000 phy timing diagrams page 675 of 676 phy write t1 t3 t5 t7 t9 pintclk pbaddr16 pbaddr17 pbrnwrt pbrdrdy pbdata t21 t22 t23 t24 (7:0) address pbphy1 pbeprm enstate (47:32) (address 15:0) :h or l data
IBM3206K0424 ibm processor for network resources preliminary phy timing diagrams page 676 of 676 pnr25.chapt07.01 august 14, 2000 revision log rev. description 8/31/99 initial release (00). 8/14/00 first revision (01). in the input/output definitions section, corrected the definition of rxclk in clock, configuration, and lssd pin descriptions on page 58. changed page numbering of contents from roman to numeric.

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